From eeb565de1005927bcfd7bde15bd1d4e09394cb78 Mon Sep 17 00:00:00 2001
From: azidar
Date: Mon, 25 Jan 2016 15:59:59 -0800
Subject: Added verilog rename pass

---
 spec/spec.tex                    |  4 ++--
 src/main/stanza/compilers.stanza |  1 +
 src/main/stanza/passes.stanza    | 30 ++++++++++++++++++++++++++++++
 test/features/VerilogRename.fir  | 18 ++++++++++++++++++
 4 files changed, 51 insertions(+), 2 deletions(-)
 create mode 100644 test/features/VerilogRename.fir

diff --git a/spec/spec.tex b/spec/spec.tex
index aaf2577d..93d62525 100644
--- a/spec/spec.tex
+++ b/spec/spec.tex
@@ -1797,8 +1797,8 @@ The concrete syntax of FIRRTL is defined in section \ref{syntax_tree}. Productio
 %   - Add memory read-under-write flag  ; probably overengineering, but could be a wash
 %   - Add partial connect algorithm     ; 
 %   - Add oriented types to type checker
-%   - Add is invalid                    ; good
-%   - Add validif                       ; good
+%   - *FINISHED* Add is invalid                    ; good
+%   - *FINISHED* Add validif                       ; good
 %   - Add UBits                         ; andrew doesn't care, favors overloading UInt
 %   - Add SBits
 %   - *FINISHED* Add Mux expression                ; that's lovely, need glitch-free mux for clock types
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index 1140e635..3ca4f8da 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -98,6 +98,7 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
       InferWidths()
       CheckWidths()
       ;===============
+      VerilogRename() 
       Verilog(with-output(c)) 
       ;===============
       ;ToRealIR()             
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index dbb489c4..3fba76de 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -2315,6 +2315,36 @@ defn lower-types (c:Circuit) -> Circuit :
    Circuit{info(c),_,main(c)} $
       for m in modules(c) map : lower-types(m)
 
+
+
+;============ RENAME VERILOG KEYWORDS =============
+
+public defstruct VerilogRename <: Pass
+public defmethod pass (b:VerilogRename) -> (Circuit -> Circuit) : verilog-rename
+public defmethod name (b:VerilogRename) -> String : "Verilog Rename"
+public defmethod short-name (b:VerilogRename) -> String : "Verilog Rename"
+
+defn verilog-rename (c:Circuit) -> Circuit :
+   defn verilog-rename-n (n:Symbol) -> Symbol :
+      if key?(v-keywords,n) : symbol-join([n `$])
+      else : n
+   defn verilog-rename-e (e:Expression) -> Expression :
+      match(e) :
+        (e:WRef) : WRef(verilog-rename-n(name(e)),type(e),kind(e),gender(e))
+        (e) : map(verilog-rename-e,e)
+   defn verilog-rename-s (s:Stmt) -> Stmt :
+      map{verilog-rename-n,_} $
+         map{verilog-rename-e,_} $
+            map(verilog-rename-s,s)
+      
+   Circuit{info(c),_,main(c)} $
+      for m in modules(c) map : 
+         val ports* = for p in ports(m) map :
+            Port(info(p),verilog-rename-n(name(p)),direction(p),type(p))
+         match(m) :
+            (m:InModule) : InModule(info(m),name(m),ports*,verilog-rename-s(body(m)))
+            (m:ExModule) : m
+
 ;============ VERILOG ==============
 
 public defstruct Verilog <: Pass :
diff --git a/test/features/VerilogRename.fir b/test/features/VerilogRename.fir
new file mode 100644
index 00000000..f8fceaa9
--- /dev/null
+++ b/test/features/VerilogRename.fir
@@ -0,0 +1,18 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+circuit Top :
+   module Top :
+      input with : Clock
+      output unsigned : Clock
+      wire trireg : Clock
+      unsigned <= with
+      trireg <= with
+
+;CHECK: Verilog Rename
+
+;CHECK: input with$ : Clock
+;CHECK: output unsigned$ : Clock
+;CHECK: wire trireg$ : Clock
+;CHECK: trireg$ <= with$
+;CHECK: unsigned$ <= with$   
+
+;CHECK: Done!
-- 
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