From c561cb225ed564c83ea636644af96fd2e6dee0ab Mon Sep 17 00:00:00 2001
From: azidar
Date: Fri, 28 Aug 2015 13:21:05 -0700
Subject: Moved check type and check kind after check gender

---
 src/main/stanza/compilers.stanza   | 4 ++--
 src/main/stanza/errors.stanza      | 3 ++-
 src/main/stanza/passes.stanza      | 3 +--
 test/passes/infer-types/bundle.fir | 6 +++---
 test/passes/infer-types/gcd.fir    | 8 ++++----
 test/passes/to-verilog/shr.fir     | 2 +-
 6 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index b9a3028a..1e978a2e 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -49,11 +49,11 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
       TempElimination()        ;R
       ToWorkingIR()            ;R -> W
       ResolveKinds()           ;W
-      CheckKinds()             ;W
       InferTypes()             ;R
-      CheckTypes()             ;R
       ResolveGenders()         ;W
       CheckGenders()           ;W
+      CheckKinds()             ;W
+      CheckTypes()             ;R
       ExpandAccessors()        ;W
       LowerToGround()          ;W
       ExpandIndexedConnects()  ;W
diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza
index 69073f9f..4bcf8dd7 100644
--- a/src/main/stanza/errors.stanza
+++ b/src/main/stanza/errors.stanza
@@ -653,7 +653,8 @@ public defn check-types (c:Circuit) -> Circuit :
             (s:Connect) : 
                if type(loc(s)) != type(exp(s)) : add(errors,InvalidConnect(info(s)))
             (s:BulkConnect) : 
-               if not bulk-equals?(type(loc(s)),type(exp(s))) : add(errors,InvalidConnect(info(s)))
+               if not bulk-equals?(type(loc(s)),type(exp(s))) : 
+                  add(errors,InvalidConnect(info(s)))
             (s:OnReset) : 
                if type(loc(s)) != type(exp(s)) : add(errors,InvalidConnect(info(s)))
                if has-flip?(type(loc(s))) : add(errors,OnResetIllegalFlips(info(s)))
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index fead9ac2..99fb8172 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -217,7 +217,7 @@ defn hasWidth (e:?) :
 defn hasType (e:?) :
    e typeof Ref|Subfield|Index|DoPrim|WRef|WSubfield
       |WIndex|DefWire|DefRegister|DefMemory|DefPoison
-      |VectorType|Port|Field|UIntValue|SIntValue
+      |VectorType|Port|UIntValue|SIntValue
 
 defn hasKind (e:?) :
    e typeof WRef
@@ -600,7 +600,6 @@ defn resolve-kinds (c:Circuit) :
       kinds[name(m)] = ModuleKind()
       for p in ports(m) do :
          kinds[name(p)] = PortKind()
-      println(name(m))
       match(m) : 
          (m:InModule) : find-stmt(body(m))
          (m:ExModule) : false
diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir
index 50f1c84b..89f9ac22 100644
--- a/test/passes/infer-types/bundle.fir
+++ b/test/passes/infer-types/bundle.fir
@@ -6,8 +6,8 @@ circuit top :
       wire z : { x : UInt, flip y: SInt}
       z.x := UInt(1)
       z.y := SInt(1)
-      node x = z.x            ;CHECK: node x = z@<t:{ x : UInt@<t:UInt>, flip y : SInt@<t:SInt>}>.x@<t:UInt>
-      node y = z.y            ;CHECK: node y = z@<t:{ x : UInt@<t:UInt>, flip y : SInt@<t:SInt>}>.y@<t:SInt>
+      node x = z.x            ;CHECK: node x = z@<t:{ x : UInt, flip y : SInt}>.x@<t:UInt>
+      node y = z.y            ;CHECK: node y = z@<t:{ x : UInt, flip y : SInt}>.y@<t:SInt>
       wire a : UInt<3>[10]    ;CHECK: wire a : UInt<3>[10]@<t:UInt>@<t:UInt<3>[10]@<t:UInt>>
       a[0] := UInt(1)
       a[1] := UInt(1)
@@ -22,8 +22,8 @@ circuit top :
       node b = a[2]           ;CHECK: node b = a@<t:UInt<3>[10]@<t:UInt>>[2]@<t:UInt>
       read accessor c = a[UInt(3)] ;CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt("h3")@<t:UInt>]
 ; CHECK: Finished Infer Types
+
 ; CHECK: Resolve Genders 
 ; CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt("h3")@<t:UInt>]
 ; CHECK: Finished Resolve Genders 
 
-
diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir
index fa14eb38..24860b91 100644
--- a/test/passes/infer-types/gcd.fir
+++ b/test/passes/infer-types/gcd.fir
@@ -24,13 +24,13 @@ circuit top :
       when gt(x, y) :
       ;CHECK: when gt(x@<t:UInt>, y@<t:UInt>)@<t:UInt> :
          inst s of subtracter
-         ;CHECK: inst s of subtracter@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>}>
+         ;CHECK: inst s of subtracter@<t:{flip x : UInt, flip y : UInt,  z : UInt}>
          s.x := x
          s.y := y
          x := s.z
-         ;CHECK: s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>}>.x@<t:UInt> := x@<t:UInt>
-         ;CHECK: s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>}>.y@<t:UInt> := y@<t:UInt>
-         ;CHECK: x@<t:UInt> := s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>}>.z@<t:UInt>      
+         ;CHECK: s@<t:{flip x : UInt, flip y : UInt,  z : UInt}>.x@<t:UInt> := x@<t:UInt>
+         ;CHECK: s@<t:{flip x : UInt, flip y : UInt,  z : UInt}>.y@<t:UInt> := y@<t:UInt>
+         ;CHECK: x@<t:UInt> := s@<t:{flip x : UInt, flip y : UInt,  z : UInt}>.z@<t:UInt>      
       else :
          inst s2 of subtracter
          s2.x := x
diff --git a/test/passes/to-verilog/shr.fir b/test/passes/to-verilog/shr.fir
index f710dc51..c4b4e4d2 100644
--- a/test/passes/to-verilog/shr.fir
+++ b/test/passes/to-verilog/shr.fir
@@ -1,7 +1,7 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p cTd 2>&1 |  tee %s.out | FileCheck %s
 
 ;CHECK: Infer Widths
-;CHECK: node s1_addr = cat(dtlb<t:{ resp$ppn : UInt<20><t:UInt<20>>}>.resp$ppn<t:UInt<20>>, bits(s1_req$addr<t:UInt<40>>, 11, 0)<t:UInt<12>>)<t:UInt<32>>
+;CEHCK: node s1_addr = cat(dtlb<t:{ resp$ppn : UInt<20>}>.resp$ppn<t:UInt<20>>, bits(s1_req$addr<t:UInt<40>>, 11, 0)<t:UInt<12>>)<t:UInt<32>>
 ;CHECK: Finished Infer Widths
 
 circuit HellaCache : 
-- 
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