From b7d8744a4d799c09f86eee8876ff139afac6b688 Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Thu, 21 Feb 2019 12:13:10 -0800
Subject: Added mergify badge to README (#1027)

---
 README.md | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/README.md b/README.md
index 2a15e1ca..dd792f82 100644
--- a/README.md
+++ b/README.md
@@ -4,6 +4,11 @@
 
 [![Join the chat at https://gitter.im/freechipsproject/firrtl](https://badges.gitter.im/freechipsproject/firrtl.svg)](https://gitter.im/freechipsproject/firrtl?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
 [![Build Status](https://travis-ci.org/freechipsproject/firrtl.svg?branch=master)](https://travis-ci.org/freechipsproject/firrtl)
+[![Mergify Status][mergify-status]][mergify]
+
+[mergify]: https://mergify.io
+[mergify-status]: https://gh.mergify.io/badges/:freechipsproject/:firrtl.png?style=cut
+
 #### Flexible Internal Representation for RTL
 
  Firrtl is an intermediate representation (IR) for digital circuits designed as a platform for writing circuit-level transformations.
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