From a7ef69180836133873be538ba0a59adcd6838032 Mon Sep 17 00:00:00 2001 From: Aditya Naik Date: Wed, 29 May 2024 17:21:32 -0700 Subject: Make it publishable --- src/main/scala/firrtl/Mappers.scala | 28 +++++++++++----------- .../firrtl/backends/verilog/VerilogEmitter.scala | 2 +- .../passes/memlib/ResolveMemoryReference.scala | 4 ++-- src/main/scala/firrtl/traversals/Foreachers.scala | 20 ++++++++-------- 4 files changed, 27 insertions(+), 27 deletions(-) diff --git a/src/main/scala/firrtl/Mappers.scala b/src/main/scala/firrtl/Mappers.scala index 55adf29f..e4df60d8 100644 --- a/src/main/scala/firrtl/Mappers.scala +++ b/src/main/scala/firrtl/Mappers.scala @@ -7,10 +7,10 @@ import firrtl.ir._ // TODO: Implement remaining mappers and recursive mappers object Mappers { // ********** Port Mappers ********** - private trait PortMagnet { + trait PortMagnet { def map(p: Port): Port } - private object PortMagnet { + object PortMagnet { implicit def forType(f: Type => Type): PortMagnet = new PortMagnet { override def map(port: Port): Port = port.mapType(f) } @@ -23,10 +23,10 @@ object Mappers { } // ********** Stmt Mappers ********** - private trait StmtMagnet { + trait StmtMagnet { def map(stmt: Statement): Statement } - private object StmtMagnet { + object StmtMagnet { implicit def forStmt(f: Statement => Statement): StmtMagnet = new StmtMagnet { override def map(stmt: Statement): Statement = stmt.mapStmt(f) } @@ -49,10 +49,10 @@ object Mappers { } // ********** Expression Mappers ********** - private trait ExprMagnet { + trait ExprMagnet { def map(expr: Expression): Expression } - private object ExprMagnet { + object ExprMagnet { implicit def forExpr(f: Expression => Expression): ExprMagnet = new ExprMagnet { override def map(expr: Expression): Expression = expr.mapExpr(f) } @@ -68,10 +68,10 @@ object Mappers { } // ********** Type Mappers ********** - private trait TypeMagnet { + trait TypeMagnet { def map(tpe: Type): Type } - private object TypeMagnet { + object TypeMagnet { implicit def forType(f: Type => Type): TypeMagnet = new TypeMagnet { override def map(tpe: Type): Type = tpe.mapType(f) } @@ -84,10 +84,10 @@ object Mappers { } // ********** Width Mappers ********** - private trait WidthMagnet { + trait WidthMagnet { def map(width: Width): Width } - private object WidthMagnet { + object WidthMagnet { implicit def forWidth(f: Width => Width): WidthMagnet = new WidthMagnet { override def map(width: Width): Width = width match { case mapable: HasMapWidth => mapable.mapWidth(f) // WIR @@ -100,10 +100,10 @@ object Mappers { } // ********** Module Mappers ********** - private trait ModuleMagnet { + trait ModuleMagnet { def map(module: DefModule): DefModule } - private object ModuleMagnet { + object ModuleMagnet { implicit def forStmt(f: Statement => Statement): ModuleMagnet = new ModuleMagnet { override def map(module: DefModule): DefModule = module.mapStmt(f) } @@ -122,10 +122,10 @@ object Mappers { } // ********** Circuit Mappers ********** - private trait CircuitMagnet { + trait CircuitMagnet { def map(module: Circuit): Circuit } - private object CircuitMagnet { + object CircuitMagnet { implicit def forModules(f: DefModule => DefModule): CircuitMagnet = new CircuitMagnet { override def map(circuit: Circuit): Circuit = circuit.mapModule(f) } diff --git a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala index 2634a8e1..30d2e891 100644 --- a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala +++ b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala @@ -511,7 +511,7 @@ class VerilogEmitter extends SeqTransform with Emitter { } private val emissionAnnos = annotations.collect { - case m: SingleTargetAnnotation[ReferenceTarget] @unchecked & EmissionOption => m + case m: SingleTargetAnnotation[ReferenceTarget] @unchecked with EmissionOption => m } annotations.foreach { diff --git a/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala b/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala index b916842f..a7dba3e9 100644 --- a/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala +++ b/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala @@ -25,7 +25,7 @@ class ResolveMemoryReference extends Transform with DependencyAPIMigration { /** Helper class for determining when two memories are equivalent while igoring * irrelevant details like name and info */ - private class WrappedDefAnnoMemory(val underlying: DefAnnotatedMemory) { + class WrappedDefAnnoMemory(val underlying: DefAnnotatedMemory) { // Remove irrelevant details for comparison private def generic = underlying.copy(info = NoInfo, name = "", memRef = None) override def hashCode: Int = generic.hashCode @@ -37,7 +37,7 @@ class ResolveMemoryReference extends Transform with DependencyAPIMigration { private def wrap(mem: DefAnnotatedMemory) = new WrappedDefAnnoMemory(mem) // Values are Tuple of Module Name and Memory Instance Name - private type AnnotatedMemories = collection.mutable.HashMap[WrappedDefAnnoMemory, (String, String)] + type AnnotatedMemories = collection.mutable.HashMap[WrappedDefAnnoMemory, (String, String)] private def dedupable(noDedups: Map[String, Set[String]], module: String, memory: String): Boolean = noDedups.get(module).map(!_.contains(memory)).getOrElse(true) diff --git a/src/main/scala/firrtl/traversals/Foreachers.scala b/src/main/scala/firrtl/traversals/Foreachers.scala index 22df6579..fda1b2a7 100644 --- a/src/main/scala/firrtl/traversals/Foreachers.scala +++ b/src/main/scala/firrtl/traversals/Foreachers.scala @@ -10,10 +10,10 @@ import language.implicitConversions object Foreachers { /** Statement Foreachers */ - private trait StmtForMagnet { + trait StmtForMagnet { def foreach(stmt: Statement): Unit } - private object StmtForMagnet { + object StmtForMagnet { implicit def forStmt(f: Statement => Unit): StmtForMagnet = new StmtForMagnet { def foreach(stmt: Statement): Unit = stmt.foreachStmt(f) } @@ -36,10 +36,10 @@ object Foreachers { } /** Expression Foreachers */ - private trait ExprForMagnet { + trait ExprForMagnet { def foreach(expr: Expression): Unit } - private object ExprForMagnet { + object ExprForMagnet { implicit def forExpr(f: Expression => Unit): ExprForMagnet = new ExprForMagnet { def foreach(expr: Expression): Unit = expr.foreachExpr(f) } @@ -55,10 +55,10 @@ object Foreachers { } /** Type Foreachers */ - private trait TypeForMagnet { + trait TypeForMagnet { def foreach(tpe: Type): Unit } - private object TypeForMagnet { + object TypeForMagnet { implicit def forType(f: Type => Unit): TypeForMagnet = new TypeForMagnet { def foreach(tpe: Type): Unit = tpe.foreachType(f) } @@ -71,10 +71,10 @@ object Foreachers { } /** Module Foreachers */ - private trait ModuleForMagnet { + trait ModuleForMagnet { def foreach(module: DefModule): Unit } - private object ModuleForMagnet { + object ModuleForMagnet { implicit def forStmt(f: Statement => Unit): ModuleForMagnet = new ModuleForMagnet { def foreach(module: DefModule): Unit = module.foreachStmt(f) } @@ -93,10 +93,10 @@ object Foreachers { } /** Circuit Foreachers */ - private trait CircuitForMagnet { + trait CircuitForMagnet { def foreach(module: Circuit): Unit } - private object CircuitForMagnet { + object CircuitForMagnet { implicit def forModules(f: DefModule => Unit): CircuitForMagnet = new CircuitForMagnet { def foreach(circuit: Circuit): Unit = circuit.foreachModule(f) } -- cgit v1.2.3