From a643cfd338ab6ae7a3b0d9e9f58e6f33c69237ff Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Tue, 3 Aug 2021 12:20:49 -0400 Subject: Require Andr, Orr, Xorr, Neg to have one operand (#2312) Fix an OG bug where Andr, Orr, and Xorr would accept an arbitrary number of operands. Verilog emission doesn't support this and will silently drop all operands after the first. E.g., "andr(a, b)" would emit as "&a". After this commit, "andr(a, b)" will be rejected by checking passes. For archaeological purposes, this appears to have been the behavior dating back to when this was added in d2d3260a. Signed-off-by: Schuyler Eldridge --- src/main/scala/firrtl/passes/CheckHighForm.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/firrtl/passes/CheckHighForm.scala b/src/main/scala/firrtl/passes/CheckHighForm.scala index 05635d00..8a88f827 100644 --- a/src/main/scala/firrtl/passes/CheckHighForm.scala +++ b/src/main/scala/firrtl/passes/CheckHighForm.scala @@ -187,7 +187,7 @@ trait CheckHighFormLike { this: Pass => case AsInterval => correctNum(Option(1), 3) case Andr | Orr | Xorr | Neg => - correctNum(None, 0) + correctNum(Option(1), 0) } } -- cgit v1.2.3