From 903e5ba4502f5c62b1373df7b44ae1ee0dd66388 Mon Sep 17 00:00:00 2001 From: azidar Date: Thu, 2 Jul 2015 11:33:58 -0700 Subject: In progress commit --- src/main/stanza/errors.stanza | 66 ++------ src/main/stanza/firrtl-ir.stanza | 29 ++-- src/main/stanza/ir-parser.stanza | 9 -- src/main/stanza/ir-utils.stanza | 9 -- src/main/stanza/passes.stanza | 276 +++++++++++++++++--------------- src/main/stanza/verilog.stanza | 168 +++++++++++++------ test/passes/expand-whens/reg-dwc.fir | 21 +++ test/passes/expand-whens/reg-dwoc.fir | 21 +++ test/passes/expand-whens/reg-wdc.fir | 20 +++ test/passes/expand-whens/reg-wdoc.fir | 20 +++ test/passes/expand-whens/scoped-reg.fir | 12 +- test/passes/expand-whens/wacc-wdc.fir | 23 +++ 12 files changed, 397 insertions(+), 277 deletions(-) create mode 100644 test/passes/expand-whens/reg-dwc.fir create mode 100644 test/passes/expand-whens/reg-dwoc.fir create mode 100644 test/passes/expand-whens/reg-wdc.fir create mode 100644 test/passes/expand-whens/reg-wdoc.fir create mode 100644 test/passes/expand-whens/wacc-wdc.fir diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza index 229a1406..8c47d112 100644 --- a/src/main/stanza/errors.stanza +++ b/src/main/stanza/errors.stanza @@ -605,11 +605,6 @@ public defn check-types (c:Circuit) -> Circuit : if value(e) >= size(t) : add(errors,IndexTooLarge(info,value(e))) (t) : add(errors,IndexOnNonVector(info)) (e:DoPrim) : check-types-primop(e,errors,info) - (e:ReadPort|WritePort) : - if type(index(e)) != u() : add(errors,IndexNotUInt(info)) - if type(enable(e)) != u() : add(errors,EnableNotUInt(info)) - (e:Register) : - if type(enable(e)) != u() : add(errors,EnableNotUInt(info)) (e:UIntValue|SIntValue) : false e defn check-types-s (s:Stmt) -> Stmt : @@ -649,9 +644,9 @@ defn WrongGender (info:FileInfo,expr:Symbol,wrong:Symbol,right:Symbol) : PassException $ string-join $ [info ": Expression " expr "has gender " wrong " but requires gender " right "."] -defn UnknownGenders (info:FileInfo,name:Symbol) : +defn InferDirection (info:FileInfo,name:Symbol) : PassException $ string-join $ - [info ": Accessor " name " has an unknown gender."] + [info ": Accessor " name " has a direction that requires inference."] ;---------------- Helper Functions -------------- defn dir-to-gender (d:Direction) -> Gender : @@ -678,9 +673,6 @@ public defn check-genders (c:Circuit) -> Circuit : (e:DoPrim) : MALE (e:UIntValue) : MALE (e:SIntValue) : MALE - (e:ReadPort) : MALE - (e:WritePort) : FEMALE - (e:Register) : MALE defn check-genders-e (info:FileInfo,e:Expression,genders:HashTable) -> False : do(check-genders-e{info,_,genders},e) @@ -693,9 +685,6 @@ public defn check-genders (c:Circuit) -> Circuit : check-gender(info,genders,e,MALE) (e:UIntValue) : false (e:SIntValue) : false - (e:ReadPort) : do(check-gender{info,genders,_,MALE},e) - (e:WritePort) : do(check-gender{info,genders,_,MALE},e) - (e:Register) : do(check-gender{info,genders,_,MALE},e) defn check-genders-s (s:Stmt,genders:HashTable) -> False : do(check-genders-e{info(s),_:Expression,genders},s) @@ -707,8 +696,8 @@ public defn check-genders (c:Circuit) -> Circuit : genders[name(s)] = MALE (s:DefMemory) : genders[name(s)] = BI-GENDER (s:DefInstance) : genders[name(s)] = MALE - (s:WDefAccessor) : - if gender(s) == UNKNOWN-GENDER : add(errors,UnknownGenders(info(s),name(s))) + (s:DefAccessor) : + if dir(s) == INFER : add(errors,InferDirection(info(s),name(s))) check-gender(info(s),genders,index(s),MALE) check-gender(info(s),genders,source(s),gender(s)) genders[name(s)] = gender(s) @@ -751,26 +740,6 @@ public defmethod name (b:CheckLowForm) -> String : "Low Form Check" public defmethod short-name (b:CheckLowForm) -> String : "low-form-check" ;----------------- Errors ------------------------ -defn IncorrectRegisterUsage (info:FileInfo) : - PassException $ string-join $ - [info ": Register can only be used on the right side of a connect statement."] - -defn IncorrectReadPortUsage (info:FileInfo) : - PassException $ string-join $ - [info ": ReadPort can only be used on the right side of a connect statement."] - -defn IncorrectWritePortUsage (info:FileInfo) : - PassException $ string-join $ - [info ": WritePort can only be used on the left side of a connect statement."] - -defn NoReg (info:FileInfo,name:Symbol) : - PassException $ string-join $ - [info ": Invalid reg declaration " name ". No reg declarations are allowed in low firrtl."] - -defn NoAccessor (info:FileInfo,name:Symbol) : - PassException $ string-join $ - [info ": Invalid accessor declaration " name ". No accessor declarations are allowed in low firrtl."] - defn InvalidVec (info:FileInfo,name:Symbol) : PassException $ string-join $ [info ": Expression " name " has an illegal vector type."] @@ -781,7 +750,7 @@ defn InvalidBundle (info:FileInfo,name:Symbol) : defn NoWhen (info:FileInfo) : PassException $ string-join $ - [info ": Illegal when statement. No when statements are allowed in low firrtl."] + [info ": Illegal when statement. No when statements with multiple statements are allowed in low firrtl."] defn SingleAssignment (info:FileInfo,name:Symbol) : PassException $ string-join $ @@ -823,9 +792,6 @@ public defn check-low-form (c:Circuit) -> Circuit : check-low-form-t(info,type(f),name(e)) if contains?(mems,name(e)) : check-low-form-t(info,type(type(e) as VectorType),name(e)) - (e:Register) : add(errors,IncorrectRegisterUsage(info)) - (e:ReadPort) : add(errors,IncorrectReadPortUsage(info)) - (e:WritePort) : add(errors,IncorrectWritePortUsage(info)) (e) : check-low-form-t(info,type(e),to-symbol $ to-string(e)) defn check-low-form-s (s:Stmt) -> False : match(s) : @@ -840,27 +806,15 @@ public defn check-low-form (c:Circuit) -> Circuit : add(insts,name(s)) (s:DefNode) : check-correct-exp(info(s),value(s)) - (s:DefRegister) : add(errors,NoReg(info(s),name(s))) - (s:DefAccessor) : add(errors,NoAccessor(info(s),name(s))) - (s:Conditionally) : add(errors,NoWhen(info(s))) + (s:DefRegister) : false + (s:DefAccessor) : false + (s:Conditionally) : + if (not alt(s) typeof EmptyStmt) or (conseq(s) typeof Begin) : add(errors,NoWhen(info(s))) (s:OnReset) : add(errors,NoOnReset(info(s))) (s:BulkConnect) : add(errors,NoBulkConnect(info(s))) (s:Connect) : - match(exp(s)) : - (e:Register) : - check-low-form-t(info(s),type(e),to-symbol $ to-string(e)) - check-correct-exp(info(s),value(e)) - check-correct-exp(info(s),enable(e)) - (e:ReadPort) : - check-low-form-t(info(s),type(e),to-symbol $ to-string(e)) - check-correct-exp(info(s),index(e)) - check-correct-exp(info(s),enable(e)) - (e) : check-correct-exp(info(s),e) + check-correct-exp(info(s),e) match(loc(s)) : - (e:WritePort) : - check-low-form-t(info(s),type(e),to-symbol $ to-string(e)) - check-correct-exp(info(s),index(e)) - check-correct-exp(info(s),enable(e)) (e:Ref|Subfield) : val n* = to-symbol $ to-string $ e if contains?(assigned?,n*) : add(errors,SingleAssignment(info(s),n*)) diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza index aeaecf47..92f955b9 100644 --- a/src/main/stanza/firrtl-ir.stanza +++ b/src/main/stanza/firrtl-ir.stanza @@ -8,14 +8,20 @@ public defmethod info! (x:?) : FileInfo() public val expand-delin = `$ public val gen-delin = `# -public definterface Direction -public val INPUT = new Direction -public val OUTPUT = new Direction +public definterface PortDirection +public val INPUT = new PortDirection +public val OUTPUT = new PortDirection public definterface Flip public val DEFAULT = new Flip public val REVERSE = new Flip +public definterface AccDirection +public val READ = new AccDirection +public val WRITE = new AccDirection +public val INFER = new AccDirection +public val RDWR = new AccDirection + public definterface Width public defstruct UnknownWidth <: Width public defstruct IntWidth <: Width : @@ -83,20 +89,6 @@ public defstruct DoPrim <: Expression : args: List consts: List type: Type with: (as-method => true) -public defstruct ReadPort <: Expression : - mem: Expression - index: Expression - type: Type with: (as-method => true) - enable: Expression -public defstruct WritePort <: Expression : - mem: Expression - index: Expression - type: Type with: (as-method => true) - enable: Expression -public defstruct Register <: Expression : - type: Type with: (as-method => true) - value: Expression - enable: Expression public definterface Stmt public defmulti info (s:Stmt) -> FileInfo @@ -124,6 +116,7 @@ public defstruct DefNode <: Stmt : ;LOW value: Expression public defstruct DefAccessor <: Stmt : info: FileInfo with: (as-method => true) + dir: AccDirection name: Symbol source: Expression index: Expression @@ -168,7 +161,7 @@ public defstruct Field : public defstruct Port : info: FileInfo name: Symbol - direction: Direction + pkind: PKind type: Type public definterface Module diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza index dd7679cc..374cf58c 100644 --- a/src/main/stanza/ir-parser.stanza +++ b/src/main/stanza/ir-parser.stanza @@ -243,15 +243,6 @@ defsyntax firrtl : (t:UIntType) : UIntValue(v, width(t)) (t:SIntType) : SIntValue(v, width(t)) - expterm = (WritePort(?m:#exp, ?i:#exp, ?e:#exp)) : WritePort(m, i, UnknownType(), e) - expterm != (WritePort) : FPE(form, "Invalid syntax for WritePort expression.") - - expterm = (ReadPort(?m:#exp, ?i:#exp, ?e:#exp)) : ReadPort(m, i, UnknownType(), e) - expterm != (ReadPort) : FPE(form, "Invalid syntax for ReadPort expression.") - - expterm = (Register(?v:#exp, ?e:#exp)) : Register(UnknownType(), v, e) - expterm != (Register) : FPE(form, "Invalid syntax for Register expression.") - expterm = (?op:#sym(?es:#exp ... ?ints:#int ... ?rest ...)) : if not empty?(rest) : FPE(rest, "Illegal operands to primitive operator.") diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza index 89de6793..e29bf4ac 100644 --- a/src/main/stanza/ir-utils.stanza +++ b/src/main/stanza/ir-utils.stanza @@ -160,9 +160,6 @@ defmethod print (o:OutputStream, e:Expression) : print-all(o, [op(e) "("]) print-all(o, join(concat(args(e), consts(e)), ", ")) print(o, ")") - (e:ReadPort) : print-all(o, ["ReadPort(" mem(e) ", " index(e) ", " enable(e) ")"]) - (e:WritePort) : print-all(o, ["WritePort(" mem(e) ", " index(e) ", " enable(e) ")"]) - (e:Register) : print-all(o, ["Register(" value(e) ", " enable(e) ")"]) print-debug(o,e) defmethod print (o:OutputStream, c:Stmt) : @@ -275,9 +272,6 @@ defmethod map (f: Expression -> Expression, e:Expression) -> Expression : (e:Subfield) : Subfield(f(exp(e)), name(e), type(e)) (e:Index) : Index(f(exp(e)), value(e), type(e)) (e:DoPrim) : DoPrim(op(e), map(f, args(e)), consts(e), type(e)) - (e:ReadPort) : ReadPort(f(mem(e)), f(index(e)), type(e), f(enable(e))) - (e:WritePort) : WritePort(f(mem(e)), f(index(e)), type(e), f(enable(e))) - (e:Register) : Register(type(e),f(value(e)),f(enable(e))) (e) : e public defmulti map (f: Expression -> Expression, c:?T&Stmt) -> T @@ -320,9 +314,6 @@ defmethod map (f: Type -> Type, c:Expression) -> Expression : (c:Subfield) : Subfield(exp(c),name(c),f(type(c))) (c:Index) : Index(exp(c),value(c),f(type(c))) (c:DoPrim) : DoPrim(op(c),args(c),consts(c),f(type(c))) - (c:ReadPort) : ReadPort(mem(c),index(c),f(type(c)),enable(c)) - (c:WritePort) : WritePort(mem(c),index(c),f(type(c)),enable(c)) - (c:Register) : Register(f(type(c)),value(c),enable(c)) (c) : c public defmulti map (f: Type -> Type, c:?T&Stmt) -> T diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index b2a53a70..6e030d24 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -65,13 +65,6 @@ public defstruct WIndex <: Expression : type: Type with: (as-method => true) gender: Gender with: (as-method => true) -public defstruct WDefAccessor <: Stmt : - info: FileInfo with: (as-method => true) - name: Symbol - source: Expression - index: Expression - gender: Gender - defstruct ConnectToIndexed <: Stmt : info: FileInfo with: (as-method => true) index: Expression @@ -147,6 +140,20 @@ defn to-dir (g:Gender) -> Direction : MALE : INPUT FEMALE : OUTPUT +defn gender (s:DefAccessor) -> Gender : + switch {_ == dir(s)} : + READ : MALE + WRITE : FEMALE + INFER : UNKNOWN-GENDER + RDWR : BI-GENDER + +defn to-acc-dir (g:Gender) -> AccDirection : + switch {_ == g} : + MALE : READ + FEMALE : WRITE + UNKNOWN-GENDER : INFER + BI-GENDER : RDWR + defmulti gender (e:Expression) -> Gender defmethod gender (e:Expression) : MALE @@ -199,14 +206,14 @@ defmethod print (o:OutputStream, k:Kind) : (k:WriteAccessorKind) : "wacc" defn hasGender (e:?) : - e typeof WRef|WSubfield|WIndex|WDefAccessor + e typeof WRef|WSubfield|WIndex defn hasWidth (e:?) : e typeof UIntType|SIntType|UIntValue|SIntValue defn hasType (e:?) : - e typeof Ref|Subfield|Index|DoPrim|WritePort|ReadPort|WRef|WSubfield - |WIndex|DefWire|DefRegister|DefMemory|Register + e typeof Ref|Subfield|Index|DoPrim|WRef|WSubfield + |WIndex|DefWire|DefRegister|DefMemory |VectorType|Port|Field defn hasKind (e:?) : @@ -249,10 +256,6 @@ defmethod print (o:OutputStream, e:WIndex) : print-all(o,[exp(e) "[" value(e) "]"]) print-debug(o,e as ?) -defmethod print (o:OutputStream, s:WDefAccessor) : - print-all(o,["accessor " name(s) " = " source(s) "[" index(s) "]"]) - print-debug(o,s) - defmethod print (o:OutputStream, c:ConnectToIndexed) : print-all(o, [locs(c) "[" index(c) "] := " exp(c)]) print-debug(o,c as ?) @@ -266,8 +269,6 @@ defmethod map (f: Expression -> Expression, e: WSubfield) : defmethod map (f: Expression -> Expression, e: WIndex) : WIndex(f(exp(e)), value(e), type(e), gender(e)) -defmethod map (f: Expression -> Expression, c:WDefAccessor) : - WDefAccessor(info(c),name(c), f(source(c)), f(index(c)), gender(c)) defmethod map (f: Expression -> Expression, c:ConnectToIndexed) : ConnectToIndexed(info(c),f(index(c)), map(f, locs(c)), f(exp(c))) defmethod map (f: Expression -> Expression, c:ConnectFromIndexed) : @@ -330,10 +331,6 @@ defn to-working-ir (c:Circuit) : (e:Subfield) : WSubfield(exp(e), name(e), type(e), UNKNOWN-GENDER) (e:Index) : WIndex(exp(e), value(e), type(e), UNKNOWN-GENDER) (e) : e - defn to-stmt (s:Stmt) : - match(map(to-exp,s)) : - (s:DefAccessor) : WDefAccessor(info(s),name(s),source(s),index(s), UNKNOWN-GENDER) - (s) : map(to-stmt,s) Circuit(info(c),modules*, main(c)) where : val modules* = @@ -423,7 +420,7 @@ defn resolve-kinds (c:Circuit) : (s:DefRegister) : kinds[name(s)] = RegKind() (s:DefInstance) : kinds[name(s)] = InstanceKind() (s:DefMemory) : kinds[name(s)] = MemKind() - (s:WDefAccessor) : kinds[name(s)] = AccessorKind() + (s:DefAccessor) : kinds[name(s)] = AccessorKind() (s) : false map(find-stmt,s) @@ -497,9 +494,6 @@ defn infer-exp-types (e:Expression, l:List>) -> Expression (e:WIndex) : WIndex(exp(e),value(e), get-vector-subtype(type(exp(e))),gender(e)) (e:DoPrim) : lower-and-type-primop(e) ;DoPrim(op(e),args(e),consts(e),get-primop-rettype(e)) - (e:ReadPort) : ReadPort(mem(e),index(e),get-vector-subtype(type(mem(e))),enable(e)) - (e:WritePort) : WritePort(mem(e),index(e),get-vector-subtype(type(mem(e))),enable(e)) - (e:Register) : Register(type(value(e)),value(e),enable(e)) (e:UIntValue|SIntValue) : e defn infer-types (s:Stmt, l:List>) -> [Stmt List>] : @@ -517,7 +511,7 @@ defn infer-types (s:Stmt, l:List>) -> [Stmt List type(s),l)] (s:DefInstance) : [s, List(name(s) => type(module(s)),l)] (s:DefNode) : [s, List(name(s) => type(value(s)),l)] - (s:WDefAccessor) : [s, List(name(s) => get-vector-subtype(type(source(s))),l)] + (s:DefAccessor) : [s, List(name(s) => get-vector-subtype(type(source(s))),l)] (s:Conditionally) : val [s*,l*] = infer-types(conseq(s),l) val [s**,l**] = infer-types(alt(s),l) @@ -624,11 +618,11 @@ defn resolve-genders (c:Circuit) : (s:DefInstance) : get-gender(name(s),MALE) DefInstance(info(s),name(s),resolve-expr(module(s),MALE)) - (s:WDefAccessor) : + (s:DefAccessor) : val gender* = get-gender(name(s),UNKNOWN-GENDER) val index* = resolve-expr(index(s),MALE) val source* = resolve-expr(source(s),gender*) - WDefAccessor(info(s),name(s),source*,index*,gender*) + DefAccessor(info(s),name(s),source*,index*,to-acc-dir(gender*)) (s:Connect) : Connect(info(s),resolve-expr(loc(s),FEMALE),resolve-expr(exp(s),MALE)) (s:BulkConnect) : @@ -696,8 +690,8 @@ defn expand-vector (e:Expression) -> List : defn expand-stmt (s:Stmt) -> Stmt : match(s) : - (s:WDefAccessor) : - println-all-debug(["Matched WDefAcc with " name(s)]) + (s:DefAccessor) : + println-all-debug(["Matched DefAcc with " name(s)]) val mem? = match(source(s)) : (e:WRef) : kind(e) typeof MemKind (e) : false @@ -829,9 +823,9 @@ defn lower-ports (ports:List) -> List : for x in generate-entry(name(p),type(p)) map : Port(info(p),name(x),direction(p) * flip(x),type(x)) -defn type (s:WDefAccessor) -> Type : type(type(source(s)) as VectorType) +defn type (s:DefAccessor) -> Type : type(type(source(s)) as VectorType) defn size (s:DefMemory) -> Int : size(type(s)) -defn size (s:WDefAccessor) -> Int : size(type(source(s)) as VectorType) +defn size (s:DefAccessor) -> Int : size(type(source(s)) as VectorType) defn base-name (e:Expression) -> Symbol : match(e) : (e:WRef) : name(e) @@ -868,13 +862,13 @@ defn lower (body:Stmt) -> Stmt : (s:DefMemory) : Begin $ for x in generate-entry(name(s),type(type(s))) map : DefMemory(info(s),name(x),VectorType(type(x),size(s)), seq?(s)) - (s:WDefAccessor) : + (s:DefAccessor) : val ls = generate-entry(name(s),type(s)) val rs = generate-entry(name(source(s) as WRef),type(s)) Begin $ for (l in ls, r in rs) map: if flip(r) == REVERSE : error("Shouldn't be here") val memref = WRef(name(r),VectorType(type(r),size(s)),MemKind(),gender(s)) - WDefAccessor(info(s),name(l),memref,index(s),gender(s)) + DefAccessor(info(s),name(l),memref,index(s),to-acc-dir(gender(s))) (s:OnReset|Connect) : Begin $ for (l in expand-expr(loc(s)), r in expand-expr(exp(s))) map : val lgender = FEMALE * flip(l) @@ -1226,66 +1220,17 @@ defn reduce-or (l:List) -> Expression : ; kinds: Used to know the kind of reference, so we know whether we should error if it isn't initialized. We also know how we should declare the refernce. ; enables:Calculated off of assigns. -defn expand-whens (ports:List, table:HashTable,cons:Vector) -> False : - for p in ports do : - if direction(p) == OUTPUT : - val ref = WRef(name(p),type(p),PortKind(),FEMALE) - if has-nul?(table[name(p)]) : - println("Uninitialized: ~" % [to-string(name(p))]);TODO actually collect error - else : add{cons,_} $ Connect(FileInfo(),ref,to-exp(table[name(p)]) as Expression) - -defn expand-whens (s:Stmt, table:HashTable,decs:Vector,cons:Vector) -> Stmt : - match(map(expand-whens{_,table,decs,cons},s)) : - (s:DefNode|DefMemory) : add(decs,s) - (s:DefWire) : - add(decs,s) - val ref = WRef(name(s),type(s),NodeKind(),FEMALE) - if has-nul?(table[name(s)]) : - println("Uninitialized: ~" % [to-string(name(s))]);TODO actually collect error - else : add{cons,_} $ Connect(info(s),ref,to-exp(table[name(s)]) as Expression) - (s:DefRegister) : - val e = to-exp(table[name(s)]) - match(e) : - (e:Expression) : - add{decs,_} $ DefWire(info(s),name(s),type(s)) - val ref = WRef(name(s),type(s),NodeKind(),FEMALE) - add{cons,_} $ Connect(info(s),ref,Register(type(s),e,to-exp(optimize $ get-write-enable(table[name(s)])) as Expression)) - (e:False) : false - (s:WDefAccessor) : - val t = type(type(source(s)) as VectorType) - val n = name(s) - switch {_ == gender(s)} : - MALE : - add{decs,_} $ DefWire(info(s),n,t) - val ref = WRef(n,t,WriteAccessorKind(),FEMALE) - add{cons,_} $ Connect(info(s),ref,ReadPort(source(s),index(s),t,get-read-enable(n,table))) - FEMALE : - add(decs,DefWire(info(s),n,t)) - val ref = WRef(n,t,WriteAccessorKind(),MALE) - val enable = (to-exp $ optimize $ get-write-enable(table[n])) as Expression - val wp = WritePort(source(s),index(s),t,enable as Expression) - val e = to-exp(table[n]) - add{cons,_} $ Connect(info(s),wp,ref) - match(e) : - (e:False) : - println("Uninitialized: ~" % [to-string(n)]) ;TODO actually collect error - (e:Expression) : - add{cons,_} $ Connect(info(s),ref,e) - (s:DefInstance) : - add(decs,s) - for f in fields(type(module(s)) as BundleType) map : - if flip(f) == REVERSE : - val n = to-symbol("~.~" % [name(s),name(f)]) ; only on inputs - val x = to-symbol(split(to-string(n),'.')[0]) - val f = to-symbol(split(to-string(n),'.')[1]) - val ref = WRef(x,type(module(s)),InstanceKind(),FEMALE) - val sref = WSubfield(ref,f,bundle-field-type(type(module(s)),f),FEMALE) - if has-nul?(table[n]) : - println("Uninitialized: ~" % [to-string(n)]);TODO actually collect error - else : add{cons,_} $ Connect(info(s),sref,to-exp(table[n]) as Expression) - (s:Connect|Conditionally|OnReset|Begin|EmptyStmt) : false - s +;----------------- Errors ------------------------ + +defn RefNotInitialized (info:FileInfo, name:Symbol) : + PassException $ string-join $ + [info ": Reference " name " is not fully initialized."] + +defn RefNotConnected (info:FileInfo, name:Symbol) : + PassException $ string-join $ + [info ": Reference " name " is never connected to."] +;---------------- Helper Functions -------------- defn get-read-enable (sym:Symbol,table:HashTable) -> Expression : defn get-single-read-enable (sym:Symbol,sv:SymbolicValue) -> Expression : defn active (e:Expression) -> True|False : @@ -1332,7 +1277,7 @@ defn build-tables (s:Stmt, (s:DefWire) : assign[name(s)] = SVNul() flattn[name(s)] = true - (s:DefRegister|WDefAccessor) : + (s:DefRegister|DefAccessor) : assign[name(s)] = SVNul() flattn[name(s)] = false (s:DefInstance) : ;TODO only add instance input ports. This probably involves correcting instance genders @@ -1386,41 +1331,106 @@ defn build-tables (s:Stmt, if s typeof OnReset : resets[key*] = SVExp(exp(s)) (s:Begin) : for s* in body(s) do: build-tables(s*,assign,resets,flattn) (s:DefMemory|DefNode|EmptyStmt) : false - -defn expand-whens (m:Module) -> Module : - match(m) : - (m:ExModule) : m - (m:InModule) : - val assign = HashTable(symbol-hash) - val resets = HashTable(symbol-hash) - val flattn = HashTable(symbol-hash) - - for p in ports(m) do : - if direction(p) == OUTPUT : - assign[name(p)] = SVNul() - flattn[name(p)] = false - - build-tables(body(m),assign,resets,flattn) - for x in assign do : assign[key(x)] = optimize(value(x)) - for x in resets do : resets[key(x)] = optimize(value(x)) - ;val enables = get-enables(assign,kinds) - ;for x in enables do : enables[key(x)] = optimize(value(x)) - - println-debug("====== Assigns ======") - for x in assign do : println-debug(x) - println-debug("====== Resets ======") - for x in resets do : println-debug(x) - - val table = merge-resets(assign,resets) - println-debug("====== Table ======") - for x in table do : println-debug(x) - val decs = Vector() - val cons = Vector() - expand-whens(ports(m),table,cons) - expand-whens(body(m),table,decs,cons) - InModule(info(m),name(m),ports(m),Begin(append(to-list(decs),to-list(cons)))) - -defn expand-whens (c:Circuit) -> Circuit : + +;--------------- Expand Whens Pass ------------------- + +public defn expand-whens (c:Circuit) -> Circuit : + val errors = Vector() + + defn expand-whens (ports:List, table:HashTable,cons:Vector) -> False : + for p in ports do : + if direction(p) == OUTPUT : + val ref = WRef(name(p),type(p),PortKind(),FEMALE) + if has-nul?(table[name(p)]) : + add(errors,RefNotInitialized(info(p), name(p)) + else : add{cons,_} $ Connect(FileInfo(),ref,to-exp(table[name(p)]) as Expression) + + defn expand-whens (s:Stmt, table:HashTable,decs:Vector,cons:Vector) -> Stmt : + match(map(expand-whens{_,table,decs,cons},s)) : + (s:DefNode|DefMemory) : add(decs,s) + (s:DefWire) : + add(decs,s) + val ref = WRef(name(s),type(s),NodeKind(),FEMALE) + if has-nul?(table[name(s)]) : + add(errors,RefNotInitialized(info(s), name(s)) + else : add{cons,_} $ Connect(info(s),ref,to-exp(table[name(s)]) as Expression) + (s:DefRegister) : + add(decs,s) + val e = to-exp(table[name(s)]) + match(e) : + (e:Expression) : + val ref = WRef(name(s),type(s),NodeKind(),FEMALE) + val en = to-exp(optimize $ get-write-enable(table[name(s)])) as Expression + if en == UIntValue(1,UnknownWidth()) : + add{cons,_} $ Connect(info(s),ref,e) + else : + add{cons,_} $ Conditionally(en,Connect(info(s),ref,e),EmptyStmt()) + (e:False) : + add(errors,RefNotConnected(info(s), name(s)) + (s:DefAccessor) : + add(decs,s) + val t = type(type(source(s)) as VectorType) + val n = name(s) + if gender(s) == FEMALE : + val ref = WRef(n,t,WriteAccessorKind(),FEMALE) + val e = to-exp(table[n]) + match(e) : + (e:Expression) : + val en = (to-exp $ optimize $ get-write-enable(table[n])) as Expression + if en == UIntValue(1,UnknownWidth()) : + add{cons,_} $ Connect(info(s),ref,e) + else : + add{cons,_} $ Conditionally(en,Connect(info(s),ref,e),EmptyStmt()) + (e:False) : + add(errors,RefNotConnected(info(s), n) + (s:DefInstance) : + add(decs,s) + for f in fields(type(module(s)) as BundleType) map : + if flip(f) == REVERSE : + val n = to-symbol("~.~" % [name(s),name(f)]) ; only on inputs + val x = to-symbol(split(to-string(n),'.')[0]) + val f = to-symbol(split(to-string(n),'.')[1]) + val ref = WRef(x,type(module(s)),InstanceKind(),FEMALE) + val sref = WSubfield(ref,f,bundle-field-type(type(module(s)),f),FEMALE) + if has-nul?(table[n]) : + add(errors,RefNotInitialized(info(s), n) + else : add{cons,_} $ Connect(info(s),sref,to-exp(table[n]) as Expression) + (s:Connect|Conditionally|OnReset|Begin|EmptyStmt) : false + s + + defn expand-whens (m:Module) -> Module : + match(m) : + (m:ExModule) : m + (m:InModule) : + val assign = HashTable(symbol-hash) + val resets = HashTable(symbol-hash) + ;val flattn = HashTable(symbol-hash) + + for p in ports(m) do : + if direction(p) == OUTPUT : + assign[name(p)] = SVNul() + flattn[name(p)] = false + + build-tables(body(m),assign,resets,flattn) + for x in assign do : assign[key(x)] = optimize(value(x)) + for x in resets do : resets[key(x)] = optimize(value(x)) + ;val enables = get-enables(assign,kinds) + ;for x in enables do : enables[key(x)] = optimize(value(x)) + + println-debug("====== Assigns ======") + for x in assign do : println-debug(x) + println-debug("====== Resets ======") + for x in resets do : println-debug(x) + + val table = merge-resets(assign,resets) + println-debug("====== Table ======") + for x in table do : println-debug(x) + val decs = Vector() + val cons = Vector() + expand-whens(ports(m),table,cons) + expand-whens(body(m),table,decs,cons) + InModule(info(m),name(m),ports(m),Begin(append(to-list(decs),to-list(cons)))) + Circuit(info(c),modules*, main(c)) where : val modules* = for m in modules(c) map : @@ -1658,6 +1668,11 @@ defn gen-constraints (m:Module, h:HashTable, v:Vector) -> Mod add(v,WGeq(width!(type(l)),width!(type(e)))) add(v,WGeq(width!(type(e)),width!(type(l)))) Connect(info(s),l,e) + (s:Conditionally) : + val p = gen-constraints(pred(s)) + add(v,WGeq(width!(type(p)),IntWidth(1))) + add(v,WGeq(IntWidth(1),width!(type(p)))) + Conditionally(info(s),p,conseq(s),alt(s)) (s) : s defn gen-constraints (e:Expression) -> Expression : @@ -1666,9 +1681,6 @@ defn gen-constraints (m:Module, h:HashTable, v:Vector) -> Mod (e:WSubfield) : WSubfield(exp(e),name(e),bundle-field-type(type(exp(e)),name(e)),gender(e)) (e:WIndex) : error("Shouldn't be here") (e:DoPrim) : DoPrim(op(e),args(e),consts(e),primop-gen-constraints(e,v)) - (e:ReadPort) : ReadPort(mem(e),index(e),type(type(mem(e)) as VectorType),enable(e)) - (e:WritePort) : WritePort(mem(e),index(e),type(type(mem(e)) as VectorType),enable(e)) - (e:Register) : Register(type(value(e)),value(e),enable(e)) (e:UIntValue) : match(width(e)) : (w:UnknownWidth) : @@ -1922,7 +1934,7 @@ defn to-real-ir (c:Circuit) : (e) : e defn to-stmt (s:Stmt) : match(map(to-exp,s)) : - (e:WDefAccessor) : error("Shouldn't be here") + (e:DefAccessor) : error("Shouldn't be here") (e:ConnectToIndexed) : error("Shouldn't be here") (e:ConnectFromIndexed) : error("Shouldn't be here") (e) : map(to-stmt,e) diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index 708430f2..4afd2a28 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -4,12 +4,55 @@ defpackage firrtl/verilog : import firrtl/ir-utils import firrtl/ir2 +public defstruct RemoveSeqMem <: Pass +public defmethod pass (b:RemoveSeqMem) -> (Circuit -> Circuit) : remove-smem{_} +public defmethod name (b:RemoveSeqMem) -> String : "Remove SeqMem" +public defmethod short-name (b:RemoveSeqMem) -> String : "remove-smem" + + +;============ Utilz ============= + +;============ Remove Seq Mem ============= + +defn remove-smem (m:InModule) -> InModule : + val hash = get-sym-hash(m) + val smems = Vector() + defn remove-smem-s (s:Stmt) -> Stmt : + map{remove-smem-s,_} $ match(s) : + (s:DefMemory) : + if seq?(s) : add(smems,name(s)) + DefMemory(info(s),name(s),type(s),false) + (s:DefAccessor) : + if dir(s) == WRITE and contains?(smems, name(source(s) as Ref)) : + val regged-index = firrtl-gensym(name(index(s) as Ref),hash) + val ref = Ref(regged-index,type(index(s))) + Begin $ to-list $ + [ DefRegister(info(s),regged-index,type(index(s))) + Connect(ref,index(s)) + DefAccessor(info(s),dir(s),name(s),source(s),ref) ] + else : s + (s) : s + + InModule(info(m),name(m),ports(m),remove-smem-s(body(m),hash)) + +public defn remove-smem (c:Circuit) -> Circuit : + for m in modules(c) do : + match(m) : + (m:InModule) : remove-smem(m) + (m:ExModule) : m + +;============ VERILOG ============== + public defstruct Verilog <: Pass : file : String public defmethod pass (b:Verilog) -> (Circuit -> Circuit) : emit-verilog{file(b),_} public defmethod name (b:Verilog) -> String : "To Verilog" public defmethod short-name (b:Verilog) -> String : "To Verilog" +defstruct DecAndConnect : + dec : Stmt + con : Connect + ;============ Utilz ============= defn width! (w:Width) -> Int : match(w) : @@ -41,12 +84,6 @@ defn remove-subfield (e:Expression) -> Expression : (e:Subfield) : Ref(to-symbol $ string-join $ [emit(exp(e)) "_" name(e)],type(e)) (e) : e -definterface VKind -defstruct WireKind <: VKind -defstruct RegKind <: VKind -defstruct SeqMemKind <: VKind -defstruct ComMemKind <: VKind - ;============ Verilog Backend ============= defn emit-as-type (e:Expression,t:Type) -> String : @@ -139,19 +176,26 @@ defn emit (e:Expression) -> String : v = concat(v, [" ^ " emit(x)]) v + +defn get-name (e:Expression) -> Symbol : + match(e) : + (e:Ref) : name(e) + (e:Subfield) : symbol-join([get-name(exp(e)) `. name(e)) + (e) : error("Shouldn't be here") + defn emit-module (m:InModule) : - val h = HashTable(symbol-hash) + val decs = HashTable(sym-hash) ; all declarations + val cons = HashTable(sym-hash) ; all connections defn build-table (m:InModule) : defn build-table (s:Stmt) -> Stmt : - match(map(build-table,s)) : - (s:DefWire) : h[name(s)] = WireKind() - (s:DefMemory) : - if seq?(s) : h[name(s)] = SeqMemKind() - else : h[name(s)] = ComMemKind() + match(map(build-table,map(remove-subfield,s))) : + (s:DefWire|DefReg|DefAccessor|DefMemory|DefNode|DefInstance) : decs[name(s)] = s + (s:Conditionally) : + val n = name(loc(conseq(s) as Connect)) + cons[n] = s (s:Connect) : - match(exp(s)) : - (e:Register) : h[name(loc(s) as Ref)] = RegKind() - (e) : false + val n = get-name(loc(s)) + cons[n] = s (s) : false s build-table(body(m)) @@ -166,14 +210,66 @@ defn emit-module (m:InModule) : val inst-ports = HashTable>(symbol-hash) val sh = get-sym-hash(m) + + for dec in decs do : + match(value(dec)) : + + defn emit-pred-connect (s:Connect,en:Expression) : + if blocking?[name(loc(s) as Ref)] : + add(assigns,["assign " emit(loc(s)) " = " emit(exp(s)) ";"]) + else : + add(updates,["if(" emit(enable(reg)) ") begin"]) + add(updates,[" " n " <= " emit(value(reg)) ";"]) + add(updates,["end"]) + + +; add(updates,["if(" en ") begin"]) +; add(updates,[" " emit(mem(wp)) "[" emit(index(wp)) "] <= " emit(exp(s)) ";"]) +; add(updates,["end"]) +; else : +; if exp(s) typeof Register : +; val n = name(loc(s) as Ref) +; val reg = exp(s) as Register +; add(inits,[n " = {" width!(type(reg)) "{$random}};"]) +; add(updates,["if(" emit(enable(reg)) ") begin"]) +; add(updates,[" " n " <= " emit(value(reg)) ";"]) +; add(updates,["end"]) +; else if exp(s) typeof ReadPort : +; val n = name(loc(s) as Ref) +; val rp = exp(s) as ReadPort +; match(h[name(mem(rp) as Ref)]) : +; (k:SeqMemKind) : +; val index* = Ref(firrtl-gensym(name(index(rp) as Ref),sh),type(index(rp))) +; add(regs,[ "reg " get-width(type(index*)) " " name(index*) ";"]) +; add(inits,[name(index*) " = {" width!(type(index*)) "{$random}};"]) +; add(updates,["if(" emit(enable(rp)) ") begin"]) +; add(updates,[" " name(index*) " <= " emit(index(rp)) ";"]) +; add(updates,["end"]) +; add(assigns,["assign " n " = " emit(mem(rp)) "[" emit(index*) "];"]) +; (k:ComMemKind) : +; add(assigns,["assign " n " = " emit(mem(rp)) "[" emit(index(rp)) "];"]) +; else : +; add(assigns,["assign " emit(loc(s)) " = " emit(exp(s)) ";"]) + defn emit-s (s:Stmt) : match(map(remove-subfield,s)) : - (s:DefWire) : - if h[name(s)] == RegKind() : - add(regs,["reg " get-width(type(s)) " " name(s) ";"]) - else : - add(wires,["wire " get-width(type(s)) " " name(s) ";"]) + (s:DefWire) : add(wires,["wire " get-width(type(s)) " " name(s) ";"]) + (s:DefRegister) : add(regs,["reg " get-width(type(s)) " " name(s) ";"]) + (s:DefAccessor) : + switch {_ == dir(s)} : + READ : + match(h[name(source(s) as Ref)]) : + (k:SeqMemKind) : + val index* = Ref(firrtl-gensym(name(index(rp) as Ref),sh),type(index(rp))) + add(regs,[ "reg " get-width(type(index*)) " " name(index*) ";"]) + add(inits,[name(index*) " = {" width!(type(index*)) "{$random}};"]) + add(updates,["if(" emit(enable(rp)) ") begin"]) + add(updates,[" " name(index*) " <= " emit(index(rp)) ";"]) + add(updates,["end"]) + add(assigns,["assign " n " = " emit(mem(rp)) "[" emit(index*) "];"]) + (k:ComMemKind) : + add(assigns,["assign " n " = " emit(mem(rp)) "[" emit(index(rp)) "];"]) (s:DefInstance) : inst-ports[name(s)] = Vector() insts[name(s)] = name(module(s) as Ref) @@ -190,36 +286,8 @@ defn emit-module (m:InModule) : add(wires,["wire " get-width(type(value(s))) " " name(s) ";"]) add(assigns,["assign " name(s) " = " emit(value(s)) ";"]) (s:Begin) : do(emit-s, body(s)) - (s:Connect) : - if loc(s) typeof WritePort : - val wp = loc(s) as WritePort - add(updates,["if(" emit(enable(wp)) ") begin"]) - add(updates,[" " emit(mem(wp)) "[" emit(index(wp)) "] <= " emit(exp(s)) ";"]) - add(updates,["end"]) - else : - if exp(s) typeof Register : - val n = name(loc(s) as Ref) - val reg = exp(s) as Register - add(inits,[n " = {" width!(type(reg)) "{$random}};"]) - add(updates,["if(" emit(enable(reg)) ") begin"]) - add(updates,[" " n " <= " emit(value(reg)) ";"]) - add(updates,["end"]) - else if exp(s) typeof ReadPort : - val n = name(loc(s) as Ref) - val rp = exp(s) as ReadPort - match(h[name(mem(rp) as Ref)]) : - (k:SeqMemKind) : - val index* = Ref(firrtl-gensym(name(index(rp) as Ref),sh),type(index(rp))) - add(regs,[ "reg " get-width(type(index*)) " " name(index*) ";"]) - add(inits,[name(index*) " = {" width!(type(index*)) "{$random}};"]) - add(updates,["if(" emit(enable(rp)) ") begin"]) - add(updates,[" " name(index*) " <= " emit(index(rp)) ";"]) - add(updates,["end"]) - add(assigns,["assign " n " = " emit(mem(rp)) "[" emit(index*) "];"]) - (k:ComMemKind) : - add(assigns,["assign " n " = " emit(mem(rp)) "[" emit(index(rp)) "];"]) - else : - add(assigns,["assign " emit(loc(s)) " = " emit(exp(s)) ";"]) + (s:Conditionally) : emit-pred-connect(pred(s),conseq(s) as Connect) + (s:Connect) : emit-pred-connect(UIntValue(1,1),s) (s) : s emit-s(body(m)) diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir new file mode 100644 index 00000000..01347fdd --- /dev/null +++ b/test/passes/expand-whens/reg-dwc.fir @@ -0,0 +1,21 @@ +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +circuit top : + module top : + wire p : UInt + p := UInt(1) + reg r : UInt + when p : + r := UInt(20) + +; CHECK: Expand Whens + +; CHECK: circuit top : +; CHECK: module top : +; CHECK: wire p : UInt +; CHECK: reg r : UInt +; CHECK: p := UInt(1) +; CHECK: when p : r := UInt(20) + +; CHECK: Finished Expand Whens + + diff --git a/test/passes/expand-whens/reg-dwoc.fir b/test/passes/expand-whens/reg-dwoc.fir new file mode 100644 index 00000000..521e1710 --- /dev/null +++ b/test/passes/expand-whens/reg-dwoc.fir @@ -0,0 +1,21 @@ +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +circuit top : + module top : + wire p : UInt + p := UInt(1) + reg r : UInt + when p : + on-reset r := UInt(10) + r := UInt(20) + +; CHECK: Expand Whens + +; CHECK: circuit top : +; CHECK: module top : +; CHECK: wire p : UInt +; CHECK: reg r : UInt +; CHECK: p := UInt(1) +; CHECK: when p : r := mux(reset, UInt(10), UInt(20)) + +; CHECK: Finished Expand Whens + diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir new file mode 100644 index 00000000..df6c7034 --- /dev/null +++ b/test/passes/expand-whens/reg-wdc.fir @@ -0,0 +1,20 @@ +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +circuit top : + module top : + wire p : UInt + p := UInt(1) + when p : + reg r : UInt + r := UInt(20) + +; CHECK: Expand Whens + +; CHECK: circuit top : +; CHECK: module top : +; CHECK: wire p : UInt +; CHECK: reg r : UInt +; CHECK: p := UInt(1) +; CHECK: r := UInt(20) + +; CHECK: Finished Expand Whens + diff --git a/test/passes/expand-whens/reg-wdoc.fir b/test/passes/expand-whens/reg-wdoc.fir new file mode 100644 index 00000000..ad2089c2 --- /dev/null +++ b/test/passes/expand-whens/reg-wdoc.fir @@ -0,0 +1,20 @@ +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +circuit top : + module top : + wire p : UInt + when p : + reg r : UInt + on-reset r := UInt(10) + r := UInt(20) + +; CHECK: Expand Whens + +; CHECK: circuit top : +; CHECK: module top : +; CHECK: wire p : UInt +; CHECK: reg r : UInt +; CHECK: p := UInt(1) +; CHECK: r := mux(reset, UInt(10), UInt(20)) + +; CHECK: Finished Expand Whens + diff --git a/test/passes/expand-whens/scoped-reg.fir b/test/passes/expand-whens/scoped-reg.fir index b71a5d50..7f2632f4 100644 --- a/test/passes/expand-whens/scoped-reg.fir +++ b/test/passes/expand-whens/scoped-reg.fir @@ -1,5 +1,4 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s -; CHECK: Expand Whens circuit top : module top : wire p : UInt @@ -7,6 +6,13 @@ circuit top : reg r : UInt on-reset r := UInt(10) r := UInt(20) -; CHECK: r := Register(mux(reset, UInt(10), UInt(20)), mux(reset, UInt(1), p)) -; CHECK: Finished Expand Whens +; CHECK: Expand Whens + +; CHECK: circuit top : +; CHECK: module top : +; CHECK: wire p : UInt +; CHECK: reg r : UInt +; CHECK: r := mux(reset, UInt(10), UInt(20)) + +; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/wacc-wdc.fir b/test/passes/expand-whens/wacc-wdc.fir new file mode 100644 index 00000000..6e407178 --- /dev/null +++ b/test/passes/expand-whens/wacc-wdc.fir @@ -0,0 +1,23 @@ +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +circuit top : + module top : + wire p : UInt + cmem m : UInt<4>[10] + p := UInt(1) + when p : + write accessor a = m[UInt(3)] + a := UInt(20) + +; CHECK: Expand Whens + +; CHECK: circuit top : +; CHECK: module top : +; CHECK: wire p : UInt +; CHECK: cmem m : UInt<4>[10] +; CHECK: write accessor a : m[UInt(3)] +; CHECK: p := UInt(1) +; CHECK: when p : a := UInt(20) + +; CHECK: Finished Expand Whens + + -- cgit v1.2.3 From 3145eaab41e76cc8cd18ceea01d7548fa539f1b6 Mon Sep 17 00:00:00 2001 From: azidar Date: Thu, 2 Jul 2015 14:15:05 -0700 Subject: Partial commit --- src/main/stanza/verilog.stanza | 76 ++++++++++++++++++++++++++++++++++-------- 1 file changed, 62 insertions(+), 14 deletions(-) diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index 4afd2a28..0e04df8a 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -180,7 +180,7 @@ defn emit (e:Expression) -> String : defn get-name (e:Expression) -> Symbol : match(e) : (e:Ref) : name(e) - (e:Subfield) : symbol-join([get-name(exp(e)) `. name(e)) + (e:Subfield) : error("Shouldn't be here") (e) : error("Shouldn't be here") defn emit-module (m:InModule) : @@ -191,7 +191,7 @@ defn emit-module (m:InModule) : match(map(build-table,map(remove-subfield,s))) : (s:DefWire|DefReg|DefAccessor|DefMemory|DefNode|DefInstance) : decs[name(s)] = s (s:Conditionally) : - val n = name(loc(conseq(s) as Connect)) + val n = get-name(loc(conseq(s) as Connect)) cons[n] = s (s:Connect) : val n = get-name(loc(s)) @@ -211,17 +211,62 @@ defn emit-module (m:InModule) : val sh = get-sym-hash(m) - for dec in decs do : + for (sym -> dec) in decs do : match(value(dec)) : + (dec:DefWire) : + add(wires,["wire " get-width(type(s)) " " name(s) ";"]) + emit-blocking-connect(cons[sym]) + (dec:DefRegister) : + add(regs,["reg " get-width(type(s)) " " name(s) ";"]) + emit-nonblocking-connect(cons[sym]) + (dec:DefMemory) : + val vtype = type(s) as VectorType + add(regs,["reg " get-width(type(vtype)) " " name(s) " [0:" size(vtype) "];"]) + add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"]) + add(inits,[" " name(s) "[initvar] = {" width!(type(vtype)) "{$random}};"]) + (s:DefNode) : + add(wires,["wire " get-width(type(value(s))) " " name(s) ";"]) + add(assigns,["assign " name(s) " = " emit(value(s)) ";"]) + (s:DefInstance) : + inst-ports[name(s)] = Vector() + insts[name(s)] = name(module(s) as Ref) + for f in fields(type(module(s)) as BundleType) do : + val n* = to-symbol $ string-join $ [name(s) "_" name(f)] + add(wires,["wire " get-width(type(f)) " " n* ";"]) + add(inst-ports[name(s)], ["." name(f) "( " n* " )"]) + (s:DefAccessor) : + switch {_ == dir(s)} : + READ : + val mem-declaration = decs[name(source(s) as Ref)] + val con = cons[sym] + if seq?(mem-declaration) : + val index* = Ref(firrtl-gensym(name(index(s) as Ref),sh),type(index(s))) + add(regs,[ "reg " get-width(type(index*)) " " name(index*) ";"]) ; to make it sequential, register the index for an additional cycle + add(inits,[name(index*) " = {" width!(type(index*)) "{$random}};"]) + add(updates,[name(index*) " <= " emit(index(s)) ";"]) + add(assigns,["assign " n " = " emit(mem(s)) "[" emit(index*) "];"]) + else : + add(assigns,["assign " n " = " emit(mem(s)) "[" emit(index(s)) "];"]) + + + - - defn emit-pred-connect (s:Connect,en:Expression) : - if blocking?[name(loc(s) as Ref)] : - add(assigns,["assign " emit(loc(s)) " = " emit(exp(s)) ";"]) - else : - add(updates,["if(" emit(enable(reg)) ") begin"]) - add(updates,[" " n " <= " emit(value(reg)) ";"]) - add(updates,["end"]) + defn emit-blocking-connect (s:Stmt) : + match(s) : + (s:Connect) : add(assigns,["assign " emit(loc(s)) " = " emit(exp(s)) ";"]) + (s:Conditionally) : error("Shouldn't be here") + defn emit-nonblocking-connect (s:Stmt) : + match(s) : + (s:Connect) : + add(updates,[n " <= " emit(value(reg)) ";"]) + (s:Conditionally) : + match(conseq(s)) : + (c:Connect) : + add(updates,["if(" emit(pred(s)) ") begin"]) + add(updates,[" " emit(loc(c) " <= " emit(exp(c)) ";"]) + add(updates,["end"]) + (c) : error("Shouldn't be here") + (s) : error("Shouldn't be here") ; add(updates,["if(" en ") begin"]) @@ -253,8 +298,11 @@ defn emit-module (m:InModule) : ; add(assigns,["assign " emit(loc(s)) " = " emit(exp(s)) ";"]) defn emit-s (s:Stmt) : - match(map(remove-subfield,s)) : - (s:DefWire) : add(wires,["wire " get-width(type(s)) " " name(s) ";"]) + match(s) : + (s:DefWire) : + add(wires,["wire " get-width(type(s)) " " name(s) ";"]) + add(assigns,["assign " emit(loc(s)) " = " emit(exp(s)) ";"]) + (s:DefRegister) : add(regs,["reg " get-width(type(s)) " " name(s) ";"]) (s:DefAccessor) : switch {_ == dir(s)} : @@ -290,7 +338,7 @@ defn emit-module (m:InModule) : (s:Connect) : emit-pred-connect(UIntValue(1,1),s) (s) : s - emit-s(body(m)) + ;==== Actually printing module ===== val port-indent = " " -- cgit v1.2.3 From d9ece539b630ef9988f6f6e2159b5126e1728ccd Mon Sep 17 00:00:00 2001 From: azidar Date: Mon, 6 Jul 2015 17:45:06 -0700 Subject: Still partial commit, many tests pass. Many tests fail. --- spec/spec.tex | 12 +- src/main/stanza/compilers.stanza | 60 +++--- src/main/stanza/errors.stanza | 29 ++- src/main/stanza/firrtl-ir.stanza | 4 +- src/main/stanza/firrtl-test-main.stanza | 5 +- src/main/stanza/flo.stanza | 87 --------- src/main/stanza/ir-parser.stanza | 17 +- src/main/stanza/ir-utils.stanza | 26 ++- src/main/stanza/passes.stanza | 138 +++++++++++--- src/main/stanza/verilog.stanza | 210 +++++---------------- test/passes/expand-accessors/accessor-mem.fir | 14 +- test/passes/expand-accessors/accessor-vec.fir | 34 +++- test/passes/expand-connect-indexed/bundle-vecs.fir | 2 +- test/passes/expand-whens/bundle-init.fir | 4 +- test/passes/expand-whens/nested-whens.fir | 10 +- test/passes/expand-whens/one-when.fir | 11 +- test/passes/expand-whens/partial-init.fir | 10 + test/passes/expand-whens/reg-wdoc.fir | 1 + test/passes/expand-whens/scoped-reg.fir | 1 + test/passes/expand-whens/two-when.fir | 21 ++- test/passes/infer-types/bundle.fir | 7 +- 21 files changed, 329 insertions(+), 374 deletions(-) diff --git a/spec/spec.tex b/spec/spec.tex index 647eb471..6c5038cd 100644 --- a/spec/spec.tex +++ b/spec/spec.tex @@ -80,7 +80,7 @@ After a custom pass, the resulting circuit should undergo lowering prior to pass \section{Acknowledgements - IN PROGRESS} The FIRRTL language could not have been developed without the help of many of the faculty and students in the ASPIRE lab, including but not limited to XXXX. -We'd also like to thank our sponsors XXXX, and the UC Berkeley University. +We'd also like to thank our sponsors XXXX, and the University of California, Berkeley. \section{FIRRTL Language Definition} @@ -333,7 +333,7 @@ Additionally, the type for a memory must be completely specified and cannot cont It is an error to specify any other type for a memory. However, the internal type to the vector type may be a non-ground type, with the caveat that the internal type, if a bundle type, cannot contain any reverse fields. -A memory cannot be explicitly initialized using a special FIRRTL construct ? the circuit itself must contain the proper logic to initialize the memory. +A memory cannot be explicitly initialized using a special FIRRTL construct - the circuit itself must contain the proper logic to initialize the memory. \subsection{Nodes} A node is simply a named intermediate value in a circuit, and is akin to a pointer in the C programming language. @@ -550,7 +550,7 @@ This is to facilitate writing transformational passes, by ensuring that the comp Inside a when, a connection to a component is conditional only if the component is declared outside the when statement. If the component is both declared and connected to inside a when, the connection is {\em not} conditional on that when. -Conceptually, a when creates a mux between the stuff outside and the stuff inside ? it acts as type of "conditional barrier". +Conceptually, a when creates a mux between the stuff outside and the stuff inside - it acts as type of "conditional barrier". Thus, if you draw a line between a component's declaration and a connection to it, that connection is dependent on all intersected when predicates being true. The following example shows a {\em conditional} connection inside a when statement, where the register \pd{r} is assigned the value of 42 only if \pds{enable} is true. @@ -1094,7 +1094,7 @@ Inlined lowered form is essentially a flat netlist which specifies every compone \item This is impossible to detect, so turns into a silent failure \item If annotations are used for actual manipulations of circuits later on, this could be the cause of a bug that is exceptionally hard to solve \item Thus, annotation producer/consumer keeps external data structure mapping names to annotations -\item Pass writers must do all they can to preserve names ? can provide transform for names that annotation users can run on their tables +\item Pass writers must do all they can to preserve names - can provide transform for names that annotation users can run on their tables \item If a name is mangled, the annotation consumer can ERROR. Then, they need to look at the pass to see how their annotations should propagate. \end{enumerate} @@ -1297,8 +1297,8 @@ Standardizing how names gets mangled requires a lot of thought, and we didn't fe For now, names have to be unique, and it is the front-end's responsibility to do this. \item Why allow declaring components in when statements? -We want the important property that a module is just a box of components inside ? for any jumble of components, you can always lace them in the box, and it will preserve the semantics. -You need to declare wires inside whens ? because generators could run within a when in a front-end. +We want the important property that a module is just a box of components inside - for any jumble of components, you can always lace them in the box, and it will preserve the semantics. +You need to declare wires inside whens - because generators could run within a when in a front-end. You should always be able to pull them into a module if we want. Now its inconsistent if you can't declare registers in the scope. diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index 2f6329dc..a3b04a94 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -3,40 +3,40 @@ defpackage firrtl/compiler : import verse import firrtl/passes import firrtl/errors - import firrtl/flo +; import firrtl/flo import firrtl/verilog import firrtl/ir2 import firrtl/ir-utils -public defstruct StandardFlo <: Compiler : - file: String with: (as-method => true) -public defmethod passes (c:StandardFlo) -> List : - to-list $ [ - CheckHighForm(expand-delin) - ;; TempElimination() - ToWorkingIR() - MakeExplicitReset() - ResolveKinds() - CheckKinds() - InferTypes() - CheckTypes() - ResolveGenders() - CheckGenders() - ExpandAccessors() - LowerToGround() - ExpandIndexedConnects() - ExpandWhens() - InferWidths() - Pad() - Inline() - SplitExp() - ToRealIR() - SpecialRename(`#,`_) - SpecialRename(`$,`::) - CheckHighForm(`::) - CheckLowForm() - Flo(file(c)) - ] +;public defstruct StandardFlo <: Compiler : +; file: String with: (as-method => true) +;public defmethod passes (c:StandardFlo) -> List : +; to-list $ [ +; CheckHighForm(expand-delin) +; ;; TempElimination() +; ToWorkingIR() +; MakeExplicitReset() +; ResolveKinds() +; CheckKinds() +; InferTypes() +; CheckTypes() +; ResolveGenders() +; CheckGenders() +; ExpandAccessors() +; LowerToGround() +; ExpandIndexedConnects() +; ExpandWhens() +; InferWidths() +; Pad() +; Inline() +; SplitExp() +; ToRealIR() +; SpecialRename(`#,`_) +; SpecialRename(`$,`::) +; CheckHighForm(`::) +; CheckLowForm() +; Flo(file(c)) +; ] public defstruct StandardVerilog <: Compiler : file: String with: (as-method => true) diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza index 8c47d112..e726fd00 100644 --- a/src/main/stanza/errors.stanza +++ b/src/main/stanza/errors.stanza @@ -247,7 +247,7 @@ public defn check-high-form (c:Circuit,sym:Symbol) -> Circuit : defn check-valid-loc (info:FileInfo,e:Expression) -> False : match(e) : - (e:UIntValue|SIntValue|DoPrim|ReadPort|Register) : + (e:UIntValue|SIntValue|DoPrim) : add(errors,InvalidLOC(info)) (e) : false @@ -403,20 +403,7 @@ public defn check-kinds (c:Circuit) -> Circuit : (e:WIndex) : check-is-mem(info,exp(e)) (e) : false - defn check-kinds-e (info:FileInfo,e:Expression) -> False : - do(check-kinds-e{info,_},e) - match(e) : - (e:ReadPort) : - check-is-mem(info,mem(e)) - check-not-mem(info,index(e)) - check-not-mem(info,enable(e)) - (e:WritePort) : - check-is-mem(info,mem(e)) - check-not-mem(info,index(e)) - check-not-mem(info,enable(e)) - (e) : do(check-not-mem{info,_},e) defn check-kinds-s (s:Stmt) -> False : - do(check-kinds-e{info(s),_:Expression},s) match(s) : (s:DefNode) : check-not-mem(info(s),value(s)) (s:DefAccessor) : check-not-mem(info(s),index(s)) @@ -649,11 +636,19 @@ defn InferDirection (info:FileInfo,name:Symbol) : [info ": Accessor " name " has a direction that requires inference."] ;---------------- Helper Functions -------------- -defn dir-to-gender (d:Direction) -> Gender : +defn dir-to-gender (d:PortDirection) -> Gender : switch {_ == d} : INPUT : MALE OUTPUT : FEMALE +defn gender (s:DefAccessor) -> Gender : + switch {_ == acc-dir(s)} : + READ : MALE + WRITE : FEMALE + INFER : UNKNOWN-GENDER + RDWR : BI-GENDER + + ;----------------- Check Genders Pass --------------------- public defn check-genders (c:Circuit) -> Circuit : @@ -697,7 +692,7 @@ public defn check-genders (c:Circuit) -> Circuit : (s:DefMemory) : genders[name(s)] = BI-GENDER (s:DefInstance) : genders[name(s)] = MALE (s:DefAccessor) : - if dir(s) == INFER : add(errors,InferDirection(info(s),name(s))) + if acc-dir(s) == INFER : add(errors,InferDirection(info(s),name(s))) check-gender(info(s),genders,index(s),MALE) check-gender(info(s),genders,source(s),gender(s)) genders[name(s)] = gender(s) @@ -813,7 +808,7 @@ public defn check-low-form (c:Circuit) -> Circuit : (s:OnReset) : add(errors,NoOnReset(info(s))) (s:BulkConnect) : add(errors,NoBulkConnect(info(s))) (s:Connect) : - check-correct-exp(info(s),e) + check-correct-exp(info(s),exp(s)) match(loc(s)) : (e:Ref|Subfield) : val n* = to-symbol $ to-string $ e diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza index 92f955b9..b698bae2 100644 --- a/src/main/stanza/firrtl-ir.stanza +++ b/src/main/stanza/firrtl-ir.stanza @@ -116,10 +116,10 @@ public defstruct DefNode <: Stmt : ;LOW value: Expression public defstruct DefAccessor <: Stmt : info: FileInfo with: (as-method => true) - dir: AccDirection name: Symbol source: Expression index: Expression + acc-dir: AccDirection public defstruct Conditionally <: Stmt : info: FileInfo with: (as-method => true) pred: Expression @@ -161,7 +161,7 @@ public defstruct Field : public defstruct Port : info: FileInfo name: Symbol - pkind: PKind + direction: PortDirection type: Type public definterface Module diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza index beb288b1..374fe438 100644 --- a/src/main/stanza/firrtl-test-main.stanza +++ b/src/main/stanza/firrtl-test-main.stanza @@ -11,7 +11,7 @@ #include("primop.stanza") #include("errors.stanza") #include("compilers.stanza") -#include("flo.stanza") +;#include("flo.stanza") #include("verilog.stanza") ;Custom Packages @@ -80,7 +80,8 @@ defn main () : run-passes(c,get-passes(to-list(pass-names))) else : switch {_ == compiler} : - "flo" : run-passes(c,StandardFlo(output as String)) + ;"flo" : run-passes(c,StandardFlo(output as String)) + "flo" : run-passes(c,StandardVerilog(output as String)) "verilog" : run-passes(c,StandardVerilog(output as String)) "verilute" : run-passes(c,InstrumentedVerilog(output as String,to-list $ pass-args)) else : error("Invalid compiler flag") diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza index fd000e20..cf15638d 100644 --- a/src/main/stanza/flo.stanza +++ b/src/main/stanza/flo.stanza @@ -5,93 +5,6 @@ defpackage firrtl/flo : import firrtl/ir2 import firrtl/passes -;========== Pad Widths ================== - -public defstruct Pad <: Pass -public defmethod pass (b:Pad) -> (Circuit -> Circuit) : pad-widths -public defmethod name (b:Pad) -> String : "Pad Widths" - -defn int-width! (t:Type) -> Int : - match(width!(t)) : - (w:IntWidth) : width(w) - (w) : error("Non-int width") - -defn set-width (desired:Int,t:Type) -> Type : - match(t) : - (t:UIntType) : UIntType(IntWidth(desired)) - (t:SIntType) : SIntType(IntWidth(desired)) - (t) : error("Non-ground type") - -defn pad-widths-e (desired:Int,e:Expression) -> Expression : - defn trim (desired:Int, e:Expression) : - ;; println-all(["TRIM " desired " e " e]) - DoPrim(BITS-SELECT-OP,list(e),list(desired - 1, 0),set-width(desired,type(e))) - defn pad (desired:Int, e:Expression) : - ;; println-all(["PAD " desired " e " e]) - DoPrim(PAD-OP,list(e),list(desired),set-width(desired,type(e))) - defn trim-pad (desired:Int, e:Expression) : - val i = int-width!(type(e)) - if i > desired : trim(desired, e) - else if i == desired : e - else : pad(desired, e) - defn self-pad-widths-e (e:Expression) -> Expression : - pad-widths-e(int-width!(type(e)), e) - ;; println-all(["PAD-E " desired " " e]) - match(e) : - (e:DoPrim) : - val new-desired = reduce(max, 0, map(int-width!{type(_)}, args(e))) - ;; println-all([" NEW DESIRED " new-desired]) - val e* = - if contains?([CONCAT-OP, DYN-SHIFT-RIGHT-OP, DYN-SHIFT-LEFT-OP], op(e)) : - DoPrim(op(e), map(self-pad-widths-e, args(e)), consts(e), type(e)) - else if contains?([MUX-OP], op(e)) : - DoPrim(op(e), list(pad-widths-e(1, args(e)[0]), pad-widths-e(new-desired, args(e)[1]), pad-widths-e(new-desired, args(e)[2])), consts(e), type(e)) - else : - map(pad-widths-e{new-desired,_},e) - trim-pad(desired, e*) - (e:WRef|WSubfield|WIndex) : - trim-pad(desired, e) - (e:UIntValue) : - val i = int-width!(type(e)) - if i > desired : trim(desired, e) - else : UIntValue(value(e),IntWidth(desired)) - (e:SIntValue) : - val i = int-width!(type(e)) - if i > desired : trim(desired, e) - else : SIntValue(value(e),IntWidth(desired)) - (e:Register) : - val value* = pad-widths-e(desired, value(e)) - Register(type(value*), value*, pad-widths-e(1, enable(e))) - (e:ReadPort) : - if int-width!(type(e)) != desired : error("ReadPort has different width than desired") - else : ReadPort(mem(e), self-pad-widths-e(index(e)), type(e), pad-widths-e(1, enable(e))) - (e:WritePort) : - if int-width!(type(e)) != desired : error("WritePort has different width than desired") - else : WritePort(mem(e), self-pad-widths-e(index(e)), type(e), pad-widths-e(1, enable(e))) - (e) : error(to-string $ e) - -defn pad-widths-s (s:Stmt) -> Stmt : - ;; println-all(["PAD-S " s]) - match(map(pad-widths-s,s)) : - (s:Connect) : - val i = int-width!(type(loc(s))) - val loc* = pad-widths-e(i,loc(s)) - val exp* = pad-widths-e(i,exp(s)) - Connect(info(s),loc*,exp*) - (s:DefNode) : - val i = int-width!(type(value(s))) - val exp* = pad-widths-e(i,value(s)) - DefNode(info(s),name(s),exp*) - (s) : - s - -public defn pad-widths (c:Circuit) -> Circuit : - Circuit{info(c),_,main(c)} $ - for m in modules(c) map : - match(m) : - (m:ExModule) : m - (m:InModule) : InModule(info(m),name(m),ports(m),pad-widths-s(body(m))) - ;============= Flo Backend ================ public defstruct Flo <: Pass : diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza index 374cf58c..f85ff7c9 100644 --- a/src/main/stanza/ir-parser.stanza +++ b/src/main/stanza/ir-parser.stanza @@ -131,6 +131,10 @@ defsyntax firrtl : FPE(form, "Expected a vector type here.") when t not-typeof VectorType t + ;Error if not an accessor direction + accdir! = (?a:#accdir) : a + accdir! != () : FPE(form, "Expected an accessor direction here.") + ;Error if not an expression exp! = (?e:#exp) : e exp! != () : FPE(form, "Expected an expression here.") @@ -196,6 +200,12 @@ defsyntax firrtl : field = (flip ?name:#id! #:! ?type:#type!) : Field(name, REVERSE, type) field = (?name:#id #:! ?type:#type!) : Field(name, DEFAULT, type) + defrule accdir : + accdir = (read) : READ + accdir = (write) : WRITE + accdir = (infer) : INFER + accdir = (rdwr) : RDWR + defrule width : width = (?x:#int) : IntWidth(x) width = (?) : UnknownWidth() @@ -208,12 +218,15 @@ defsyntax firrtl : stmt = (smem ?name:#id! #:! ?t:#vectype!) : DefMemory(first-info(form),name, t, true) stmt = (inst ?name:#id! #of! ?m:#ref!) : DefInstance(first-info(form),name, m) stmt = (node ?name:#id! #=! ?e:#exp!) : DefNode(first-info(form),name, e) - stmt = (accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name, s, i) + stmt = (on-reset ?x:#exp := ?y:#exp!) : OnReset(first-info(form),x, y) + stmt = (read accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name, s, i,READ) + stmt = (write accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name, s, i,WRITE) + stmt = (infer accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name, s, i,INFER) + stmt = (rdwr accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name, s, i,RDWR) stmt = (?s:#stmt/when) : s stmt = (?x:#exp := ?y:#exp!) : Connect(first-info(form),x, y) stmt = (?x:#exp <> ?y:#exp!) : BulkConnect(first-info(form),x, y) - stmt = (on-reset ?x:#exp := ?y:#exp!) : OnReset(first-info(form),x, y) stmt = ((?s:#stmt ?ss:#stmt ... ?rest ...)) : if not empty?(rest) : diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza index e29bf4ac..8e65005f 100644 --- a/src/main/stanza/ir-utils.stanza +++ b/src/main/stanza/ir-utils.stanza @@ -98,7 +98,15 @@ defmethod print (o:OutputStream, d:Flip) : DEFAULT : "" REVERSE: "flip" -defmethod print (o:OutputStream, d:Direction) : +defmethod print (o:OutputStream, d:AccDirection) : + print{o, _} $ + switch {d == _} : + READ : "read" + WRITE: "write" + INFER: "infer" + RDWR: "rdwr" + +defmethod print (o:OutputStream, d:PortDirection) : print{o, _} $ switch {d == _} : INPUT : "input" @@ -177,12 +185,16 @@ defmethod print (o:OutputStream, c:Stmt) : (c:DefNode) : print-all(o,["node " name(c) " = " value(c)]) (c:DefAccessor) : - print-all(o,["accessor " name(c) " = " source(c) "[" index(c) "]"]) + print-all(o,[acc-dir(c) " accessor " name(c) " = " source(c) "[" index(c) "]"]) (c:Conditionally) : - print-all(o, ["when " pred(c) " :"]) - print-debug(o,c) - print(o,"\n") - print(io,conseq(c)) + if conseq(c) typeof Begin : + print-all(o, ["when " pred(c) " :"]) + print-debug(o,c) + print(o,"\n") + print(io,conseq(c)) + else : + print-all(o, ["when " pred(c) " : " conseq(c)]) + print-debug(o,c) if alt(c) not-typeof EmptyStmt : print(o, "\nelse :") print(io, "\n") @@ -277,7 +289,7 @@ defmethod map (f: Expression -> Expression, e:Expression) -> Expression : public defmulti map (f: Expression -> Expression, c:?T&Stmt) -> T defmethod map (f: Expression -> Expression, c:Stmt) -> Stmt : match(c) : - (c:DefAccessor) : DefAccessor(info(c),name(c), f(source(c)), f(index(c))) + (c:DefAccessor) : DefAccessor(info(c),name(c), f(source(c)), f(index(c)),acc-dir(c)) (c:DefNode) : DefNode(info(c),name(c), f(value(c))) (c:DefInstance) : DefInstance(info(c),name(c), f(module(c))) (c:Conditionally) : Conditionally(info(c),f(pred(c)), conseq(c), alt(c)) diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 6e030d24..6ad4e63f 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -27,7 +27,8 @@ public val standard-passes = to-list $ [ Inline() SplitExp() CheckLowForm() - ToRealIR() ] + ToRealIR() + Pad() ] ;=============== WORKING IR ================================ public definterface Kind public defstruct WireKind <: Kind @@ -108,13 +109,13 @@ defn swap (f:Flip) -> Flip : DEFAULT : REVERSE REVERSE : DEFAULT -defn swap (d:Direction) -> Direction : +defn swap (d:PortDirection) -> PortDirection : switch {_ == d} : OUTPUT : INPUT INPUT : OUTPUT -public defn times (flip:Flip,d:Direction) -> Direction : flip * d -public defn times (d:Direction,flip:Flip) -> Direction : +public defn times (flip:Flip,d:PortDirection) -> PortDirection : flip * d +public defn times (d:PortDirection,flip:Flip) -> PortDirection : switch {_ == flip} : DEFAULT : d REVERSE : swap(d) @@ -135,13 +136,13 @@ defn to-field (p:Port) -> Field : else if direction(p) == INPUT : Field(name(p),REVERSE,type(p)) else : error("Shouldn't be here") -defn to-dir (g:Gender) -> Direction : +defn to-dir (g:Gender) -> PortDirection : switch {_ == g} : MALE : INPUT FEMALE : OUTPUT defn gender (s:DefAccessor) -> Gender : - switch {_ == dir(s)} : + switch {_ == acc-dir(s)} : READ : MALE WRITE : FEMALE INFER : UNKNOWN-GENDER @@ -331,6 +332,8 @@ defn to-working-ir (c:Circuit) : (e:Subfield) : WSubfield(exp(e), name(e), type(e), UNKNOWN-GENDER) (e:Index) : WIndex(exp(e), value(e), type(e), UNKNOWN-GENDER) (e) : e + defn to-stmt (s:Stmt) -> Stmt : + map{to-stmt,_} $ map(to-exp,s) Circuit(info(c),modules*, main(c)) where : val modules* = @@ -1342,7 +1345,7 @@ public defn expand-whens (c:Circuit) -> Circuit : if direction(p) == OUTPUT : val ref = WRef(name(p),type(p),PortKind(),FEMALE) if has-nul?(table[name(p)]) : - add(errors,RefNotInitialized(info(p), name(p)) + add(errors,RefNotInitialized(info(p), name(p))) else : add{cons,_} $ Connect(FileInfo(),ref,to-exp(table[name(p)]) as Expression) defn expand-whens (s:Stmt, table:HashTable,decs:Vector,cons:Vector) -> Stmt : @@ -1352,7 +1355,7 @@ public defn expand-whens (c:Circuit) -> Circuit : add(decs,s) val ref = WRef(name(s),type(s),NodeKind(),FEMALE) if has-nul?(table[name(s)]) : - add(errors,RefNotInitialized(info(s), name(s)) + add(errors,RefNotInitialized(info(s), name(s))) else : add{cons,_} $ Connect(info(s),ref,to-exp(table[name(s)]) as Expression) (s:DefRegister) : add(decs,s) @@ -1361,12 +1364,12 @@ public defn expand-whens (c:Circuit) -> Circuit : (e:Expression) : val ref = WRef(name(s),type(s),NodeKind(),FEMALE) val en = to-exp(optimize $ get-write-enable(table[name(s)])) as Expression - if en == UIntValue(1,UnknownWidth()) : + if en == UIntValue(to-long(1),UnknownWidth()) : add{cons,_} $ Connect(info(s),ref,e) else : - add{cons,_} $ Conditionally(en,Connect(info(s),ref,e),EmptyStmt()) + add{cons,_} $ Conditionally(info(s),en,Connect(info(s),ref,e),EmptyStmt()) (e:False) : - add(errors,RefNotConnected(info(s), name(s)) + add(errors,RefNotConnected(info(s), name(s))) (s:DefAccessor) : add(decs,s) val t = type(type(source(s)) as VectorType) @@ -1377,12 +1380,12 @@ public defn expand-whens (c:Circuit) -> Circuit : match(e) : (e:Expression) : val en = (to-exp $ optimize $ get-write-enable(table[n])) as Expression - if en == UIntValue(1,UnknownWidth()) : + if en == UIntValue(to-long(1),UnknownWidth()) : add{cons,_} $ Connect(info(s),ref,e) else : - add{cons,_} $ Conditionally(en,Connect(info(s),ref,e),EmptyStmt()) + add{cons,_} $ Conditionally(info(s),en,Connect(info(s),ref,e),EmptyStmt()) (e:False) : - add(errors,RefNotConnected(info(s), n) + add(errors,RefNotConnected(info(s), n)) (s:DefInstance) : add(decs,s) for f in fields(type(module(s)) as BundleType) map : @@ -1393,7 +1396,7 @@ public defn expand-whens (c:Circuit) -> Circuit : val ref = WRef(x,type(module(s)),InstanceKind(),FEMALE) val sref = WSubfield(ref,f,bundle-field-type(type(module(s)),f),FEMALE) if has-nul?(table[n]) : - add(errors,RefNotInitialized(info(s), n) + add(errors,RefNotInitialized(info(s), n)) else : add{cons,_} $ Connect(info(s),sref,to-exp(table[n]) as Expression) (s:Connect|Conditionally|OnReset|Begin|EmptyStmt) : false s @@ -1404,7 +1407,7 @@ public defn expand-whens (c:Circuit) -> Circuit : (m:InModule) : val assign = HashTable(symbol-hash) val resets = HashTable(symbol-hash) - ;val flattn = HashTable(symbol-hash) + val flattn = HashTable(symbol-hash) for p in ports(m) do : if direction(p) == OUTPUT : @@ -1431,10 +1434,12 @@ public defn expand-whens (c:Circuit) -> Circuit : expand-whens(body(m),table,decs,cons) InModule(info(m),name(m),ports(m),Begin(append(to-list(decs),to-list(cons)))) - Circuit(info(c),modules*, main(c)) where : + val c* = Circuit(info(c),modules*, main(c)) where : val modules* = for m in modules(c) map : expand-whens(m) + throw(PassExceptions(errors)) when not empty?(errors) + c* ;;================ INFER WIDTHS ============================= @@ -1654,6 +1659,8 @@ defn gen-constraints (m:Module, h:HashTable, v:Vector) -> Mod defn gen-constraints-s (s:Stmt) -> Stmt : match(map(gen-constraints-s,s)) : (s:DefWire) : DefWire(info(s),name(s),h[name(s)]) + (s:DefRegister) : DefRegister(info(s),name(s),h[name(s)]) + (s:DefAccessor) : DefAccessor(info(s),name(s),gen-constraints(source(s)),gen-constraints(index(s)), acc-dir(s)) (s:DefInstance) : DefInstance(info(s),name(s),gen-constraints(module(s))) (s:DefMemory) : DefMemory(info(s),name(s),h[name(s)] as VectorType,seq?(s)) (s:DefNode) : @@ -1672,7 +1679,7 @@ defn gen-constraints (m:Module, h:HashTable, v:Vector) -> Mod val p = gen-constraints(pred(s)) add(v,WGeq(width!(type(p)),IntWidth(1))) add(v,WGeq(IntWidth(1),width!(type(p)))) - Conditionally(info(s),p,conseq(s),alt(s)) + map(gen-constraints-s,Conditionally(info(s),p,conseq(s),alt(s))) (s) : s defn gen-constraints (e:Expression) -> Expression : @@ -1708,8 +1715,11 @@ defn build-environment (c:Circuit,m:Module,h:HashTable) -> HashTabl defn build-environment (s:Stmt) -> False : match(s) : (s:DefWire) : h[name(s)] = remove-unknowns(type(s)) + (s:DefRegister) : h[name(s)] = remove-unknowns(type(s)) (s:DefInstance) : h[name(s)] = h[name(module(s) as WRef)] (s:DefMemory) : h[name(s)] = remove-unknowns(type(s)) + (s:DefAccessor) : + h[name(s)] = remove-unknowns(type(type(source(s)) as VectorType)) (s:DefNode) : h[name(s)] = remove-unknowns(type(value(s))) (s) : false do(build-environment,s) @@ -1746,7 +1756,9 @@ defn reduce-var-widths (c:Circuit,h:HashTable) -> Circuit : (w:MinusWidth) : apply(solve(arg1(w)),solve(arg2(w)),{_ - _}) (w:ExpWidth) : apply(2,solve(arg1(w)),{pow(_,_) - 1}) (w:IntWidth) : width(w) - (w) : error("Shouldn't be here") + (w) : + println(w) + error("Shouldn't be here") val s = solve(w) if s typeof Int : IntWidth(s as Int) @@ -1889,14 +1901,16 @@ defn split-exp (c:Circuit) : add(v,DefNode(info,n*,e)) WRef(n*,type(e),NodeKind(),UNKNOWN-GENDER) (e) : e + defn f (s:Stmt) -> False: split-exp-s(s,v,sh) match(s) : (s:Begin) : - defn f (s:Stmt) -> False: split-exp-s(s,v,sh) do(f,s) - (s:Conditionally) : error("Shouldn't be here") + (s:Conditionally) : + add(v,map(split-exp-e{_,false,info(s)},s)) + do(f,s) (s:Connect) : match(loc(s)) : - (e:WritePort) : add(v,map(split-exp-e{_,full-name(exp(s)),info(s)},s)) + ;(e:WritePort) : add(v,map(split-exp-e{_,full-name(exp(s)),info(s)},s)) (e) : add(v,map(split-exp-e{_,full-name(loc(s)),info(s)},s)) (s:DefNode) : add(v,map(split-exp-e{_,name(s),info(s)},s)) (s) : add(v,map(split-exp-e{_,false,info(s)},s)) @@ -1934,7 +1948,6 @@ defn to-real-ir (c:Circuit) : (e) : e defn to-stmt (s:Stmt) : match(map(to-exp,s)) : - (e:DefAccessor) : error("Shouldn't be here") (e:ConnectToIndexed) : error("Shouldn't be here") (e:ConnectFromIndexed) : error("Shouldn't be here") (e) : map(to-stmt,e) @@ -1993,7 +2006,7 @@ public defn special-rename (original-sym:Symbol,new-sym:Symbol,c:Circuit) : (s:DefInstance) : DefInstance(info(s),rename(name(s)),module(s)) (s:DefMemory) : DefMemory(info(s),rename(name(s)),type(s),seq?(s)) (s:DefNode) : DefNode(info(s),rename(name(s)),value(s)) - (s:DefAccessor) : DefAccessor(info(s),rename(name(s)),source(s),index(s)) + (s:DefAccessor) : DefAccessor(info(s),rename(name(s)),source(s),index(s),acc-dir(s)) (s) : map(to-stmt,s) defn to-port (p:Port) -> Port : Port(info(p),rename(name(p)),direction(p),type(p)) @@ -2006,3 +2019,80 @@ public defn special-rename (original-sym:Symbol,new-sym:Symbol,c:Circuit) : (m:ExModule) : m +;========== Pad Widths ================== + +public defstruct Pad <: Pass +public defmethod pass (b:Pad) -> (Circuit -> Circuit) : pad-widths +public defmethod name (b:Pad) -> String : "Pad Widths" + +defn int-width! (t:Type) -> Int : + match(width!(t)) : + (w:IntWidth) : width(w) + (w) : error("Non-int width") + +defn set-width (desired:Int,t:Type) -> Type : + match(t) : + (t:UIntType) : UIntType(IntWidth(desired)) + (t:SIntType) : SIntType(IntWidth(desired)) + (t) : error("Non-ground type") + +defn pad-widths-e (desired:Int,e:Expression) -> Expression : + defn trim (desired:Int, e:Expression) : + ;; println-all(["TRIM " desired " e " e]) + DoPrim(BITS-SELECT-OP,list(e),list(desired - 1, 0),set-width(desired,type(e))) + defn pad (desired:Int, e:Expression) : + ;; println-all(["PAD " desired " e " e]) + DoPrim(PAD-OP,list(e),list(desired),set-width(desired,type(e))) + defn trim-pad (desired:Int, e:Expression) : + val i = int-width!(type(e)) + if i > desired : trim(desired, e) + else if i == desired : e + else : pad(desired, e) + defn self-pad-widths-e (e:Expression) -> Expression : + pad-widths-e(int-width!(type(e)), e) + ;; println-all(["PAD-E " desired " " e]) + match(e) : + (e:DoPrim) : + val new-desired = reduce(max, 0, map(int-width!{type(_)}, args(e))) + ;; println-all([" NEW DESIRED " new-desired]) + val e* = + if contains?([CONCAT-OP, DYN-SHIFT-RIGHT-OP, DYN-SHIFT-LEFT-OP], op(e)) : + DoPrim(op(e), map(self-pad-widths-e, args(e)), consts(e), type(e)) + else if contains?([MUX-OP], op(e)) : + DoPrim(op(e), list(pad-widths-e(1, args(e)[0]), pad-widths-e(new-desired, args(e)[1]), pad-widths-e(new-desired, args(e)[2])), consts(e), type(e)) + else : + map(pad-widths-e{new-desired,_},e) + trim-pad(desired, e*) + (e:WRef|WSubfield|WIndex) : + trim-pad(desired, e) + (e:UIntValue) : + val i = int-width!(type(e)) + if i > desired : trim(desired, e) + else : UIntValue(value(e),IntWidth(desired)) + (e:SIntValue) : + val i = int-width!(type(e)) + if i > desired : trim(desired, e) + else : SIntValue(value(e),IntWidth(desired)) + (e) : error(to-string $ e) + +defn pad-widths-s (s:Stmt) -> Stmt : + ;; println-all(["PAD-S " s]) + match(map(pad-widths-s,s)) : + (s:Connect) : + val i = int-width!(type(loc(s))) + val loc* = pad-widths-e(i,loc(s)) + val exp* = pad-widths-e(i,exp(s)) + Connect(info(s),loc*,exp*) + (s:DefNode) : + val i = int-width!(type(value(s))) + val exp* = pad-widths-e(i,value(s)) + DefNode(info(s),name(s),exp*) + (s) : s + +public defn pad-widths (c:Circuit) -> Circuit : + Circuit{info(c),_,main(c)} $ + for m in modules(c) map : + match(m) : + (m:ExModule) : m + (m:InModule) : InModule(info(m),name(m),ports(m),pad-widths-s(body(m))) + diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index 0e04df8a..0367c333 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -4,43 +4,6 @@ defpackage firrtl/verilog : import firrtl/ir-utils import firrtl/ir2 -public defstruct RemoveSeqMem <: Pass -public defmethod pass (b:RemoveSeqMem) -> (Circuit -> Circuit) : remove-smem{_} -public defmethod name (b:RemoveSeqMem) -> String : "Remove SeqMem" -public defmethod short-name (b:RemoveSeqMem) -> String : "remove-smem" - - -;============ Utilz ============= - -;============ Remove Seq Mem ============= - -defn remove-smem (m:InModule) -> InModule : - val hash = get-sym-hash(m) - val smems = Vector() - defn remove-smem-s (s:Stmt) -> Stmt : - map{remove-smem-s,_} $ match(s) : - (s:DefMemory) : - if seq?(s) : add(smems,name(s)) - DefMemory(info(s),name(s),type(s),false) - (s:DefAccessor) : - if dir(s) == WRITE and contains?(smems, name(source(s) as Ref)) : - val regged-index = firrtl-gensym(name(index(s) as Ref),hash) - val ref = Ref(regged-index,type(index(s))) - Begin $ to-list $ - [ DefRegister(info(s),regged-index,type(index(s))) - Connect(ref,index(s)) - DefAccessor(info(s),dir(s),name(s),source(s),ref) ] - else : s - (s) : s - - InModule(info(m),name(m),ports(m),remove-smem-s(body(m),hash)) - -public defn remove-smem (c:Circuit) -> Circuit : - for m in modules(c) do : - match(m) : - (m:InModule) : remove-smem(m) - (m:ExModule) : m - ;============ VERILOG ============== public defstruct Verilog <: Pass : @@ -49,10 +12,6 @@ public defmethod pass (b:Verilog) -> (Circuit -> Circuit) : emit-verilog{file(b) public defmethod name (b:Verilog) -> String : "To Verilog" public defmethod short-name (b:Verilog) -> String : "To Verilog" -defstruct DecAndConnect : - dec : Stmt - con : Connect - ;============ Utilz ============= defn width! (w:Width) -> Int : match(w) : @@ -105,9 +64,6 @@ defn emit (e:Expression) -> String : (e:SIntValue) : string-join $ [width!(type(e)) "'sd" value(e)] (e:Subfield) : error("Non-supported expression") (e:Index) : error("Non-supported expression") - (e:Register) : error("Non-supported expression") - (e:ReadPort) : error("Non-supported expression") - (e:WritePort) : error("Non-supported expression") (e:DoPrim) : val sargs = map(emit-as-type{_,type(e)},args(e)) val xargs = map(emit-signed-if-any{_,args(e)},args(e)) @@ -184,18 +140,20 @@ defn get-name (e:Expression) -> Symbol : (e) : error("Shouldn't be here") defn emit-module (m:InModule) : - val decs = HashTable(sym-hash) ; all declarations - val cons = HashTable(sym-hash) ; all connections + val decs = HashTable(symbol-hash) ; all declarations + val cons = HashTable(symbol-hash) ; all connections + val ens = HashTable(symbol-hash) ; all enables defn build-table (m:InModule) : defn build-table (s:Stmt) -> Stmt : match(map(build-table,map(remove-subfield,s))) : - (s:DefWire|DefReg|DefAccessor|DefMemory|DefNode|DefInstance) : decs[name(s)] = s + (s:DefWire|DefRegister|DefAccessor|DefMemory|DefNode|DefInstance) : decs[name(s)] = s (s:Conditionally) : val n = get-name(loc(conseq(s) as Connect)) - cons[n] = s + ens[n] = pred(s) + cons[n] = exp(conseq(s) as Connect) (s:Connect) : val n = get-name(loc(s)) - cons[n] = s + cons[n] = exp(s) (s) : false s build-table(body(m)) @@ -211,135 +169,59 @@ defn emit-module (m:InModule) : val sh = get-sym-hash(m) - for (sym -> dec) in decs do : - match(value(dec)) : - (dec:DefWire) : - add(wires,["wire " get-width(type(s)) " " name(s) ";"]) - emit-blocking-connect(cons[sym]) - (dec:DefRegister) : - add(regs,["reg " get-width(type(s)) " " name(s) ";"]) - emit-nonblocking-connect(cons[sym]) - (dec:DefMemory) : + for x in decs do : + val sym = key(x) + match(value(x)) : + (s:DefWire) : + add(wires,["wire " get-width(type(s)) " " sym ";"]) + add(assigns,["assign " sym " = " emit(cons[sym]) ";"]) + (s:DefRegister) : + add(regs,["reg " get-width(type(s)) " " sym ";"]) + if key?(ens,sym) : + add(updates,["if(" emit(ens[sym]) ") begin"]) + add(updates,[" " sym " <= " emit(cons[sym]) ";"]) + add(updates,["end"]) + else : + add(updates,[sym " <= " emit(cons[sym]) ";"]) + (s:DefMemory) : val vtype = type(s) as VectorType - add(regs,["reg " get-width(type(vtype)) " " name(s) " [0:" size(vtype) "];"]) + add(regs,["reg " get-width(type(vtype)) " " sym " [0:" size(vtype) "];"]) add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"]) - add(inits,[" " name(s) "[initvar] = {" width!(type(vtype)) "{$random}};"]) + add(inits,[" " sym "[initvar] = {" width!(type(vtype)) "{$random}};"]) (s:DefNode) : - add(wires,["wire " get-width(type(value(s))) " " name(s) ";"]) - add(assigns,["assign " name(s) " = " emit(value(s)) ";"]) + add(wires,["wire " get-width(type(value(s))) " " sym ";"]) + add(assigns,["assign " sym " = " emit(value(s)) ";"]) (s:DefInstance) : - inst-ports[name(s)] = Vector() - insts[name(s)] = name(module(s) as Ref) + inst-ports[sym] = Vector() + insts[sym] = name(module(s) as Ref) for f in fields(type(module(s)) as BundleType) do : - val n* = to-symbol $ string-join $ [name(s) "_" name(f)] + val n* = to-symbol $ string-join $ [sym "_" name(f)] add(wires,["wire " get-width(type(f)) " " n* ";"]) - add(inst-ports[name(s)], ["." name(f) "( " n* " )"]) + add(inst-ports[sym], ["." name(f) "( " n* " )"]) (s:DefAccessor) : - switch {_ == dir(s)} : + switch {_ == acc-dir(s)} : READ : val mem-declaration = decs[name(source(s) as Ref)] - val con = cons[sym] - if seq?(mem-declaration) : + if seq?(mem-declaration as DefMemory) : + ; to make it sequential, register the index for an additional cycle val index* = Ref(firrtl-gensym(name(index(s) as Ref),sh),type(index(s))) - add(regs,[ "reg " get-width(type(index*)) " " name(index*) ";"]) ; to make it sequential, register the index for an additional cycle + add(regs,[ "reg " get-width(type(index*)) " " name(index*) ";"]) add(inits,[name(index*) " = {" width!(type(index*)) "{$random}};"]) add(updates,[name(index*) " <= " emit(index(s)) ";"]) - add(assigns,["assign " n " = " emit(mem(s)) "[" emit(index*) "];"]) - else : - add(assigns,["assign " n " = " emit(mem(s)) "[" emit(index(s)) "];"]) - - - - - defn emit-blocking-connect (s:Stmt) : - match(s) : - (s:Connect) : add(assigns,["assign " emit(loc(s)) " = " emit(exp(s)) ";"]) - (s:Conditionally) : error("Shouldn't be here") - defn emit-nonblocking-connect (s:Stmt) : - match(s) : - (s:Connect) : - add(updates,[n " <= " emit(value(reg)) ";"]) - (s:Conditionally) : - match(conseq(s)) : - (c:Connect) : - add(updates,["if(" emit(pred(s)) ") begin"]) - add(updates,[" " emit(loc(c) " <= " emit(exp(c)) ";"]) - add(updates,["end"]) - (c) : error("Shouldn't be here") - (s) : error("Shouldn't be here") - -; add(updates,["if(" en ") begin"]) -; add(updates,[" " emit(mem(wp)) "[" emit(index(wp)) "] <= " emit(exp(s)) ";"]) -; add(updates,["end"]) -; else : -; if exp(s) typeof Register : -; val n = name(loc(s) as Ref) -; val reg = exp(s) as Register -; add(inits,[n " = {" width!(type(reg)) "{$random}};"]) -; add(updates,["if(" emit(enable(reg)) ") begin"]) -; add(updates,[" " n " <= " emit(value(reg)) ";"]) -; add(updates,["end"]) -; else if exp(s) typeof ReadPort : -; val n = name(loc(s) as Ref) -; val rp = exp(s) as ReadPort -; match(h[name(mem(rp) as Ref)]) : -; (k:SeqMemKind) : -; val index* = Ref(firrtl-gensym(name(index(rp) as Ref),sh),type(index(rp))) -; add(regs,[ "reg " get-width(type(index*)) " " name(index*) ";"]) -; add(inits,[name(index*) " = {" width!(type(index*)) "{$random}};"]) -; add(updates,["if(" emit(enable(rp)) ") begin"]) -; add(updates,[" " name(index*) " <= " emit(index(rp)) ";"]) -; add(updates,["end"]) -; add(assigns,["assign " n " = " emit(mem(rp)) "[" emit(index*) "];"]) -; (k:ComMemKind) : -; add(assigns,["assign " n " = " emit(mem(rp)) "[" emit(index(rp)) "];"]) -; else : -; add(assigns,["assign " emit(loc(s)) " = " emit(exp(s)) ";"]) - - defn emit-s (s:Stmt) : - match(s) : - (s:DefWire) : - add(wires,["wire " get-width(type(s)) " " name(s) ";"]) - add(assigns,["assign " emit(loc(s)) " = " emit(exp(s)) ";"]) + ; emit read accessor + add(assigns,["assign " sym " = " emit(source(s)) "[" emit(index*) "];"]) + else : + ; emit read accessor + add(assigns,["assign " sym " = " emit(source(s)) "[" emit(index(s)) "];"]) + WRITE : + if key?(ens,sym) : + add(updates,["if(" emit(ens[sym]) ") begin"]) + add(updates,[" " emit(source(s)) "[" emit(index(s)) "] <= " emit(cons[sym]) ";"]) + add(updates,["end"]) + else : + add(updates,[emit(source(s)) "[" emit(index(s)) "] <= " emit(cons[sym]) ";"]) - (s:DefRegister) : add(regs,["reg " get-width(type(s)) " " name(s) ";"]) - (s:DefAccessor) : - switch {_ == dir(s)} : - READ : - match(h[name(source(s) as Ref)]) : - (k:SeqMemKind) : - val index* = Ref(firrtl-gensym(name(index(rp) as Ref),sh),type(index(rp))) - add(regs,[ "reg " get-width(type(index*)) " " name(index*) ";"]) - add(inits,[name(index*) " = {" width!(type(index*)) "{$random}};"]) - add(updates,["if(" emit(enable(rp)) ") begin"]) - add(updates,[" " name(index*) " <= " emit(index(rp)) ";"]) - add(updates,["end"]) - add(assigns,["assign " n " = " emit(mem(rp)) "[" emit(index*) "];"]) - (k:ComMemKind) : - add(assigns,["assign " n " = " emit(mem(rp)) "[" emit(index(rp)) "];"]) - (s:DefInstance) : - inst-ports[name(s)] = Vector() - insts[name(s)] = name(module(s) as Ref) - for f in fields(type(module(s)) as BundleType) do : - val n* = to-symbol $ string-join $ [name(s) "_" name(f)] - add(wires,["wire " get-width(type(f)) " " n* ";"]) - add(inst-ports[name(s)], ["." name(f) "( " n* " )"]) - (s:DefMemory) : - val vtype = type(s) as VectorType - add(regs,["reg " get-width(type(vtype)) " " name(s) " [0:" size(vtype) "];"]) - add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"]) - add(inits,[" " name(s) "[initvar] = {" width!(type(vtype)) "{$random}};"]) - (s:DefNode) : - add(wires,["wire " get-width(type(value(s))) " " name(s) ";"]) - add(assigns,["assign " name(s) " = " emit(value(s)) ";"]) - (s:Begin) : do(emit-s, body(s)) - (s:Conditionally) : emit-pred-connect(pred(s),conseq(s) as Connect) - (s:Connect) : emit-pred-connect(UIntValue(1,1),s) - (s) : s - - - ;==== Actually printing module ===== val port-indent = " " print-all(["module " name(m) "(input clk, input reset,\n"]) diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir index eb396bcf..0daec379 100644 --- a/test/passes/expand-accessors/accessor-mem.fir +++ b/test/passes/expand-accessors/accessor-mem.fir @@ -6,15 +6,17 @@ circuit top : cmem m : UInt<32>[2][2][2] wire i : UInt<4> i := UInt(1) - accessor a = m[i] ;CHECK: accessor a = m[i] - accessor b = a[i] ;CHECK: b := (a[0] a[1])[i] - accessor c = b[i] ;CHECK: c := (b[0] b[1])[i] + infer accessor a = m[i] ;CHECK: read accessor a = m[i] + infer accessor b = a[i] ;CHECK: b := (a[0] a[1])[i] + infer accessor c = b[i] ;CHECK: c := (b[0] b[1])[i] wire j : UInt j := c - accessor x = m[i] ;CHECK: accessor x = m[i] - accessor y = x[i] ;CHECK: (x[0] x[1])[i] := y - accessor z = y[i] ;CHECK: (y[0] y[1])[i] := z + infer accessor x = m[i] ;CHECK: write accessor x = m[i] + infer accessor y = x[i] ;CHECK: (x[0] x[1])[i] := y + y[0] := UInt(1) + y[1] := UInt(1) + infer accessor z = y[i] ;CHECK: (y[0] y[1])[i] := z z := j ; CHECK: Finished Expand Accessors diff --git a/test/passes/expand-accessors/accessor-vec.fir b/test/passes/expand-accessors/accessor-vec.fir index 81c44d1b..5cdad6c7 100644 --- a/test/passes/expand-accessors/accessor-vec.fir +++ b/test/passes/expand-accessors/accessor-vec.fir @@ -4,25 +4,43 @@ circuit top : module top : wire m : UInt<32>[2][2][2] + m[0][0][0] := UInt(1) + m[1][0][0] := UInt(1) + m[0][1][0] := UInt(1) + m[1][1][0] := UInt(1) + m[0][0][1] := UInt(1) + m[1][0][1] := UInt(1) + m[0][1][1] := UInt(1) + m[1][1][1] := UInt(1) wire i : UInt i := UInt(1) - accessor a = m[i] ;CHECK: a := (m[0] m[1])[i] - accessor b = a[i] ;CHECK: b := (a[0] a[1])[i] - accessor c = b[i] ;CHECK: c := (b[0] b[1])[i] + infer accessor a = m[i] ;CHECK: a := (m[0] m[1])[i] + infer accessor b = a[i] ;CHECK: b := (a[0] a[1])[i] + infer accessor c = b[i] ;CHECK: c := (b[0] b[1])[i] wire j : UInt j := c - accessor x = m[i] ;CHECK: (m[0] m[1])[i] := x - accessor y = x[i] ;CHECK: (x[0] x[1])[i] := y - accessor z = y[i] ;CHECK: (y[0] y[1])[i] := z + infer accessor x = m[i] ;CHECK: (m[0] m[1])[i] := x + x[0][0] := UInt(1) + x[1][0] := UInt(1) + x[0][1] := UInt(1) + x[1][1] := UInt(1) + infer accessor y = x[i] ;CHECK: (x[0] x[1])[i] := y + infer accessor z = y[i] ;CHECK: (y[0] y[1])[i] := z + y[0] := UInt(1) + y[1] := UInt(1) z := j wire p : {n : UInt<32>[2]} - accessor q = p.n[i] ;CHECK: (p.n[0] p.n[1])[i] := q + p.n[0] := UInt(1) + p.n[1] := UInt(1) + infer accessor q = p.n[i] ;CHECK: (p.n[0] p.n[1])[i] := q q := j wire r : {m : UInt<32>}[2] - accessor s = r[i] ;CHECK: s := (r[0] r[1])[i] + r[0].m := UInt(1) + r[1].m := UInt(1) + infer accessor s = r[i] ;CHECK: s := (r[0] r[1])[i] j := s.m ; CHECK: Finished Expand Accessors diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir index 9d375087..ea453ab1 100644 --- a/test/passes/expand-connect-indexed/bundle-vecs.fir +++ b/test/passes/expand-connect-indexed/bundle-vecs.fir @@ -12,7 +12,7 @@ circuit top : ; CHECK: wire a$1$x : UInt<32> ; CHECK: wire a$1$y : UInt<32> - accessor b = a[i] + infer accessor b = a[i] ; CHECK: wire b$x : UInt<32> ; CHECK: wire b$y : UInt<32> ; CHECK: b$x := a$0$x diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir index 4f8c31e2..261ebf02 100644 --- a/test/passes/expand-whens/bundle-init.fir +++ b/test/passes/expand-whens/bundle-init.fir @@ -15,8 +15,8 @@ circuit top : r.y := b on-reset r := w -; CHECK: r$x := Register(mux(reset, w$x, a), UInt(1)) -; CHECK: r$y := Register(b, UInt(1)) +; CHECK: when UInt(1) : r$x := mux(reset, w$x, a) +; CHECK: when UInt(1) : r$y := b ; CHECK: a := UInt(1) ; CHECK: b := UInt(2) ; CHECK: w$x := b diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir index f7ac8337..4d23a549 100644 --- a/test/passes/expand-whens/nested-whens.fir +++ b/test/passes/expand-whens/nested-whens.fir @@ -11,6 +11,14 @@ circuit top : wire y : UInt wire z : UInt wire w : UInt + p := UInt(1) + q := UInt(1) + a := UInt(1) + b := UInt(1) + x := UInt(1) + y := UInt(1) + z := UInt(1) + w := UInt(1) on-reset r := w when p : @@ -20,5 +28,5 @@ circuit top : on-reset r := y r := b r := z -; CHECK: r := Register(mux(reset, mux(q, y, mux(p, x, w)), z), UInt(1)) +; CHECK: when UInt(1) : r := mux(reset, mux(q, y, mux(p, x, w)), z) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir index 114e5b5b..4e6ea1e5 100644 --- a/test/passes/expand-whens/one-when.fir +++ b/test/passes/expand-whens/one-when.fir @@ -7,21 +7,22 @@ circuit top : wire i : UInt<1> wire p : UInt<1> wire j : UInt<1> + j := UInt(1) reg r : UInt<1> p := j when p : on-reset r := i - accessor a = m[i] + infer accessor a = m[i] i := a - accessor b = m[i] + infer accessor b = m[i] b := i else : - accessor c = m[i] + infer accessor c = m[i] i := c - accessor d = m[i] + infer accessor d = m[i] d := i - accessor e = m[i] + infer accessor e = m[i] when p : p := i when e : diff --git a/test/passes/expand-whens/partial-init.fir b/test/passes/expand-whens/partial-init.fir index c9afd86c..03b1f965 100644 --- a/test/passes/expand-whens/partial-init.fir +++ b/test/passes/expand-whens/partial-init.fir @@ -4,6 +4,16 @@ circuit top : module top : reg r : UInt<1>[10] + r[0] := UInt(1) + r[1] := UInt(1) + r[2] := UInt(1) + r[3] := UInt(1) + r[4] := UInt(1) + r[5] := UInt(1) + r[6] := UInt(1) + r[7] := UInt(1) + r[8] := UInt(1) + r[9] := UInt(1) on-reset r[3] := UInt(0) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/reg-wdoc.fir b/test/passes/expand-whens/reg-wdoc.fir index ad2089c2..ad191a01 100644 --- a/test/passes/expand-whens/reg-wdoc.fir +++ b/test/passes/expand-whens/reg-wdoc.fir @@ -2,6 +2,7 @@ circuit top : module top : wire p : UInt + p := UInt(1) when p : reg r : UInt on-reset r := UInt(10) diff --git a/test/passes/expand-whens/scoped-reg.fir b/test/passes/expand-whens/scoped-reg.fir index 7f2632f4..d119932f 100644 --- a/test/passes/expand-whens/scoped-reg.fir +++ b/test/passes/expand-whens/scoped-reg.fir @@ -2,6 +2,7 @@ circuit top : module top : wire p : UInt + p := UInt(1) when p : reg r : UInt on-reset r := UInt(10) diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir index fb537303..b6c98263 100644 --- a/test/passes/expand-whens/two-when.fir +++ b/test/passes/expand-whens/two-when.fir @@ -5,31 +5,34 @@ circuit top : module top : cmem m :{ x : UInt<1>, y : UInt<1> }[2] wire i : UInt<1> + i := UInt(1) wire p : UInt<1> + p := UInt(1) wire q : { x : UInt<1>, y : UInt<1> } when p : wire p2 : UInt<1> - reg r5 : UInt<1> + p2 := UInt(1) when p2 : - accessor a = m[i] + infer accessor a = m[i] q := a - accessor b = m[i] + infer accessor b = m[i] b := q else : - accessor c = m[i] + infer accessor c = m[i] q := c - accessor d = m[i] + infer accessor d = m[i] d := q else : wire p3 : UInt<1> + p3 := UInt(1) when p3 : - accessor w = m[i] + infer accessor w = m[i] q := w - accessor x = m[i] + infer accessor x = m[i] x := q else : - accessor y = m[i] + infer accessor y = m[i] q := y - accessor z = m[i] + infer accessor z = m[i] z := q ; CHECK: Finished Expand Whens diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir index 5018aeef..892103d2 100644 --- a/test/passes/infer-types/bundle.fir +++ b/test/passes/infer-types/bundle.fir @@ -8,5 +8,10 @@ circuit top : node y = z.y ;CHECK: node y = z@, flip y : SInt@}>.y@ wire a : UInt<3>[10] ;CHECK: wire a : UInt<3>[10]@@[10]@> node b = a[2] ;CHECK: node b = a@[10]@>[2]@ - accessor c = a[UInt(3)] ;CHECK: accessor c = a@[10]@>[UInt(3)] + read accessor c = a[UInt(3)] ;CHECK: read accessor c = a@[10]@>[UInt(3)] ; CHECK: Finished Infer Types +; CHECK: Resolve Genders +; CHECK: read accessor c = a@[10]@>[UInt(3)] +; CHECK: Finished Resolve Genders + + -- cgit v1.2.3 From c8d1fc06443e81374b1af95e17e3ecbecf863700 Mon Sep 17 00:00:00 2001 From: azidar Date: Mon, 6 Jul 2015 17:45:44 -0700 Subject: Added chisel feedback to firrtl spec. Datapath_new triggers too large a width error --- notes/chisel-feedback-7.6.15.txt | 8 + test/chisel3/Datapath_new.fir | 355 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 363 insertions(+) create mode 100644 notes/chisel-feedback-7.6.15.txt create mode 100644 test/chisel3/Datapath_new.fir diff --git a/notes/chisel-feedback-7.6.15.txt b/notes/chisel-feedback-7.6.15.txt new file mode 100644 index 00000000..5f5bc8cc --- /dev/null +++ b/notes/chisel-feedback-7.6.15.txt @@ -0,0 +1,8 @@ +Firrtl spec feedback + +add limited support for zero width wires? + +Add more explanation for what types of passes +spec of what chisel3/firrtl whole compiler toolchain looks like + +Why is verilog generation unreadable and slow for chisel 2.0? diff --git a/test/chisel3/Datapath_new.fir b/test/chisel3/Datapath_new.fir new file mode 100644 index 00000000..9f018394 --- /dev/null +++ b/test/chisel3/Datapath_new.fir @@ -0,0 +1,355 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s +;CHECK: Done! + +circuit Datapath : + module ALU : + input B : UInt<32> + output out : UInt<32> + output sum : UInt<32> + input A : UInt<32> + input alu_op : UInt<4> + + node shamt = bits(B, 4, 0) + node T_426 = add-wrap(A, B) + node T_427 = sub-wrap(A, B) + node T_428 = as-SInt(A) + node T_429 = dshr(T_428, shamt) + node T_430 = as-UInt(T_429) + node T_431 = dshr(A, shamt) + node T_432 = dshl(A, shamt) + node T_433 = as-SInt(A) + node T_434 = as-SInt(B) + node T_435 = lt(T_433, T_434) + node T_436 = lt(A, B) + node T_437 = bit-and(A, B) + node T_438 = bit-or(A, B) + node T_439 = bit-xor(A, B) + node T_440 = eq(UInt<4>(10), alu_op) + node T_441 = mux(T_440, A, B) + node T_442 = eq(UInt<4>(4), alu_op) + node T_443 = mux(T_442, T_439, T_441) + node T_444 = eq(UInt<4>(3), alu_op) + node T_445 = mux(T_444, T_438, T_443) + node T_446 = eq(UInt<4>(2), alu_op) + node T_447 = mux(T_446, T_437, T_445) + node T_448 = eq(UInt<4>(7), alu_op) + node T_449 = mux(T_448, T_436, T_447) + node T_450 = eq(UInt<4>(5), alu_op) + node T_451 = mux(T_450, T_435, T_449) + node T_452 = eq(UInt<4>(6), alu_op) + node T_453 = mux(T_452, T_432, T_451) + node T_454 = eq(UInt<4>(8), alu_op) + node T_455 = mux(T_454, T_431, T_453) + node T_456 = eq(UInt<4>(9), alu_op) + node T_457 = mux(T_456, T_430, T_455) + node T_458 = eq(UInt<4>(1), alu_op) + node T_459 = mux(T_458, T_427, T_457) + node T_460 = eq(UInt<4>(0), alu_op) + node T_461 = mux(T_460, T_426, T_459) + out := T_461 + node T_462 = bit(alu_op, 0) + node T_463 = sub-wrap(UInt<1>(0), B) + node T_464 = mux(T_462, T_463, B) + node T_465 = add-wrap(A, T_464) + sum := T_465 + module BrCond : + output taken : UInt<1> + input rs2 : UInt<32> + input rs1 : UInt<32> + input br_type : UInt<3> + + node eq = eq(rs1, rs2) + node neq = bit-not(eq) + node T_466 = as-SInt(rs1) + node T_467 = as-SInt(rs2) + node lt = lt(T_466, T_467) + node ge = bit-not(lt) + node ltu = lt(rs1, rs2) + node geu = bit-not(ltu) + node T_468 = eq(br_type, UInt<3>(2)) + node T_469 = bit-and(T_468, eq) + node T_470 = eq(br_type, UInt<3>(6)) + node T_471 = bit-and(T_470, neq) + node T_472 = bit-or(T_469, T_471) + node T_473 = eq(br_type, UInt<3>(1)) + node T_474 = bit-and(T_473, lt) + node T_475 = bit-or(T_472, T_474) + node T_476 = eq(br_type, UInt<3>(5)) + node T_477 = bit-and(T_476, ge) + node T_478 = bit-or(T_475, T_477) + node T_479 = eq(br_type, UInt<3>(0)) + node T_480 = bit-and(T_479, ltu) + node T_481 = bit-or(T_478, T_480) + node T_482 = eq(br_type, UInt<3>(4)) + node T_483 = bit-and(T_482, geu) + node T_484 = bit-or(T_481, T_483) + taken := T_484 + module RegFile : + input raddr1 : UInt<5> + input raddr2 : UInt<5> + output rdata1 : UInt<32> + output rdata2 : UInt<32> + input wen : UInt<1> + input waddr : UInt<5> + input wdata : UInt<32> + + cmem regs : UInt<32>[32] + node T_485 = eq(raddr1, UInt<1>(0)) + node T_486 = bit-not(T_485) + accessor T_487 = regs[raddr1] + node T_488 = mux(T_486, T_487, UInt<1>(0)) + rdata1 := T_488 + node T_489 = eq(raddr2, UInt<1>(0)) + node T_490 = bit-not(T_489) + accessor T_491 = regs[raddr2] + node T_492 = mux(T_490, T_491, UInt<1>(0)) + rdata2 := T_492 + node T_493 = eq(waddr, UInt<1>(0)) + node T_494 = bit-not(T_493) + node T_495 = bit-and(wen, T_494) + when T_495 : + accessor T_496 = regs[waddr] + T_496 := wdata + module ImmGenWire : + output out : UInt<32> + input inst_252 : UInt<32> + input sel : UInt<3> + + node T_497 = bits(inst_252, 31, 20) + node Iimm = as-SInt(T_497) + node T_498 = bits(inst_252, 31, 25) + node T_499 = bits(inst_252, 11, 7) + node T_500 = cat(T_498, T_499) + node Simm = as-SInt(T_500) + node T_501 = bit(inst_252, 31) + node T_502 = bit(inst_252, 7) + node T_503 = bits(inst_252, 30, 25) + node T_504 = bits(inst_252, 11, 8) + node T_505 = cat(T_501, T_502) + node T_506 = cat(T_504, UInt<1>(0)) + node T_507 = cat(T_503, T_506) + node T_508 = cat(T_505, T_507) + node Bimm = as-SInt(T_508) + node T_509 = bits(inst_252, 31, 12) + node T_510 = cat(T_509, UInt<12>(0)) + node Uimm = as-SInt(T_510) + node T_511 = bit(inst_252, 31) + node T_512 = bits(inst_252, 19, 12) + node T_513 = bit(inst_252, 20) + node T_514 = bits(inst_252, 30, 25) + node T_515 = bits(inst_252, 24, 21) + node T_516 = cat(T_512, T_513) + node T_517 = cat(T_511, T_516) + node T_518 = cat(T_515, UInt<1>(0)) + node T_519 = cat(T_514, T_518) + node T_520 = cat(T_517, T_519) + node Jimm = as-SInt(T_520) + node T_521 = bits(inst_252, 19, 15) + node Zimm = convert(T_521) + node T_522 = eq(UInt<3>(3), sel) + node T_523 = mux(T_522, Jimm, Zimm) + node T_524 = eq(UInt<3>(2), sel) + node T_525 = mux(T_524, Uimm, T_523) + node T_526 = eq(UInt<3>(4), sel) + node T_527 = mux(T_526, Bimm, T_525) + node T_528 = eq(UInt<3>(1), sel) + node T_529 = mux(T_528, Simm, T_527) + node T_530 = eq(UInt<3>(0), sel) + node T_531 = mux(T_530, Iimm, T_529) + node T_532 = as-UInt(T_531) + out := T_532 + module CSR : + output host : {status : UInt<32>, flip id : UInt<1>, tohost : UInt<32>} + input cmd : UInt<2> + input src : UInt<32> + output data : UInt<32> + input addr : UInt<12> + + reg reg_tohost : UInt<32> + on-reset reg_tohost := UInt<32>(0) + reg reg_status : UInt<32> + on-reset reg_status := UInt<32>(0) + host.tohost := reg_tohost + host.status := reg_status + node T_533 = eq(UInt<12>(1291), addr) + node T_534 = mux(T_533, host.id, UInt<1>(0)) + node T_535 = eq(UInt<12>(1290), addr) + node T_536 = mux(T_535, reg_status, T_534) + node T_537 = eq(UInt<12>(1310), addr) + node T_538 = mux(T_537, reg_tohost, T_536) + data := T_538 + node T_539 = eq(cmd, UInt<2>(1)) + when T_539 : + node T_540 = eq(addr, UInt<12>(1310)) + when T_540 : reg_tohost := src + node T_541 = eq(addr, UInt<12>(1290)) + when T_541 : reg_status := src + node T_542 = eq(cmd, UInt<2>(2)) + node T_543 = neq(src, UInt<1>(0)) + node T_544 = bit-and(T_542, T_543) + when T_544 : + node T_545 = eq(addr, UInt<12>(1310)) + when T_545 : + node T_546 = dshl(UInt<1>(1), src) + node T_547 = bit-or(data, T_546) + reg_tohost := T_547 + node T_548 = eq(addr, UInt<12>(1290)) + when T_548 : + node T_549 = dshl(UInt<1>(1), src) + node T_550 = bit-or(data, T_549) + reg_status := T_550 + node T_551 = eq(cmd, UInt<2>(3)) + node T_552 = neq(src, UInt<1>(0)) + node T_553 = bit-and(T_551, T_552) + when T_553 : + node T_554 = eq(addr, UInt<12>(1310)) + when T_554 : + node T_555 = dshl(UInt<1>(0), src) + node T_556 = bit-and(data, T_555) + reg_tohost := T_556 + node T_557 = eq(addr, UInt<12>(1290)) + when T_557 : + node T_558 = dshl(UInt<1>(0), src) + node T_559 = bit-and(data, T_558) + reg_status := T_559 + module Datapath : + output host : {status : UInt<32>, flip id : UInt<1>, tohost : UInt<32>} + input ctrl : {flip inst_424 : UInt<32>, pc_sel : UInt<1>, inst_type : UInt<1>, inst_re : UInt<1>, flip stall : UInt<1>, imm_sel : UInt<3>, wb_en : UInt<1>, wb_sel : UInt<2>, A_sel : UInt<1>, B_sel : UInt<1>, alu_op : UInt<4>, br_type : UInt<3>, data_re : UInt<1>, st_type : UInt<2>, ld_type : UInt<3>, csr_cmd : UInt<2>} + output icache : {re : UInt<1>, addr : UInt<32>, we : UInt<4>, din : UInt<32>, flip dout : UInt<32>} + output dcache : {re : UInt<1>, addr : UInt<32>, we : UInt<4>, din : UInt<32>, flip dout : UInt<32>} + input stall : UInt<1> + + inst alu of ALU + inst brCond of BrCond + inst regFile of RegFile + inst immGen of ImmGenWire + reg fe_inst : UInt<32> + on-reset fe_inst := UInt<32>(0) + reg fe_pc : UInt + reg ew_inst : UInt<32> + on-reset ew_inst := UInt<32>(0) + reg ew_pc : UInt + reg ew_alu : UInt + node T_560 = sub-wrap(UInt<14>(8192), UInt<3>(4)) + reg pc : UInt<14> + on-reset pc := T_560 + node T_561 = eq(ctrl.pc_sel, UInt<1>(1)) + node T_562 = bit-or(T_561, brCond.taken) + node T_563 = add-wrap(pc, UInt<3>(4)) + node iaddr = mux(T_562, alu.sum, T_563) + node T_564 = eq(ctrl.inst_type, UInt<1>(1)) + node T_565 = bit-or(T_564, brCond.taken) + node inst_425 = mux(T_565, UInt<32>(19), icache.dout) + icache.addr := iaddr + icache.re := ctrl.inst_re + node T_566 = eq(dcache.we, UInt<1>(0)) + node T_567 = bit-not(T_566) + node T_568 = bit-not(T_567) + node T_569 = bit-and(icache.re, T_568) + node T_570 = mux(T_569, iaddr, pc) + pc := T_570 + node T_571 = bit-not(stall) + when T_571 : + fe_pc := pc + fe_inst := inst_425 + ctrl.inst_424 := fe_inst + ctrl.stall := stall + node rd_addr = bits(fe_inst, 11, 7) + node rs1_addr = bits(fe_inst, 19, 15) + node rs2_addr = bits(fe_inst, 24, 20) + regFile.raddr1 := rs1_addr + regFile.raddr2 := rs2_addr + immGen.inst_252 := fe_inst + immGen.sel := ctrl.imm_sel + node T_572 = eq(rs1_addr, UInt<1>(0)) + node rs1NotZero = bit-not(T_572) + node T_573 = eq(rs2_addr, UInt<1>(0)) + node rs2NotZero = bit-not(T_573) + node T_574 = eq(ctrl.wb_sel, UInt<2>(0)) + node alutype = bit-and(ctrl.wb_en, T_574) + node ex_rd_addr = bits(ew_inst, 11, 7) + node T_575 = bit-and(alutype, rs1NotZero) + node T_576 = eq(rs1_addr, ex_rd_addr) + node T_577 = bit-and(T_575, T_576) + node rs1 = mux(T_577, ew_alu, regFile.rdata1) + node T_578 = bit-and(alutype, rs2NotZero) + node T_579 = eq(rs2_addr, ex_rd_addr) + node T_580 = bit-and(T_578, T_579) + node rs2 = mux(T_580, ew_alu, regFile.rdata2) + node T_581 = eq(ctrl.A_sel, UInt<1>(0)) + node T_582 = mux(T_581, rs1, fe_pc) + alu.A := T_582 + node T_583 = eq(ctrl.B_sel, UInt<1>(0)) + node T_584 = mux(T_583, rs2, immGen.out) + alu.B := T_584 + alu.alu_op := ctrl.alu_op + brCond.rs1 := rs1 + brCond.rs2 := rs2 + brCond.br_type := ctrl.br_type + node T_585 = bit(alu.sum, 1) + node T_586 = dshl(T_585, UInt<3>(4)) + node T_587 = bit(alu.sum, 0) + node T_588 = dshl(T_587, UInt<2>(3)) + node woffset = bit-or(T_586, T_588) + dcache.re := ctrl.data_re + node T_589 = mux(stall, ew_alu, alu.sum) + dcache.addr := T_589 + node T_590 = bits(alu.sum, 1, 0) + node T_591 = dshl(UInt<2>(3), T_590) + node T_592 = bits(alu.sum, 1, 0) + node T_593 = dshl(UInt<1>(1), T_592) + node T_594 = eq(UInt<2>(2), ctrl.st_type) + node T_595 = mux(T_594, T_593, UInt<4>(0)) + node T_596 = eq(UInt<2>(1), ctrl.st_type) + node T_597 = mux(T_596, T_591, T_595) + node T_598 = eq(UInt<2>(0), ctrl.st_type) + node T_599 = mux(T_598, UInt<4>(15), T_597) + node T_600 = mux(stall, UInt<4>(0), T_599) + dcache.we := T_600 + node T_601 = dshl(rs2, woffset) + dcache.din := T_601 + node T_602 = bit-not(stall) + when T_602 : + ew_pc := fe_pc + ew_inst := fe_inst + ew_alu := alu.out + node T_603 = bit(ew_alu, 1) + node T_604 = dshl(T_603, UInt<3>(4)) + node T_605 = bit(ew_alu, 0) + node T_606 = dshl(T_605, UInt<2>(3)) + node loffset = bit-or(T_604, T_606) + node lshift = dshr(dcache.dout, loffset) + node T_607 = as-SInt(dcache.dout) + node T_608 = bits(lshift, 15, 0) + node T_609 = as-SInt(T_608) + node T_610 = bits(lshift, 7, 0) + node T_611 = as-SInt(T_610) + node T_612 = bits(lshift, 15, 0) + node T_613 = convert(T_612) + node T_614 = bits(lshift, 7, 0) + node T_615 = convert(T_614) + node T_616 = eq(UInt<3>(4), ctrl.ld_type) + node T_617 = mux(T_616, T_615, T_607) + node T_618 = eq(UInt<3>(3), ctrl.ld_type) + node T_619 = mux(T_618, T_613, T_617) + node T_620 = eq(UInt<3>(2), ctrl.ld_type) + node T_621 = mux(T_620, T_611, T_619) + node T_622 = eq(UInt<3>(1), ctrl.ld_type) + node T_623 = mux(T_622, T_609, T_621) + node load = as-UInt(T_623) + inst csr of CSR + csr.host <> host + csr.src := ew_alu + node T_624 = bits(ew_inst, 31, 20) + csr.addr := T_624 + csr.cmd := ctrl.csr_cmd + node T_625 = add-wrap(ew_pc, UInt<3>(4)) + node T_626 = eq(UInt<2>(3), ctrl.wb_sel) + node T_627 = mux(T_626, csr.data, ew_alu) + node T_628 = eq(UInt<2>(2), ctrl.wb_sel) + node T_629 = mux(T_628, T_625, T_627) + node T_630 = eq(UInt<2>(1), ctrl.wb_sel) + node regWrite = mux(T_630, load, T_629) + regFile.wen := ctrl.wb_en + regFile.waddr := ex_rd_addr + regFile.wdata := regWrite -- cgit v1.2.3 From df4bae5c7a95d3a56f95d86212f083b7ba121da7 Mon Sep 17 00:00:00 2001 From: azidar Date: Tue, 7 Jul 2015 10:13:29 -0700 Subject: Pass most tests. The ones that do not pass are not expected to, yet --- src/main/stanza/passes.stanza | 12 +++++++----- test/chisel3/Core.fir | 6 +++--- test/chisel3/Datapath.fir | 6 +++--- test/chisel3/Datapath_new.fir | 6 +++--- test/chisel3/MemorySearch.fir | 2 +- test/chisel3/Mul.fir | 2 +- test/chisel3/Risc.fir | 10 +++++----- test/chisel3/Rom.fir | 2 +- test/chisel3/Stack.fir | 4 ++-- test/chisel3/Tbl.fir | 4 ++-- test/chisel3/Tile.fir | 14 +++++++------- test/errors/high-form/InvalidLOC.fir | 4 ---- test/features/BulkConnect.fir | 15 +++++++++++++++ test/features/SeqMem.fir | 9 +++++---- test/passes/infer-types/bundle.fir | 12 ++++++++++++ test/passes/infer-widths/dsh.fir | 3 +++ test/passes/infer-widths/simple.fir | 4 ++++ test/passes/jacktest/MemorySearch.fir | 2 +- test/passes/jacktest/Mul.fir | 2 +- test/passes/jacktest/Rom.fir | 2 +- test/passes/jacktest/Stack.fir | 4 ++-- test/passes/jacktest/Tbl.fir | 4 ++-- test/passes/jacktest/risc.fir | 10 +++++----- test/passes/lower-to-ground/accessor.fir | 8 ++++---- test/passes/lower-to-ground/bundle-vecs.fir | 4 ++-- test/passes/lower-to-ground/nested-vec.fir | 4 ++-- test/passes/lower-to-ground/test.fir | 3 +++ test/passes/resolve-genders/accessor.fir | 27 +++++++++++++++++++++------ test/riscv-mini/Core.fir | 6 +++--- 29 files changed, 121 insertions(+), 70 deletions(-) diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 6ad4e63f..b500f991 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -207,7 +207,7 @@ defmethod print (o:OutputStream, k:Kind) : (k:WriteAccessorKind) : "wacc" defn hasGender (e:?) : - e typeof WRef|WSubfield|WIndex + e typeof WRef|WSubfield|WIndex|DefAccessor defn hasWidth (e:?) : e typeof UIntType|SIntType|UIntValue|SIntValue @@ -622,7 +622,7 @@ defn resolve-genders (c:Circuit) : get-gender(name(s),MALE) DefInstance(info(s),name(s),resolve-expr(module(s),MALE)) (s:DefAccessor) : - val gender* = get-gender(name(s),UNKNOWN-GENDER) + val gender* = get-gender(name(s),gender(s)) val index* = resolve-expr(index(s),MALE) val source* = resolve-expr(source(s),gender*) DefAccessor(info(s),name(s),source*,index*,to-acc-dir(gender*)) @@ -702,17 +702,19 @@ defn expand-stmt (s:Stmt) -> Stmt : else : val vtype = type(type(source(s)) as VectorType) val wire = DefWire(info(s),name(s),vtype) - switch {gender(s) == _} : - MALE : Begin{list(wire,_)} $ ConnectFromIndexed( + switch {acc-dir(s) == _} : + READ : Begin{list(wire,_)} $ ConnectFromIndexed( info(s), index(s), WRef(name(wire),vtype,NodeKind(),FEMALE), expand-vector(source(s))) - FEMALE: Begin{list(wire,_)} $ ConnectToIndexed( + WRITE : Begin{list(wire,_)} $ ConnectToIndexed( info(s), index(s), expand-vector(source(s)), WRef(name(wire),vtype,NodeKind(),MALE)) + INFER : error("Shouldn't be here") + RDWR : error("Haven't implemented RDWR yet") (s) : map(expand-stmt,s) defn expand-accessors (c:Circuit) : diff --git a/test/chisel3/Core.fir b/test/chisel3/Core.fir index 5c446b3d..e9aef65f 100644 --- a/test/chisel3/Core.fir +++ b/test/chisel3/Core.fir @@ -100,19 +100,19 @@ circuit Core : cmem regs : UInt<32>[32] node T_1286 = eq(raddr1, UInt<1>(0)) node T_1287 = bit-not(T_1286) - accessor T_1288 = regs[raddr1] + infer accessor T_1288 = regs[raddr1] node T_1289 = mux(T_1287, T_1288, UInt<1>(0)) rdata1 := T_1289 node T_1290 = eq(raddr2, UInt<1>(0)) node T_1291 = bit-not(T_1290) - accessor T_1292 = regs[raddr2] + infer accessor T_1292 = regs[raddr2] node T_1293 = mux(T_1291, T_1292, UInt<1>(0)) rdata2 := T_1293 node T_1294 = eq(waddr, UInt<1>(0)) node T_1295 = bit-not(T_1294) node T_1296 = bit-and(wen, T_1295) when T_1296 : - accessor T_1297 = regs[waddr] + infer accessor T_1297 = regs[waddr] T_1297 := wdata module ImmGenWire : output out : UInt<32> diff --git a/test/chisel3/Datapath.fir b/test/chisel3/Datapath.fir index 7d684395..c2752a37 100644 --- a/test/chisel3/Datapath.fir +++ b/test/chisel3/Datapath.fir @@ -100,19 +100,19 @@ circuit Datapath : cmem regs : UInt<32>[32] node T_495 = eq(raddr1, UInt<1>(0)) node T_496 = bit-not(T_495) - accessor T_497 = regs[raddr1] + infer accessor T_497 = regs[raddr1] node T_498 = mux(T_496, T_497, UInt<1>(0)) rdata1 := T_498 node T_499 = eq(raddr2, UInt<1>(0)) node T_500 = bit-not(T_499) - accessor T_501 = regs[raddr2] + infer accessor T_501 = regs[raddr2] node T_502 = mux(T_500, T_501, UInt<1>(0)) rdata2 := T_502 node T_503 = eq(waddr, UInt<1>(0)) node T_504 = bit-not(T_503) node T_505 = bit-and(wen, T_504) when T_505 : - accessor T_506 = regs[waddr] + infer accessor T_506 = regs[waddr] T_506 := wdata module ImmGenWire : output out : UInt<32> diff --git a/test/chisel3/Datapath_new.fir b/test/chisel3/Datapath_new.fir index 9f018394..2d3072b2 100644 --- a/test/chisel3/Datapath_new.fir +++ b/test/chisel3/Datapath_new.fir @@ -96,19 +96,19 @@ circuit Datapath : cmem regs : UInt<32>[32] node T_485 = eq(raddr1, UInt<1>(0)) node T_486 = bit-not(T_485) - accessor T_487 = regs[raddr1] + infer accessor T_487 = regs[raddr1] node T_488 = mux(T_486, T_487, UInt<1>(0)) rdata1 := T_488 node T_489 = eq(raddr2, UInt<1>(0)) node T_490 = bit-not(T_489) - accessor T_491 = regs[raddr2] + infer accessor T_491 = regs[raddr2] node T_492 = mux(T_490, T_491, UInt<1>(0)) rdata2 := T_492 node T_493 = eq(waddr, UInt<1>(0)) node T_494 = bit-not(T_493) node T_495 = bit-and(wen, T_494) when T_495 : - accessor T_496 = regs[waddr] + infer accessor T_496 = regs[waddr] T_496 := wdata module ImmGenWire : output out : UInt<32> diff --git a/test/chisel3/MemorySearch.fir b/test/chisel3/MemorySearch.fir index a0cc0b7d..fec082c0 100644 --- a/test/chisel3/MemorySearch.fir +++ b/test/chisel3/MemorySearch.fir @@ -18,7 +18,7 @@ circuit MemorySearch : elts[4] := UInt<4>(2) elts[5] := UInt<4>(5) elts[6] := UInt<4>(13) - accessor elt = elts[index] + infer accessor elt = elts[index] node T_35 = bit-not(en) node T_36 = eq(elt, target) node T_37 = eq(index, UInt<3>(7)) diff --git a/test/chisel3/Mul.fir b/test/chisel3/Mul.fir index c5dccb6f..b80b8a83 100644 --- a/test/chisel3/Mul.fir +++ b/test/chisel3/Mul.fir @@ -26,5 +26,5 @@ circuit Mul : tbl[15] := UInt<4>(9) node T_42 = shl(x, 2) node T_43 = bit-or(T_42, y) - accessor T_44 = tbl[T_43] + infer accessor T_44 = tbl[T_43] z := T_44 diff --git a/test/chisel3/Risc.fir b/test/chisel3/Risc.fir index 425f8a91..a1ba01b9 100644 --- a/test/chisel3/Risc.fir +++ b/test/chisel3/Risc.fir @@ -14,23 +14,23 @@ circuit Risc : cmem code : UInt<32>[256] reg pc : UInt<8> on-reset pc := UInt<8>(0) - accessor inst = code[pc] + infer accessor inst = code[pc] node op = bits(inst, 31, 24) node rci = bits(inst, 23, 16) node rai = bits(inst, 15, 8) node rbi = bits(inst, 7, 0) node T_51 = eq(rai, UInt<1>(0)) - accessor T_52 = file[rai] + infer accessor T_52 = file[rai] node ra = mux(T_51, UInt<1>(0), T_52) node T_53 = eq(rbi, UInt<1>(0)) - accessor T_54 = file[rbi] + infer accessor T_54 = file[rbi] node rb = mux(T_53, UInt<1>(0), T_54) wire rc : UInt<32> valid := UInt<1>(0) out := UInt<1>(0) rc := UInt<1>(0) when isWr : - accessor T_55 = code[wrAddr] + infer accessor T_55 = code[wrAddr] T_55 := wrData else : when boot : pc := UInt<1>(0) else : @@ -47,7 +47,7 @@ circuit Risc : node T_61 = eq(rci, UInt<8>(255)) when T_61 : valid := UInt<1>(1) else : - accessor T_62 = file[rci] + infer accessor T_62 = file[rci] T_62 := rc node T_63 = add-wrap(pc, UInt<1>(1)) pc := T_63 diff --git a/test/chisel3/Rom.fir b/test/chisel3/Rom.fir index 1c19d9b3..f91593a4 100644 --- a/test/chisel3/Rom.fir +++ b/test/chisel3/Rom.fir @@ -23,5 +23,5 @@ circuit Rom : r[13] := UInt<5>(26) r[14] := UInt<5>(28) r[15] := UInt<5>(30) - accessor T_39 = r[addr] + infer accessor T_39 = r[addr] out := T_39 diff --git a/test/chisel3/Stack.fir b/test/chisel3/Stack.fir index caa70da5..52c9b437 100644 --- a/test/chisel3/Stack.fir +++ b/test/chisel3/Stack.fir @@ -18,7 +18,7 @@ circuit Stack : node T_30 = lt(sp, UInt<5>(16)) node T_31 = bit-and(push, T_30) when T_31 : - accessor T_32 = stack_mem[sp] + infer accessor T_32 = stack_mem[sp] T_32 := dataIn node T_33 = add-wrap(sp, UInt<1>(1)) sp := T_33 @@ -31,6 +31,6 @@ circuit Stack : node T_37 = gt(sp, UInt<1>(0)) when T_37 : node T_38 = sub-wrap(sp, UInt<1>(1)) - accessor T_39 = stack_mem[T_38] + infer accessor T_39 = stack_mem[T_38] out := T_39 dataOut := out diff --git a/test/chisel3/Tbl.fir b/test/chisel3/Tbl.fir index e7397f61..013fd098 100644 --- a/test/chisel3/Tbl.fir +++ b/test/chisel3/Tbl.fir @@ -11,9 +11,9 @@ circuit Tbl : cmem m : UInt<10>[256] o := UInt<1>(0) when we : - accessor T_13 = m[i] + infer accessor T_13 = m[i] node T_14 = bits(d, 9, 0) T_13 := T_14 else : - accessor T_15 = m[i] + infer accessor T_15 = m[i] o := T_15 diff --git a/test/chisel3/Tile.fir b/test/chisel3/Tile.fir index b84684db..9efb079c 100644 --- a/test/chisel3/Tile.fir +++ b/test/chisel3/Tile.fir @@ -100,19 +100,19 @@ circuit Tile : cmem regs : UInt<32>[32] node T_1616 = eq(raddr1, UInt<1>(0)) node T_1617 = bit-not(T_1616) - accessor T_1618 = regs[raddr1] + infer accessor T_1618 = regs[raddr1] node T_1619 = mux(T_1617, T_1618, UInt<1>(0)) rdata1 := T_1619 node T_1620 = eq(raddr2, UInt<1>(0)) node T_1621 = bit-not(T_1620) - accessor T_1622 = regs[raddr2] + infer accessor T_1622 = regs[raddr2] node T_1623 = mux(T_1621, T_1622, UInt<1>(0)) rdata2 := T_1623 node T_1624 = eq(waddr, UInt<1>(0)) node T_1625 = bit-not(T_1624) node T_1626 = bit-and(wen, T_1625) when T_1626 : - accessor T_1627 = regs[waddr] + infer accessor T_1627 = regs[waddr] T_1627 := wdata module ImmGenWire : output out : UInt<32> @@ -1046,7 +1046,7 @@ circuit Tile : node T_2387 = bit-not(do_flow) node do_deq = bit-and(T_2386, T_2387) when do_enq : - accessor T_2388 = ram[T_2381] + infer accessor T_2388 = ram[T_2381] T_2388 := enq.bits node T_2389 = eq(T_2381, UInt<2>(3)) node T_2390 = bit-and(UInt<1>(0), T_2389) @@ -1069,7 +1069,7 @@ circuit Tile : node T_2402 = bit-and(UInt<1>(0), deq.ready) node T_2403 = bit-or(T_2401, T_2402) enq.ready := T_2403 - accessor T_2404 = ram[T_2382] + infer accessor T_2404 = ram[T_2382] wire T_2405 : {mask : UInt<4>, tag : UInt<5>, rw : UInt<1>, addr : UInt<32>} node T_2406 = mux(maybe_flow, enq.bits.mask, T_2404.mask) T_2405.mask := T_2406 @@ -1109,7 +1109,7 @@ circuit Tile : node T_2418 = bit-not(do_flow) node do_deq = bit-and(T_2417, T_2418) when do_enq : - accessor T_2419 = ram[T_2412] + infer accessor T_2419 = ram[T_2412] T_2419 := enq.bits node T_2420 = eq(T_2412, UInt<2>(3)) node T_2421 = bit-and(UInt<1>(0), T_2420) @@ -1132,7 +1132,7 @@ circuit Tile : node T_2433 = bit-and(UInt<1>(0), deq.ready) node T_2434 = bit-or(T_2432, T_2433) enq.ready := T_2434 - accessor T_2435 = ram[T_2413] + infer accessor T_2435 = ram[T_2413] wire T_2436 : {data : UInt<32>} node T_2437 = mux(maybe_flow, enq.bits.data, T_2435.data) T_2436.data := T_2437 diff --git a/test/errors/high-form/InvalidLOC.fir b/test/errors/high-form/InvalidLOC.fir index cbbb53a9..a4cc49ef 100644 --- a/test/errors/high-form/InvalidLOC.fir +++ b/test/errors/high-form/InvalidLOC.fir @@ -2,15 +2,11 @@ ; CHECK: Invalid connect to an expression that is not a reference or a WritePort. ; CHECK: Invalid connect to an expression that is not a reference or a WritePort. ; CHECK: Invalid connect to an expression that is not a reference or a WritePort. -; CHECK: Invalid connect to an expression that is not a reference or a WritePort. -; CHECK: Invalid connect to an expression that is not a reference or a WritePort. circuit Top : module Top : wire x : UInt add(x,x) := UInt(1) - Register(x,x) := UInt(1) - ReadPort(x,x,x) := UInt(1) UInt(1) := UInt(1) SInt(1) := UInt(1) diff --git a/test/features/BulkConnect.fir b/test/features/BulkConnect.fir index f78ba45b..f8840f46 100644 --- a/test/features/BulkConnect.fir +++ b/test/features/BulkConnect.fir @@ -3,7 +3,14 @@ circuit Top : module Top : wire a : { w : UInt<42>, x : UInt<10>, flip y : UInt<42>, z : SInt<42>} + a.w := UInt(1) + a.y := UInt(1) + a.z := SInt(1) wire b : { w : UInt<42>, x : UInt<20>, y : UInt<42>, z : UInt<42>} + b.w := UInt(1) + b.x := UInt(1) + b.y := UInt(1) + b.z := UInt(1) a <> b ; CHECK: a$w := b$w ; CHECK: a$x := b$x @@ -13,7 +20,15 @@ circuit Top : wire c : { x : { y : UInt<1>, z : UInt<1>}}[4] + c[0].x.z := UInt(1) + c[1].x.z := UInt(1) + c[2].x.y := UInt(1) + c[2].x.z := UInt(1) + c[3].x.y := UInt(1) + c[3].x.z := UInt(1) wire d : { x : { y : UInt<1>}}[2] + d[0].x.y := UInt(1) + d[1].x.y := UInt(1) c <> d ; CHECK: c$0$x$y := d$0$x$y ; CHECK: c$1$x$y := d$1$x$y diff --git a/test/features/SeqMem.fir b/test/features/SeqMem.fir index 998df8c9..4b346ea9 100644 --- a/test/features/SeqMem.fir +++ b/test/features/SeqMem.fir @@ -3,20 +3,21 @@ circuit Top : module Top : wire i : UInt<5> + i := UInt(1) wire i0 : UInt<5> wire j : UInt<128> i0 := UInt(10) cmem m-com : UInt<128>[32] - accessor r-com = m-com[i] - accessor w-com = m-com[i] + infer accessor r-com = m-com[i] + infer accessor w-com = m-com[i] j := r-com w-com := j smem m-seq : UInt<128>[32] - accessor r-seq = m-seq[i] - accessor w-seq = m-seq[i] + infer accessor r-seq = m-seq[i] + infer accessor w-seq = m-seq[i] j := r-seq w-seq := j diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir index 892103d2..6309b46f 100644 --- a/test/passes/infer-types/bundle.fir +++ b/test/passes/infer-types/bundle.fir @@ -4,9 +4,21 @@ circuit top : module top : wire z : { x : UInt, flip y: SInt} + z.x := UInt(1) + z.y := SInt(1) node x = z.x ;CHECK: node x = z@, flip y : SInt@}>.x@ node y = z.y ;CHECK: node y = z@, flip y : SInt@}>.y@ wire a : UInt<3>[10] ;CHECK: wire a : UInt<3>[10]@@[10]@> + a[0] := UInt(1) + a[1] := UInt(1) + a[2] := UInt(1) + a[3] := UInt(1) + a[4] := UInt(1) + a[5] := UInt(1) + a[6] := UInt(1) + a[7] := UInt(1) + a[8] := UInt(1) + a[9] := UInt(1) node b = a[2] ;CHECK: node b = a@[10]@>[2]@ read accessor c = a[UInt(3)] ;CHECK: read accessor c = a@[10]@>[UInt(3)] ; CHECK: Finished Infer Types diff --git a/test/passes/infer-widths/dsh.fir b/test/passes/infer-widths/dsh.fir index 6b683e56..08396978 100644 --- a/test/passes/infer-widths/dsh.fir +++ b/test/passes/infer-widths/dsh.fir @@ -11,6 +11,9 @@ circuit top : wire b : SInt wire c : UInt wire d : SInt + x := UInt(1) + y := UInt(1) + z := SInt(1) a := dshl(x,y) b := dshl(z,y) diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir index 590515e7..6a50ae77 100644 --- a/test/passes/infer-widths/simple.fir +++ b/test/passes/infer-widths/simple.fir @@ -4,12 +4,16 @@ circuit top : module top : wire e : UInt<30> + e := UInt(1) reg y : UInt y := e wire a : UInt<20> + a := UInt(1) wire b : UInt<10> + b := UInt(1) wire c : UInt + c := UInt(1) wire z : UInt z := mux(c,a,b) diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir index 1953e39b..59352162 100644 --- a/test/passes/jacktest/MemorySearch.fir +++ b/test/passes/jacktest/MemorySearch.fir @@ -17,7 +17,7 @@ circuit MemorySearch : elts[4] := UInt<4>(2) elts[5] := UInt<4>(5) elts[6] := UInt<4>(13) - accessor elt = elts[index] + infer accessor elt = elts[index] node T_35 = bit-not(en) node T_36 = eq(elt, target) node T_37 = eq(index, UInt<3>(7)) diff --git a/test/passes/jacktest/Mul.fir b/test/passes/jacktest/Mul.fir index 58515110..14db8769 100644 --- a/test/passes/jacktest/Mul.fir +++ b/test/passes/jacktest/Mul.fir @@ -25,5 +25,5 @@ circuit Mul : tbl[15] := UInt<4>(9) node T_42 = shl(x, 2) node T_43 = bit-or(T_42, y) - accessor T_44 = tbl[T_43] + infer accessor T_44 = tbl[T_43] z := T_44 diff --git a/test/passes/jacktest/Rom.fir b/test/passes/jacktest/Rom.fir index ee417771..3c70c670 100644 --- a/test/passes/jacktest/Rom.fir +++ b/test/passes/jacktest/Rom.fir @@ -22,5 +22,5 @@ circuit Rom : r[13] := UInt<5>(26) r[14] := UInt<5>(28) r[15] := UInt<5>(30) - accessor T_39 = r[addr] + infer accessor T_39 = r[addr] out := T_39 diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir index 43f61827..4bce2bd4 100644 --- a/test/passes/jacktest/Stack.fir +++ b/test/passes/jacktest/Stack.fir @@ -17,7 +17,7 @@ circuit Stack : node T_30 = lt(sp, UInt<5>(16)) node T_31 = bit-and(push, T_30) when T_31 : - accessor T_32 = stack_mem[sp] + infer accessor T_32 = stack_mem[sp] T_32 := dataIn node T_33 = add-wrap(sp, UInt<1>(1)) sp := T_33 @@ -30,6 +30,6 @@ circuit Stack : node T_37 = gt(sp, UInt<1>(0)) when T_37 : node T_38 = sub-wrap(sp, UInt<1>(1)) - accessor T_39 = stack_mem[T_38] + infer accessor T_39 = stack_mem[T_38] out := T_39 dataOut := out diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir index 4e0e954c..f315aaa9 100644 --- a/test/passes/jacktest/Tbl.fir +++ b/test/passes/jacktest/Tbl.fir @@ -10,9 +10,9 @@ circuit Tbl : cmem m : UInt<10>[256] o := UInt<1>(0) when we : - accessor T_13 = m[i] + infer accessor T_13 = m[i] node T_14 = bits(d, 9, 0) T_13 := T_14 else : - accessor T_15 = m[i] + infer accessor T_15 = m[i] o := T_15 diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir index 4d02bcf7..21030448 100644 --- a/test/passes/jacktest/risc.fir +++ b/test/passes/jacktest/risc.fir @@ -13,23 +13,23 @@ circuit Risc : cmem code : UInt<32>[256] reg pc : UInt<8> on-reset pc := UInt<8>(0) - accessor inst = code[pc] + infer accessor inst = code[pc] node op = bits(inst, 31, 24) node rci = bits(inst, 23, 16) node rai = bits(inst, 15, 8) node rbi = bits(inst, 7, 0) node T_51 = eq(rai, UInt<1>(0)) - accessor T_52 = file[rai] + infer accessor T_52 = file[rai] node ra = mux(T_51, UInt<1>(0), T_52) node T_53 = eq(rbi, UInt<1>(0)) - accessor T_54 = file[rbi] + infer accessor T_54 = file[rbi] node rb = mux(T_53, UInt<1>(0), T_54) wire rc : UInt<32> valid := UInt<1>(0) out := UInt<1>(0) rc := UInt<1>(0) when isWr : - accessor T_55 = code[wrAddr] + infer accessor T_55 = code[wrAddr] T_55 := wrData else : when boot : pc := UInt<1>(0) else : @@ -46,7 +46,7 @@ circuit Risc : node T_61 = eq(rci, UInt<8>(255)) when T_61 : valid := UInt<1>(1) else : - accessor T_62 = file[rci] + infer accessor T_62 = file[rci] T_62 := rc node T_63 = add-wrap(pc, UInt<1>(1)) pc := T_63 diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir index 8fe1bc52..cede6f43 100644 --- a/test/passes/lower-to-ground/accessor.fir +++ b/test/passes/lower-to-ground/accessor.fir @@ -12,21 +12,21 @@ circuit top : ; CHECK: wire a$2 : UInt<32> ; CHECK: wire a$3 : UInt<32> - accessor b = a[i] + infer accessor b = a[i] ; CHECK: wire b : UInt<32> ; CHECK: b := (a$0 a$1 a$2 a$3)[i] j := b - accessor c = a[i] + infer accessor c = a[i] ; CHECK: wire c : UInt<32> ; CHECK: (a$0 a$1 a$2 a$3)[i] := c c := j cmem p : UInt<32>[4] - accessor t = p[i] + infer accessor t = p[i] ; CHECK: accessor t = p[i] j := t - accessor r = p[i] + infer accessor r = p[i] ; CHECK: accessor r = p[i] r := j diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir index 0b9d9799..e71e9104 100644 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ b/test/passes/lower-to-ground/bundle-vecs.fir @@ -12,14 +12,14 @@ circuit top : ; CHECK: wire a$1$x : UInt<32> ; CHECK: wire a$1$y : UInt<32> - accessor b = a[i] + infer accessor b = a[i] ; CHECK: wire b$x : UInt<32> ; CHECK: wire b$y : UInt<32> ; CHECK: b$x := (a$0$x a$1$x)[i] ; CHECK: (a$0$y a$1$y)[i] := b$y j := b - accessor c = a[i] + infer accessor c = a[i] ; CHECK: wire c$x : UInt<32> ; CHECK: wire c$y : UInt<32> ; CHECK: (a$0$x a$1$x)[i] := c$x diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir index c39850f4..a2eb1215 100644 --- a/test/passes/lower-to-ground/nested-vec.fir +++ b/test/passes/lower-to-ground/nested-vec.fir @@ -13,7 +13,7 @@ circuit top : ; CHECK: wire a$1$x : UInt<32> ; CHECK: wire a$1$y : UInt<32> - accessor b = a[i] + infer accessor b = a[i] ; CHECK: wire b$x : UInt<32> ; CHECK: wire b$y : UInt<32> ; CHECK: b$x := (a$0$x a$1$x)[i] @@ -24,7 +24,7 @@ circuit top : ; CHECK: cmem m$x : UInt<32>[2] ; CHECK: cmem m$y : UInt<32>[2] - accessor c = m[i] ; MALE + infer accessor c = m[i] ; MALE ; CHECK: accessor c$x = m$x[i] ; CHECK: accessor c$y = m$y[i] diff --git a/test/passes/lower-to-ground/test.fir b/test/passes/lower-to-ground/test.fir index 7fcf0013..7e123fc3 100644 --- a/test/passes/lower-to-ground/test.fir +++ b/test/passes/lower-to-ground/test.fir @@ -4,10 +4,13 @@ circuit Top : module Queue : output out : {valid : UInt<1>, flip ready : UInt<1>} + out.valid := UInt(1) module Top : output this : {out : {valid : UInt<1>, flip ready : UInt<1>}} inst queue of Queue this.out := queue.out wire w : { x : UInt<5>, flip y : UInt<5>} + w.x := UInt(1) wire a : UInt<5> + a := UInt(1) w.y := a diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir index 41aea1f4..8a86868b 100644 --- a/test/passes/resolve-genders/accessor.fir +++ b/test/passes/resolve-genders/accessor.fir @@ -4,16 +4,31 @@ circuit top : module top : wire m : UInt<32>[2][2][2] + m[0][0][0] := UInt(1) + m[1][0][0] := UInt(1) + m[0][1][0] := UInt(1) + m[1][1][0] := UInt(1) + m[0][0][1] := UInt(1) + m[1][0][1] := UInt(1) + m[0][1][1] := UInt(1) + m[1][1][1] := UInt(1) wire i : UInt - accessor a = m[i] ;CHECK: accessor a = m@[i@]@ - accessor b = a[i] ;CHECK: accessor b = a@[i@]@ - accessor c = b[i] ;CHECK: accessor c = b@[i@]@ + i := UInt(1) + infer accessor a = m[i] ;CHECK: accessor a = m@[i@]@ + infer accessor b = a[i] ;CHECK: accessor b = a@[i@]@ + infer accessor c = b[i] ;CHECK: accessor c = b@[i@]@ wire j : UInt j := c - accessor x = m[i] ;CHECK: accessor x = m@[i@]@ - accessor y = x[i] ;CHECK: accessor y = x@[i@]@ - accessor z = y[i] ;CHECK: accessor z = y@[i@]@ + infer accessor x = m[i] ;CHECK: accessor x = m@[i@]@ + x[0][0] := UInt(1) + x[1][0] := UInt(1) + x[0][1] := UInt(1) + x[1][1] := UInt(1) + infer accessor y = x[i] ;CHECK: accessor y = x@[i@]@ + y[0] := UInt(1) + y[1] := UInt(1) + infer accessor z = y[i] ;CHECK: accessor z = y@[i@]@ z := j ; CHECK: Finished Resolve Genders diff --git a/test/riscv-mini/Core.fir b/test/riscv-mini/Core.fir index aea05940..439cf1db 100644 --- a/test/riscv-mini/Core.fir +++ b/test/riscv-mini/Core.fir @@ -100,19 +100,19 @@ circuit Core : cmem regs : UInt<32>[32] node T_1286 = eq(raddr1, UInt<1>(0)) node T_1287 = bit-not(T_1286) - accessor T_1288 = regs[raddr1] + infer accessor T_1288 = regs[raddr1] node T_1289 = mux(T_1287, T_1288, UInt<1>(0)) rdata1 := T_1289 node T_1290 = eq(raddr2, UInt<1>(0)) node T_1291 = bit-not(T_1290) - accessor T_1292 = regs[raddr2] + infer accessor T_1292 = regs[raddr2] node T_1293 = mux(T_1291, T_1292, UInt<1>(0)) rdata2 := T_1293 node T_1294 = eq(waddr, UInt<1>(0)) node T_1295 = bit-not(T_1294) node T_1296 = bit-and(wen, T_1295) when T_1296 : - accessor T_1297 = regs[waddr] + infer accessor T_1297 = regs[waddr] T_1297 := wdata module ImmGenWire : output out : UInt<32> -- cgit v1.2.3 From 521bac8227030f12090e45f4c1a0e02bf59884ec Mon Sep 17 00:00:00 2001 From: azidar Date: Tue, 7 Jul 2015 13:25:33 -0700 Subject: Passes riscv-mini tests --- src/main/stanza/passes.stanza | 6 +++++- src/main/stanza/verilog.stanza | 18 ++++++++++++++---- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index b500f991..ed3f0079 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -1908,7 +1908,7 @@ defn split-exp (c:Circuit) : (s:Begin) : do(f,s) (s:Conditionally) : - add(v,map(split-exp-e{_,false,info(s)},s)) + add(v,map(split-exp-e{_,full-name(loc(conseq(s) as Connect)),info(s)},s)) do(f,s) (s:Connect) : match(loc(s)) : @@ -2089,6 +2089,10 @@ defn pad-widths-s (s:Stmt) -> Stmt : val i = int-width!(type(value(s))) val exp* = pad-widths-e(i,value(s)) DefNode(info(s),name(s),exp*) + (s:Conditionally) : + val i = int-width!(type(pred(s))) + val pred* = pad-widths-e(i,pred(s)) + Conditionally(info(s),pred*,conseq(s),alt(s)) (s) : s public defn pad-widths (c:Circuit) -> Circuit : diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index 0367c333..1904f92f 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -140,13 +140,16 @@ defn get-name (e:Expression) -> Symbol : (e) : error("Shouldn't be here") defn emit-module (m:InModule) : + val vdecs = Vector>() ; all declarations val decs = HashTable(symbol-hash) ; all declarations val cons = HashTable(symbol-hash) ; all connections val ens = HashTable(symbol-hash) ; all enables defn build-table (m:InModule) : defn build-table (s:Stmt) -> Stmt : match(map(build-table,map(remove-subfield,s))) : - (s:DefWire|DefRegister|DefAccessor|DefMemory|DefNode|DefInstance) : decs[name(s)] = s + (s:DefWire|DefRegister|DefAccessor|DefMemory|DefNode|DefInstance) : + add(vdecs,name(s) => s) + decs[name(s)] = s (s:Conditionally) : val n = get-name(loc(conseq(s) as Connect)) ens[n] = pred(s) @@ -169,7 +172,7 @@ defn emit-module (m:InModule) : val sh = get-sym-hash(m) - for x in decs do : + for x in vdecs do : val sym = key(x) match(value(x)) : (s:DefWire) : @@ -198,6 +201,8 @@ defn emit-module (m:InModule) : val n* = to-symbol $ string-join $ [sym "_" name(f)] add(wires,["wire " get-width(type(f)) " " n* ";"]) add(inst-ports[sym], ["." name(f) "( " n* " )"]) + if flip(f) == REVERSE : + add(assigns,["assign " n* " = " emit(cons[n*]) ";"]) (s:DefAccessor) : switch {_ == acc-dir(s)} : READ : @@ -210,9 +215,11 @@ defn emit-module (m:InModule) : add(updates,[name(index*) " <= " emit(index(s)) ";"]) ; emit read accessor + add(wires,["wire " get-width(type(type(source(s)) as VectorType)) " " sym ";"]) add(assigns,["assign " sym " = " emit(source(s)) "[" emit(index*) "];"]) else : ; emit read accessor + add(wires,["wire " get-width(type(type(source(s)) as VectorType)) " " sym ";"]) add(assigns,["assign " sym " = " emit(source(s)) "[" emit(index(s)) "];"]) WRITE : if key?(ens,sym) : @@ -231,8 +238,11 @@ defn emit-module (m:InModule) : if length(ports(m)) - 1 == i : end = "\n);\n" switch {_ == direction(p)} : - INPUT : print-all([port-indent "input " get-width(type(p)) " " name(p) end]) - OUTPUT : print-all([port-indent "output " get-width(type(p)) " " name(p) end]) + INPUT : + print-all([port-indent "input " get-width(type(p)) " " name(p) end]) + OUTPUT : + print-all([port-indent "output " get-width(type(p)) " " name(p) end]) + add(assigns,["assign " name(p) " = " emit(cons[name(p)]) ";"]) for w in wires do : print(" ") -- cgit v1.2.3 From a62fea153cf01e9f7517c6889198d02e5fbbb266 Mon Sep 17 00:00:00 2001 From: azidar Date: Tue, 7 Jul 2015 14:56:47 -0700 Subject: Updated flo backend --- TODO | 6 ++- src/main/stanza/compilers.stanza | 60 ++++++++++++++-------------- src/main/stanza/firrtl-test-main.stanza | 5 +-- src/main/stanza/flo.stanza | 71 +++++++++++++++++++++------------ src/main/stanza/passes.stanza | 1 + 5 files changed, 83 insertions(+), 60 deletions(-) diff --git a/TODO b/TODO index c881509d..edc3fe17 100644 --- a/TODO +++ b/TODO @@ -6,13 +6,15 @@ Add/Update Unit Tests for each pass Check after each pass write test that checks instance types are correctly lowered -error on uninitialized wires +fix expand-whens to have correct semantics ensure module names are unique add check that limits size of width of dshl add efficient prefix checker -Change to new low firrtl +update high/low firrtl checks add clock type add clock, reset to reg, mem etc +need a multi-clock domain example +need an annotation example change parser to accept subword, but error move width inference earlier diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index a3b04a94..2f6329dc 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -3,40 +3,40 @@ defpackage firrtl/compiler : import verse import firrtl/passes import firrtl/errors -; import firrtl/flo + import firrtl/flo import firrtl/verilog import firrtl/ir2 import firrtl/ir-utils -;public defstruct StandardFlo <: Compiler : -; file: String with: (as-method => true) -;public defmethod passes (c:StandardFlo) -> List : -; to-list $ [ -; CheckHighForm(expand-delin) -; ;; TempElimination() -; ToWorkingIR() -; MakeExplicitReset() -; ResolveKinds() -; CheckKinds() -; InferTypes() -; CheckTypes() -; ResolveGenders() -; CheckGenders() -; ExpandAccessors() -; LowerToGround() -; ExpandIndexedConnects() -; ExpandWhens() -; InferWidths() -; Pad() -; Inline() -; SplitExp() -; ToRealIR() -; SpecialRename(`#,`_) -; SpecialRename(`$,`::) -; CheckHighForm(`::) -; CheckLowForm() -; Flo(file(c)) -; ] +public defstruct StandardFlo <: Compiler : + file: String with: (as-method => true) +public defmethod passes (c:StandardFlo) -> List : + to-list $ [ + CheckHighForm(expand-delin) + ;; TempElimination() + ToWorkingIR() + MakeExplicitReset() + ResolveKinds() + CheckKinds() + InferTypes() + CheckTypes() + ResolveGenders() + CheckGenders() + ExpandAccessors() + LowerToGround() + ExpandIndexedConnects() + ExpandWhens() + InferWidths() + Pad() + Inline() + SplitExp() + ToRealIR() + SpecialRename(`#,`_) + SpecialRename(`$,`::) + CheckHighForm(`::) + CheckLowForm() + Flo(file(c)) + ] public defstruct StandardVerilog <: Compiler : file: String with: (as-method => true) diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza index 374fe438..beb288b1 100644 --- a/src/main/stanza/firrtl-test-main.stanza +++ b/src/main/stanza/firrtl-test-main.stanza @@ -11,7 +11,7 @@ #include("primop.stanza") #include("errors.stanza") #include("compilers.stanza") -;#include("flo.stanza") +#include("flo.stanza") #include("verilog.stanza") ;Custom Packages @@ -80,8 +80,7 @@ defn main () : run-passes(c,get-passes(to-list(pass-names))) else : switch {_ == compiler} : - ;"flo" : run-passes(c,StandardFlo(output as String)) - "flo" : run-passes(c,StandardVerilog(output as String)) + "flo" : run-passes(c,StandardFlo(output as String)) "verilog" : run-passes(c,StandardVerilog(output as String)) "verilute" : run-passes(c,InstrumentedVerilog(output as String,to-list $ pass-args)) else : error("Invalid compiler flag") diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza index cf15638d..9f4cdc8c 100644 --- a/src/main/stanza/flo.stanza +++ b/src/main/stanza/flo.stanza @@ -11,8 +11,16 @@ public defstruct Flo <: Pass : file : String public defmethod pass (b:Flo) -> (Circuit -> Circuit) : emit-flo{file(b),_} public defmethod name (b:Flo) -> String : "To Flo" + +definterface FloKind +defstruct FRegKind <: FloKind +defstruct FWritePortKind <: FloKind : + mem: Expression + index: Expression +defstruct FOutputPortKind <: FloKind defn is-sint? (arg:Expression) -> True|False : type(arg) typeof SIntType +defn type (s:DefAccessor) -> Type : type(type(source(s)) as VectorType) defn flo-op-name (op:PrimOp, args:List) -> String : switch {op == _ } : @@ -94,12 +102,6 @@ defn emit! (e:Expression,top:Symbol) : (e:SIntValue) : emit-all([value(e) "'" sane-width(width(e))], top) (e:Subfield) : emit-all([exp(e) "/" name(e)], top) (e:Index) : emit-all([exp(e) "/" value(e)], top) - ;(e:Pad) : - ;emit-all(["rsh'" prim-width(type(e)) " " value(e) " 0"], top) - (e:Register) : - emit-all(["reg'" prim-width(type(e)) " " enable(e) " " value(e)], top) - (e:ReadPort) : - emit-all(["rd'" prim-width(type(e)) " " "1" " " mem(e) " " index(e)], top) ;; enable(e) (e:DoPrim) : if cmp-op?(op(e)) : emit-all([flo-op-name(op(e), args(e)) "'" prim-width(type(args(e)[0]))], top) @@ -137,41 +139,60 @@ defn maybe-mov (e:Expression) -> String : (e) : false if need-mov?: "mov " else: "" -defn emit-s (s:Stmt, v:List, top:Symbol,sh:HashTable) : +defn emit-s (s:Stmt, flokinds:HashTable, top:Symbol,sh:HashTable) : + defn emit-connect (s:Connect, en:Expression) : + match(loc(s)) : + (r:Ref) : + val n = name(r) + if key?(flokinds,n) : + match(flokinds[n]) : + (k:FRegKind) : + emit-all(["reg'" prim-width(type(r)) " " en " " exp(s)], top) + (k:FWritePortKind) : + emit-all([top "::" n " = wr'" prim-width(type(r)) " " en " " mem(k) " " index(k) " " exp(s) "\n"], top) + (k:FOutputPortKind) : + emit-all([top "::" n " = out'" prim-width(type(r)) " " exp(s) "\n"], top) + (k) : error("Shouldn't be here") + else : + emit-all([top "::" n " = " maybe-mov(exp(s)) exp(s) "\n"], top) + (o) : + println-all(["CONNEcT LOC " loc(s)]) + error("Unknown Connect") match(s) : (s:DefWire) : "" (s:DefInstance) : error("Shouldn't be here") + (e:DefAccessor) : + if acc-dir == READ : + emit-all(["rd'" prim-width(type(e)) " " "1" " " source(e) " " index(e)], top) (s:DefMemory) : val vtype = type(s) as VectorType emit-all([top "::" name(s) " = mem'" prim-width(type(vtype)) " " size(vtype) "\n"], top) (s:DefNode) : emit-all([top "::" name(s) " = " maybe-mov(value(s)) value(s) "\n"], top) - (s:Begin) : do(emit-s{_, v, top,sh}, body(s)) - (s:Connect) : - match(loc(s)) : - (r:Ref) : - val n = name(r) - if contains?(v,n) : - emit-all([top "::" n " = out'" prim-width(type(r)) " " exp(s) "\n"], top) - else : - emit-all([top "::" n " = " maybe-mov(exp(s)) exp(s) "\n"], top) - (w:WritePort) : - val n = firrtl-gensym(`F,sh) - emit-all([top "::" n " = wr'" prim-width(type(w)) " " enable(w) " " mem(w) " " index(w) " " exp(s) "\n"], top) - (o) : - println-all(["CONNEcT LOC " loc(s)]) - error("Unknown Connect") + (s:Begin) : do(emit-s{_, flokinds, top,sh}, body(s)) + (s:Connect) : emit-connect(s,UIntValue(to-long(1),IntWidth(1))) + (s:Conditionally) : emit-connect(conseq(s) as Connect,pred(s)) (s) : s defn emit-module (m:InModule,sh:HashTable) : - val v = Vector() + val flokinds = HashTable(symbol-hash) + defn build-table (s:Stmt) -> False : + do(build-table,s) + match(s) : + (s:DefRegister) : flokinds[name(s)] = FRegKind() + (s:DefAccessor) : + switch {_ == acc-dir(s)} : + WRITE : flokinds[name(s)] = FWritePortKind(source(s),index(s)) + else : false + (s) : false + for port in ports(m) do : if name(port) ==`reset : emit-all([name(m) "::" name(port) " = rst'1\n"], name(m)) else : switch {_ == direction(port)} : INPUT : print-all([name(m) "::" name(port) " = " "in'" prim-width(type(port)) "\n"]) - OUTPUT : add(v,name(port)) - emit-s(body(m), to-list(v), name(m),sh) + OUTPUT : flokinds[name(port)] = FOutputPortKind() + emit-s(body(m), flokinds, name(m),sh) public defn emit-flo (file:String, c:Circuit) : with-output-file{file, _} $ fn () : diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index ed3f0079..43cc06a4 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -1867,6 +1867,7 @@ defn inline-instances (c:Circuit) : defn rename-s (s:Stmt,n:Symbol) -> Stmt : map{rename-e{_,n},_} $ match(map(rename-s{_,n},s)) : (s:DefWire) : DefWire(info(s),rename(name(s),n),type(s)) + (s:DefRegister) : DefRegister(info(s),rename(name(s),n),type(s)) (s:DefInstance) : error("Shouldn't be here") (s:DefMemory) : DefMemory(info(s),rename(name(s),n),type(s),seq?(s)) (s:DefNode) : DefNode(info(s),rename(name(s),n),value(s)) -- cgit v1.2.3 From 1ed6d4a47c92072b12db4b784f239071e4928049 Mon Sep 17 00:00:00 2001 From: azidar Date: Fri, 10 Jul 2015 13:25:21 -0700 Subject: Added clock support --- TODO | 24 +- notes/frontend-notes.04.16.15.txt | 11 + src/main/stanza/compilers.stanza | 4 +- src/main/stanza/custom-compiler.stanza | 2 +- src/main/stanza/custom-passes.stanza | 2 +- src/main/stanza/errors.stanza | 31 +- src/main/stanza/firrtl-ir.stanza | 4 + src/main/stanza/flo.stanza | 1 + src/main/stanza/ir-parser.stanza | 47 +- src/main/stanza/ir-utils.stanza | 40 +- src/main/stanza/passes.stanza | 157 +-- src/main/stanza/verilog.stanza | 79 +- test/chisel3/ALUTop.fir | 28 +- test/chisel3/Control.fir | 108 ++- test/chisel3/Core.fir | 1274 +++++++++++++------------ test/chisel3/Datapath.fir | 174 ++-- test/features/SeqMem.fir | 5 +- test/passes/expand-accessors/accessor-mem.fir | 3 +- 18 files changed, 1024 insertions(+), 970 deletions(-) diff --git a/TODO b/TODO index edc3fe17..2ba5f2b4 100644 --- a/TODO +++ b/TODO @@ -3,22 +3,22 @@ ================================================ ======== Current Tasks ======== -Add/Update Unit Tests for each pass - Check after each pass - write test that checks instance types are correctly lowered +change parser to accept subword, but error +--Merge with master + +Tests: + Lowering for instance types with bundle ports + More prefix tests + Expand-when semantics + Ensure module names are unique + Large width of dshl + fix expand-whens to have correct semantics -ensure module names are unique -add check that limits size of width of dshl -add efficient prefix checker update high/low firrtl checks -add clock type -add clock, reset to reg, mem etc +add efficient prefix checker need a multi-clock domain example need an annotation example -change parser to accept subword, but error - -move width inference earlier - Required for subword assignment, consistent vec width inference, and supporting the new constructs of tobits/frombits +move width inference earlier (required for subword assignment, consistent vec width inference, and supporting the new constructs of tobits/frombits) Temp elimination needs to count # uses Declared references needs to understand scope <= check in high form check Check for recursively defined instances diff --git a/notes/frontend-notes.04.16.15.txt b/notes/frontend-notes.04.16.15.txt index 23da75d9..fb7c1af9 100644 --- a/notes/frontend-notes.04.16.15.txt +++ b/notes/frontend-notes.04.16.15.txt @@ -1,6 +1,17 @@ ======= Fixes to Jonathan's Front-end ====== == TODO == +convert -> cvt +as-UInt -> asUInt +as-SInt -> asSInt +add-wrap -> addw +sub-wrap -> subw +bit-and -> and +bit-or -> or +bit-xor -> xor + + + Fixing chisel3 front-end bugs: LFSR16: "concat" -> "cat" MemorySearch: name collision with node done and output done diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index 2f6329dc..c458f1e1 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -15,7 +15,7 @@ public defmethod passes (c:StandardFlo) -> List : CheckHighForm(expand-delin) ;; TempElimination() ToWorkingIR() - MakeExplicitReset() + ;; MakeExplicitReset() ResolveKinds() CheckKinds() InferTypes() @@ -45,7 +45,7 @@ public defmethod passes (c:StandardVerilog) -> List : CheckHighForm(expand-delin) TempElimination() ToWorkingIR() - MakeExplicitReset() + ;; MakeExplicitReset() ResolveKinds() CheckKinds() InferTypes() diff --git a/src/main/stanza/custom-compiler.stanza b/src/main/stanza/custom-compiler.stanza index 773b63ca..91732f22 100644 --- a/src/main/stanza/custom-compiler.stanza +++ b/src/main/stanza/custom-compiler.stanza @@ -17,7 +17,7 @@ public defmethod passes (c:InstrumentedVerilog) -> List : CheckHighForm(expand-delin) TempElimination() ToWorkingIR() - MakeExplicitReset() + ;; MakeExplicitReset() ResolveKinds() CheckKinds() InferTypes() diff --git a/src/main/stanza/custom-passes.stanza b/src/main/stanza/custom-passes.stanza index 6c1e58f6..4904d6d1 100644 --- a/src/main/stanza/custom-passes.stanza +++ b/src/main/stanza/custom-passes.stanza @@ -70,7 +70,7 @@ defn when-coverage (port-name:Symbol, reg-name:Symbol, instrument?:HashTable ; * Unique names per module ; * No name can be a prefix of any other name. ; * all references are declared @@ -88,9 +86,9 @@ defn ModuleNotDefined (info:FileInfo, name:Symbol) : PassException $ string-join $ [info ": Module " name " is not defined."] -defn WrongReset (info:FileInfo, name:Symbol) : - PassException $ string-join $ - [info ": Module " name " has a reset that is not of type UInt<1>."] +;defn WrongReset (info:FileInfo, name:Symbol) : +; PassException $ string-join $ +; [info ": Module " name " has a reset that is not of type UInt<1>."] defn IncorrectNumArgs (info:FileInfo, op:Symbol, n:Int) : PassException $ string-join $ @@ -324,15 +322,15 @@ public defn check-high-form (c:Circuit,sym:Symbol) -> Circuit : names[name(m)] = true for p in ports(m) do : names[name(p)] = true - if name(p) == `reset : - if direction(p) == OUTPUT : - add(errors,WrongReset(info!(m),name(m))) - else : - if type(p) typeof UIntType : - if width(type(p) as UIntType) != IntWidth(1) : - add(errors,WrongReset(info!(m),name(m))) - else : - add(errors,WrongReset(info!(m),name(m))) + ;if name(p) == `reset : + ; if direction(p) == OUTPUT : + ; add(errors,WrongReset(info!(m),name(m))) + ; else : + ; if type(p) typeof UIntType : + ; if width(type(p) as UIntType) != IntWidth(1) : + ; add(errors,WrongReset(info!(m),name(m))) + ; else : + ; add(errors,WrongReset(info!(m),name(m))) map(check-high-form-t{info(p),_},type(p)) map(check-high-form-w{info(p),_},type(p)) @@ -436,6 +434,8 @@ public defn check-kinds (c:Circuit) -> Circuit : ; o node's value cannot be a bundle with a flip in it ; o := has same types ; o 2nd arg in dshr/l must be UInt, in general do primops +; o clock must be ClockType +; o reset must be UInt<1> public defstruct CheckTypes <: Pass public defmethod pass (b:CheckTypes) -> (Circuit -> Circuit) : check-types @@ -499,6 +499,7 @@ defn NodeWithFlips (info:FileInfo) : ;---------------- Helper Functions -------------- defmethod equal? (t1:Type,t2:Type) -> True|False : match(t1,t2) : + (t1:ClockType,t2:ClockType) : true (t1:UIntType,t2:UIntType) : true (t1:SIntType,t2:SIntType) : true (t1:BundleType,t2:BundleType) : @@ -648,7 +649,6 @@ defn gender (s:DefAccessor) -> Gender : INFER : UNKNOWN-GENDER RDWR : BI-GENDER - ;----------------- Check Genders Pass --------------------- public defn check-genders (c:Circuit) -> Circuit : @@ -728,6 +728,7 @@ public defn check-genders (c:Circuit) -> Circuit : ; o no accessors ; o only vecs are for memories ; o no bundles (future, will have them for mems) +; o only predicated conditional connects public defstruct CheckLowForm <: Pass public defmethod pass (b:CheckLowForm) -> (Circuit -> Circuit) : check-low-form diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza index b698bae2..b9d2cee4 100644 --- a/src/main/stanza/firrtl-ir.stanza +++ b/src/main/stanza/firrtl-ir.stanza @@ -101,6 +101,8 @@ public defstruct DefRegister <: Stmt : info: FileInfo with: (as-method => true) name: Symbol type: Type + clock: Expression + reset: Expression public defstruct DefInstance <: Stmt : ;LOW info: FileInfo with: (as-method => true) name: Symbol @@ -110,6 +112,7 @@ public defstruct DefMemory <: Stmt : ;LOW name: Symbol type: VectorType seq?: True|False + clock: Expression public defstruct DefNode <: Stmt : ;LOW info: FileInfo with: (as-method => true) name: Symbol @@ -151,6 +154,7 @@ public defstruct BundleType <: Type : public defstruct VectorType <: Type : type: Type size: Int +public defstruct ClockType <: Type public defstruct UnknownType <: Type public defstruct Field : diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza index 9f4cdc8c..d8fe705f 100644 --- a/src/main/stanza/flo.stanza +++ b/src/main/stanza/flo.stanza @@ -69,6 +69,7 @@ defn prim-width (type:Type) -> Int : match(type) : (t:UIntType) : sane-width(width(t)) (t:SIntType) : sane-width(width(t)) + (t:ClockType) : 1 (t) : error("Bad prim width type") defn sizeof (in: Int) -> Int : diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza index f85ff7c9..96c50c3c 100644 --- a/src/main/stanza/ir-parser.stanza +++ b/src/main/stanza/ir-parser.stanza @@ -38,8 +38,8 @@ OPERATORS[`div] = DIV-OP OPERATORS[`mod] = MOD-OP OPERATORS[`quo] = QUO-OP OPERATORS[`rem] = REM-OP -OPERATORS[`add-wrap] = ADD-WRAP-OP -OPERATORS[`sub-wrap] = SUB-WRAP-OP +OPERATORS[`addw] = ADD-WRAP-OP +OPERATORS[`subw] = SUB-WRAP-OP OPERATORS[`lt] = LESS-OP OPERATORS[`leq] = LESS-EQ-OP OPERATORS[`gt] = GREATER-OP @@ -49,20 +49,20 @@ OPERATORS[`neq] = NEQUAL-OP OPERATORS[`mux] = MUX-OP OPERATORS[`pad] = PAD-OP OPERATORS[`neg] = NEG-OP -OPERATORS[`as-UInt] = AS-UINT-OP -OPERATORS[`as-SInt] = AS-SINT-OP +OPERATORS[`asUInt] = AS-UINT-OP +OPERATORS[`asSInt] = AS-SINT-OP OPERATORS[`dshl] = DYN-SHIFT-LEFT-OP OPERATORS[`dshr] = DYN-SHIFT-RIGHT-OP OPERATORS[`shl] = SHIFT-LEFT-OP OPERATORS[`shr] = SHIFT-RIGHT-OP -OPERATORS[`convert] = CONVERT-OP -OPERATORS[`bit-and-reduce] = BIT-AND-REDUCE-OP -OPERATORS[`bit-or-reduce] = BIT-OR-REDUCE-OP -OPERATORS[`bit-xor-reduce] = BIT-XOR-REDUCE-OP -OPERATORS[`bit-not] = BIT-NOT-OP -OPERATORS[`bit-and] = BIT-AND-OP -OPERATORS[`bit-or] = BIT-OR-OP -OPERATORS[`bit-xor] = BIT-XOR-OP +OPERATORS[`cvt] = CONVERT-OP +OPERATORS[`andr] = BIT-AND-REDUCE-OP +OPERATORS[`orr] = BIT-OR-REDUCE-OP +OPERATORS[`xorr] = BIT-XOR-REDUCE-OP +OPERATORS[`not] = BIT-NOT-OP +OPERATORS[`and] = BIT-AND-OP +OPERATORS[`or] = BIT-OR-OP +OPERATORS[`xor] = BIT-XOR-OP OPERATORS[`cat] = CONCAT-OP OPERATORS[`bit] = BIT-SELECT-OP OPERATORS[`bits] = BITS-SELECT-OP @@ -187,7 +187,10 @@ defsyntax firrtl : inttype = (SInt) : SIntType(w) inttype = (SInt) : SIntType(UnknownWidth()) + clktype = (Clock) : ClockType() + type = (?t:#typeterm ?ops:#typeop ...) : apply-suffix-ops(t, ops) + type = (?t:#clktype) : t typeop = ((@get ?size:#int$)) : (fn (t) : VectorType(t, size)) typeterm = (?t:#inttype) : t @@ -213,16 +216,16 @@ defsyntax firrtl : ;Main Statement Productions defrule statements : stmt = (wire ?name:#id! #:! ?t:#type!) : DefWire(first-info(form),name, t) - stmt = (reg ?name:#id! #:! ?t:#type!) : DefRegister(first-info(form),name, t) - stmt = (cmem ?name:#id! #:! ?t:#vectype!) : DefMemory(first-info(form),name, t, false) - stmt = (smem ?name:#id! #:! ?t:#vectype!) : DefMemory(first-info(form),name, t, true) - stmt = (inst ?name:#id! #of! ?m:#ref!) : DefInstance(first-info(form),name, m) - stmt = (node ?name:#id! #=! ?e:#exp!) : DefNode(first-info(form),name, e) - stmt = (on-reset ?x:#exp := ?y:#exp!) : OnReset(first-info(form),x, y) - stmt = (read accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name, s, i,READ) - stmt = (write accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name, s, i,WRITE) - stmt = (infer accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name, s, i,INFER) - stmt = (rdwr accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name, s, i,RDWR) + stmt = (reg ?name:#id! #:! ?t:#type! ?clk:#exp! ?reset:#exp!) : DefRegister(first-info(form),name, t,clk,reset) + stmt = (cmem ?name:#id! #:! ?t:#vectype! ?clk:#exp!) : DefMemory(first-info(form),name, t, false, clk) + stmt = (smem ?name:#id! #:! ?t:#vectype! ?clk:#exp!) : DefMemory(first-info(form),name, t, true, clk) + stmt = (inst ?name:#id! #of! ?m:#ref!) : DefInstance(first-info(form),name,m) + stmt = (node ?name:#id! #=! ?e:#exp!) : DefNode(first-info(form),name,e) + stmt = (onreset ?x:#exp := ?y:#exp!) : OnReset(first-info(form),x,y) + stmt = (read accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name,s,i,READ) + stmt = (write accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name,s,i,WRITE) + stmt = (infer accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name,s,i,INFER) + stmt = (rdwr accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name,s, i,RDWR) stmt = (?s:#stmt/when) : s stmt = (?x:#exp := ?y:#exp!) : Connect(first-info(form),x, y) diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza index 8e65005f..bd8a0fd6 100644 --- a/src/main/stanza/ir-utils.stanza +++ b/src/main/stanza/ir-utils.stanza @@ -128,8 +128,8 @@ defmethod print (o:OutputStream, op:PrimOp) : MOD-OP : "mod" QUO-OP : "quo" REM-OP : "rem" - ADD-WRAP-OP : "add-wrap" - SUB-WRAP-OP : "sub-wrap" + ADD-WRAP-OP : "addw" + SUB-WRAP-OP : "subw" LESS-OP : "lt" LESS-EQ-OP : "leq" GREATER-OP : "gt" @@ -138,21 +138,21 @@ defmethod print (o:OutputStream, op:PrimOp) : NEQUAL-OP : "neq" MUX-OP : "mux" PAD-OP : "pad" - AS-UINT-OP : "as-UInt" - AS-SINT-OP : "as-SInt" + AS-UINT-OP : "asUInt" + AS-SINT-OP : "asSInt" DYN-SHIFT-LEFT-OP : "dshl" DYN-SHIFT-RIGHT-OP : "dshr" SHIFT-LEFT-OP : "shl" SHIFT-RIGHT-OP : "shr" - CONVERT-OP : "convert" + CONVERT-OP : "cvt" NEG-OP : "neg" - BIT-NOT-OP : "bit-not" - BIT-AND-OP : "bit-and" - BIT-OR-OP : "bit-or" - BIT-XOR-OP : "bit-xor" - BIT-AND-REDUCE-OP : "bit-and-reduce" - BIT-OR-REDUCE-OP : "bit-or-reduce" - BIT-XOR-REDUCE-OP : "bit-xor-reduce" + BIT-NOT-OP : "not" + BIT-AND-OP : "and" + BIT-OR-OP : "or" + BIT-XOR-OP : "xor" + BIT-AND-REDUCE-OP : "andr" + BIT-OR-REDUCE-OP : "orr" + BIT-XOR-REDUCE-OP : "xorr" CONCAT-OP : "cat" BIT-SELECT-OP : "bit" BITS-SELECT-OP : "bits" @@ -176,10 +176,10 @@ defmethod print (o:OutputStream, c:Stmt) : (c:DefWire) : print-all(o,["wire " name(c) " : " type(c)]) (c:DefRegister) : - print-all(o,["reg " name(c) " : " type(c)]) + print-all(o,["reg " name(c) " : " type(c) ", " clock(c) ", " reset(c)]) (c:DefMemory) : - if seq?(c) : print-all(o,["smem " name(c) " : " type(c)]) - else : print-all(o,["cmem " name(c) " : " type(c)]) + if seq?(c) : print-all(o,["smem " name(c) " : " type(c) ", " clock(c)]) + else : print-all(o,["cmem " name(c) " : " type(c) ", " clock(c)]) (c:DefInstance) : print-all(o,["inst " name(c) " of " module(c)]) (c:DefNode) : @@ -206,7 +206,7 @@ defmethod print (o:OutputStream, c:Stmt) : (c:BulkConnect) : print-all(o, [loc(c) " <> " exp(c)]) (c:OnReset) : - print-all(o, ["on-reset " loc(c) " := " exp(c)]) + print-all(o, ["onreset " loc(c) " := " exp(c)]) (c:EmptyStmt) : print(o, "skip") if not c typeof Conditionally|Begin|EmptyStmt : print-debug(o,c) @@ -215,6 +215,8 @@ defmethod print (o:OutputStream, t:Type) : match(t) : (t:UnknownType) : print(o, "?") + (t:ClockType) : + print(o, "Clock") (t:UIntType) : match(width(t)) : (w:UnknownWidth) : print-all(o, ["UInt"]) @@ -290,6 +292,8 @@ public defmulti map (f: Expression -> Expression, c:?T&Stmt) -> T defmethod map (f: Expression -> Expression, c:Stmt) -> Stmt : match(c) : (c:DefAccessor) : DefAccessor(info(c),name(c), f(source(c)), f(index(c)),acc-dir(c)) + (c:DefRegister) : DefRegister(info(c),name(c), type(c), f(clock(c)), f(reset(c))) + (c:DefMemory) : DefMemory(info(c),name(c), type(c), seq?(c), f(clock(c))) (c:DefNode) : DefNode(info(c),name(c), f(value(c))) (c:DefInstance) : DefInstance(info(c),name(c), f(module(c))) (c:Conditionally) : Conditionally(info(c),f(pred(c)), conseq(c), alt(c)) @@ -332,8 +336,8 @@ public defmulti map (f: Type -> Type, c:?T&Stmt) -> T defmethod map (f: Type -> Type, c:Stmt) -> Stmt : match(c) : (c:DefWire) : DefWire(info(c),name(c),f(type(c))) - (c:DefRegister) : DefRegister(info(c),name(c),f(type(c))) - (c:DefMemory) : DefMemory(info(c),name(c),f(type(c)) as VectorType,seq?(c)) + (c:DefRegister) : DefRegister(info(c),name(c),f(type(c)),clock(c),reset(c)) + (c:DefMemory) : DefMemory(info(c),name(c),f(type(c)) as VectorType,seq?(c),clock(c)) (c) : c public defmulti mapr (f: Width -> Width, t:?T&Type) -> T diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 43cc06a4..f844d7cc 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -12,7 +12,7 @@ public val standard-passes = to-list $ [ CheckHighForm(expand-delin) TempElimination() ToWorkingIR() - MakeExplicitReset() + ;MakeExplicitReset() ResolveKinds() CheckKinds() InferTypes() @@ -350,47 +350,48 @@ defn to-working-ir (c:Circuit) : ; If reset is not explicitly passed to instantiations, then this ; pass autmatically connects the parent module's reset to the ; instantiation's reset -public defstruct MakeExplicitReset <: Pass -public defmethod pass (b:MakeExplicitReset) -> (Circuit -> Circuit) : make-explicit-reset -public defmethod name (b:MakeExplicitReset) -> String : "Make Explicit Reset" -public defmethod short-name (b:MakeExplicitReset) -> String : "make-explicit-reset" - -defn make-explicit-reset (c:Circuit) : - defn find-explicit (c:Circuit) -> List : - defn explicit? (m:Module) -> True|False : - for p in ports(m) any? : - name(p) == `reset - val explicit-reset = Vector() - for m in modules(c) do: - if explicit?(m) : add(explicit-reset,name(m)) - to-list(explicit-reset) - - defn make-explicit (m:Module, explicit-reset:List) -> Module : - defn route-reset (s:Stmt) -> Stmt : - match(s) : - (s:DefInstance) : - val iref = WSubfield(WRef(name(s), UnknownType(), InstanceKind(), UNKNOWN-GENDER),`reset,UnknownType(),UNKNOWN-GENDER) - val pref = WRef(`reset, UnknownType(), PortKind(), MALE) - Begin(to-list([s,Connect(info(s),iref,pref)])) - (s) : map(route-reset,s) - - var ports! = ports(m) - if not contains?(explicit-reset,name(m)) : - ports! = append(ports(m),list(Port(FileInfo(),`reset,INPUT,UIntType(IntWidth(1))))) - match(m) : - (m:InModule) : - val body! = route-reset(body(m)) - InModule(info(m),name(m),ports!,body!) - (m:ExModule) : ExModule(info(m),name(m),ports!) - - defn make-explicit-reset (m:Module, c:Circuit) -> Module : - val explicit-reset = find-explicit(c) - make-explicit(m,explicit-reset) - Circuit(info(c),modules*, main(c)) where : - val modules* = - for m in modules(c) map : - make-explicit-reset(m,c) +;public defstruct MakeExplicitReset <: Pass +;public defmethod pass (b:MakeExplicitReset) -> (Circuit -> Circuit) : make-explicit-reset +;public defmethod name (b:MakeExplicitReset) -> String : "Make Explicit Reset" +;public defmethod short-name (b:MakeExplicitReset) -> String : "make-explicit-reset" +; +;defn make-explicit-reset (c:Circuit) : +; defn find-explicit (c:Circuit) -> List : +; defn explicit? (m:Module) -> True|False : +; for p in ports(m) any? : +; name(p) == `reset +; val explicit-reset = Vector() +; for m in modules(c) do: +; if explicit?(m) : add(explicit-reset,name(m)) +; to-list(explicit-reset) +; +; defn make-explicit (m:Module, explicit-reset:List) -> Module : +; defn route-reset (s:Stmt) -> Stmt : +; match(s) : +; (s:DefInstance) : +; val iref = WSubfield(WRef(name(s), UnknownType(), InstanceKind(), UNKNOWN-GENDER),`reset,UnknownType(),UNKNOWN-GENDER) +; val pref = WRef(`reset, UnknownType(), PortKind(), MALE) +; Begin(to-list([s,Connect(info(s),iref,pref)])) +; (s) : map(route-reset,s) +; +; var ports! = ports(m) +; if not contains?(explicit-reset,name(m)) : +; ports! = append(ports(m),list(Port(FileInfo(),`reset,INPUT,UIntType(IntWidth(1))))) +; match(m) : +; (m:InModule) : +; val body! = route-reset(body(m)) +; InModule(info(m),name(m),ports!,body!) +; (m:ExModule) : ExModule(info(m),name(m),ports!) +; +; defn make-explicit-reset (m:Module, c:Circuit) -> Module : +; val explicit-reset = find-explicit(c) +; make-explicit(m,explicit-reset) +; +; Circuit(info(c),modules*, main(c)) where : +; val modules* = +; for m in modules(c) map : +; make-explicit-reset(m,c) ;=============== Resolve Kinds ============================= ; It is useful for the compiler to know information about @@ -852,7 +853,7 @@ defn lower (body:Stmt) -> Stmt : DefWire(info(s),name(x),type(x)) (s:DefRegister) : Begin{_} $ for x in generate-entry(name(s),type(s)) map : - DefRegister(info(s),name(x),type(x)) + DefRegister(info(s),name(x),type(x),clock(s),reset(s)) (s:DefInstance) : val fields = for f in fields(type(module(s)) as BundleType) map-append : @@ -866,7 +867,7 @@ defn lower (body:Stmt) -> Stmt : DefNode(info(s),name(s),exp(x)) (s:DefMemory) : Begin $ for x in generate-entry(name(s),type(type(s))) map : - DefMemory(info(s),name(x),VectorType(type(x),size(s)), seq?(s)) + DefMemory(info(s),name(x),VectorType(type(x),size(s)),seq?(s),clock(s)) (s:DefAccessor) : val ls = generate-entry(name(s),type(s)) val rs = generate-entry(name(source(s) as WRef),type(s)) @@ -1262,14 +1263,13 @@ defn get-write-enable (sv:SymbolicValue) -> SymbolicValue : (sv: SVNul) : SVExp(zero) (sv) : sv -defn merge-resets (assign:HashTable, resets:HashTable) -> HashTable : +defn merge-resets (assign:HashTable, resets:HashTable, rsignals:HashTable) -> HashTable : val table = HashTable(symbol-hash) - val reset = WRef(`reset, UnknownType(), PortKind(), MALE) for i in get-unique-keys(list(assign,resets)) do : table[i] = match(get?(assign,i,false),get?(resets,i,false)) : - (a:SymbolicValue,r:SymbolicValue) : SVMux(reset,r,a) + (a:SymbolicValue,r:SymbolicValue) : SVMux(rsignals[i],r,a) (a:SymbolicValue,r:False) : a - (a:False,r:SymbolicValue) : SVMux(reset,r,SVNul()) + (a:False,r:SymbolicValue) : SVMux(rsignals[i],r,SVNul()) (a:False,r:False) : error("Shouldn't be here") table @@ -1277,12 +1277,17 @@ defn build-tables (s:Stmt, assign:HashTable, resets:HashTable, flattn:HashTable, + rsignals:HashTable, ) -> False : match(s) : (s:DefWire) : assign[name(s)] = SVNul() flattn[name(s)] = true - (s:DefRegister|DefAccessor) : + (s:DefRegister) : + assign[name(s)] = SVNul() + flattn[name(s)] = false + rsignals[name(s)] = reset(s) + (s:DefAccessor) : assign[name(s)] = SVNul() flattn[name(s)] = false (s:DefInstance) : ;TODO only add instance input ports. This probably involves correcting instance genders @@ -1313,8 +1318,8 @@ defn build-tables (s:Stmt, val assign-a = deepcopy(assign) val resets-c = deepcopy(resets) val resets-a = deepcopy(resets) - build-tables(conseq(s),assign-c,resets-c,flattn) - build-tables(alt(s),assign-a,resets-a,flattn) + build-tables(conseq(s),assign-c,resets-c,flattn,rsignals) + build-tables(alt(s),assign-a,resets-a,flattn,rsignals) for i in get-unique-keys(list(assign-c,assign-a)) do : assign[i] = combine(flattn,assign-c,assign-a,i) as SymbolicValue val r = combine(flattn,resets-c,resets-a,i) @@ -1334,7 +1339,7 @@ defn build-tables (s:Stmt, (e) : error("Shouldn't be here with ~" % [e]) if s typeof Connect : assign[key*] = SVExp(exp(s)) if s typeof OnReset : resets[key*] = SVExp(exp(s)) - (s:Begin) : for s* in body(s) do: build-tables(s*,assign,resets,flattn) + (s:Begin) : for s* in body(s) do: build-tables(s*,assign,resets,flattn,rsignals) (s:DefMemory|DefNode|EmptyStmt) : false ;--------------- Expand Whens Pass ------------------- @@ -1410,13 +1415,14 @@ public defn expand-whens (c:Circuit) -> Circuit : val assign = HashTable(symbol-hash) val resets = HashTable(symbol-hash) val flattn = HashTable(symbol-hash) + val rsignals = HashTable(symbol-hash) for p in ports(m) do : if direction(p) == OUTPUT : assign[name(p)] = SVNul() flattn[name(p)] = false - build-tables(body(m),assign,resets,flattn) + build-tables(body(m),assign,resets,flattn,rsignals) for x in assign do : assign[key(x)] = optimize(value(x)) for x in resets do : resets[key(x)] = optimize(value(x)) ;val enables = get-enables(assign,kinds) @@ -1427,7 +1433,7 @@ public defn expand-whens (c:Circuit) -> Circuit : println-debug("====== Resets ======") for x in resets do : println-debug(x) - val table = merge-resets(assign,resets) + val table = merge-resets(assign,resets,rsignals) println-debug("====== Table ======") for x in table do : println-debug(x) val decs = Vector() @@ -1654,6 +1660,7 @@ public defn width! (t:Type) -> Width : match(t) : (t:UIntType) : width(t) (t:SIntType) : width(t) + (t:ClockType) : IntWidth(1) (t) : error("No width!") public defn width! (e:Expression) -> Width : width!(type(e)) @@ -1661,10 +1668,10 @@ defn gen-constraints (m:Module, h:HashTable, v:Vector) -> Mod defn gen-constraints-s (s:Stmt) -> Stmt : match(map(gen-constraints-s,s)) : (s:DefWire) : DefWire(info(s),name(s),h[name(s)]) - (s:DefRegister) : DefRegister(info(s),name(s),h[name(s)]) + (s:DefRegister) : DefRegister(info(s),name(s),h[name(s)],gen-constraints(clock(s)),gen-constraints(reset(s))) (s:DefAccessor) : DefAccessor(info(s),name(s),gen-constraints(source(s)),gen-constraints(index(s)), acc-dir(s)) (s:DefInstance) : DefInstance(info(s),name(s),gen-constraints(module(s))) - (s:DefMemory) : DefMemory(info(s),name(s),h[name(s)] as VectorType,seq?(s)) + (s:DefMemory) : DefMemory(info(s),name(s),h[name(s)] as VectorType,seq?(s),gen-constraints(clock(s))) (s:DefNode) : val l = h[name(s)] val r = gen-constraints(value(s)) @@ -1720,8 +1727,7 @@ defn build-environment (c:Circuit,m:Module,h:HashTable) -> HashTabl (s:DefRegister) : h[name(s)] = remove-unknowns(type(s)) (s:DefInstance) : h[name(s)] = h[name(module(s) as WRef)] (s:DefMemory) : h[name(s)] = remove-unknowns(type(s)) - (s:DefAccessor) : - h[name(s)] = remove-unknowns(type(type(source(s)) as VectorType)) + (s:DefAccessor) : h[name(s)] = remove-unknowns(type(type(source(s)) as VectorType)) (s:DefNode) : h[name(s)] = remove-unknowns(type(value(s))) (s) : false do(build-environment,s) @@ -1867,9 +1873,9 @@ defn inline-instances (c:Circuit) : defn rename-s (s:Stmt,n:Symbol) -> Stmt : map{rename-e{_,n},_} $ match(map(rename-s{_,n},s)) : (s:DefWire) : DefWire(info(s),rename(name(s),n),type(s)) - (s:DefRegister) : DefRegister(info(s),rename(name(s),n),type(s)) + (s:DefRegister) : DefRegister(info(s),rename(name(s),n),type(s),clock(s),reset(s)) (s:DefInstance) : error("Shouldn't be here") - (s:DefMemory) : DefMemory(info(s),rename(name(s),n),type(s),seq?(s)) + (s:DefMemory) : DefMemory(info(s),rename(name(s),n),type(s),seq?(s),clock(s)) (s:DefNode) : DefNode(info(s),rename(name(s),n),value(s)) (s) : s for m in modules(c) do : @@ -1898,11 +1904,17 @@ defn split-exp (c:Circuit) : defn split-exp-e (e:Expression,n:Symbol|False,info:FileInfo) -> Expression : match(map(split-exp-e{_,n,info},e)) : (e:DoPrim) : - val n* = - if n typeof False : firrtl-gensym(`T,sh) - else : firrtl-gensym(symbol-join([n as Symbol gen-delin]),sh) - add(v,DefNode(info,n*,e)) - WRef(n*,type(e),NodeKind(),UNKNOWN-GENDER) + var all-same-type? = true + for x in args(e) do : + if type(x) != type(e) : all-same-type? = false + all-same-type? = false + if not all-same-type? : + val n* = + if n typeof False : firrtl-gensym(`T,sh) + else : firrtl-gensym(symbol-join([n as Symbol gen-delin]),sh) + add(v,DefNode(info,n*,e)) + WRef(n*,type(e),NodeKind(),UNKNOWN-GENDER) + else : e (e) : e defn f (s:Stmt) -> False: split-exp-s(s,v,sh) match(s) : @@ -1913,25 +1925,24 @@ defn split-exp (c:Circuit) : do(f,s) (s:Connect) : match(loc(s)) : - ;(e:WritePort) : add(v,map(split-exp-e{_,full-name(exp(s)),info(s)},s)) (e) : add(v,map(split-exp-e{_,full-name(loc(s)),info(s)},s)) (s:DefNode) : add(v,map(split-exp-e{_,name(s),info(s)},s)) (s) : add(v,map(split-exp-e{_,false,info(s)},s)) false - val start-time = current-time-us() + ;val start-time = current-time-us() Circuit{info(c),_,main(c)} $ for m in modules(c) map : match(m) : (m:InModule) : val v = Vector() val sh = get-sym-hash(m) - val before = current-time-us() - start-time - println-all(["Before split: " before]) + ;val before = current-time-us() - start-time + ;println-all(["Before split: " before]) split-exp-s(body(m),v,sh) - val now = current-time-us() - start-time - println-all(["After split: " now]) - println-all(["Diff: " now - before]) + ;val now = current-time-us() - start-time + ;println-all(["After split: " now]) + ;println-all(["Diff: " now - before]) InModule(info(m),name(m),ports(m),Begin(to-list(v))) (m:ExModule) : m @@ -2005,9 +2016,9 @@ public defn special-rename (original-sym:Symbol,new-sym:Symbol,c:Circuit) : defn to-stmt (s:Stmt) -> Stmt : map{to-type,_} $ match(map(to-exp,s)) : (s:DefWire) : DefWire(info(s),rename(name(s)),type(s)) - (s:DefRegister) : DefRegister(info(s),rename(name(s)),type(s)) + (s:DefRegister) : DefRegister(info(s),rename(name(s)),type(s),clock(s),reset(s)) (s:DefInstance) : DefInstance(info(s),rename(name(s)),module(s)) - (s:DefMemory) : DefMemory(info(s),rename(name(s)),type(s),seq?(s)) + (s:DefMemory) : DefMemory(info(s),rename(name(s)),type(s),seq?(s),clock(s)) (s:DefNode) : DefNode(info(s),rename(name(s)),value(s)) (s:DefAccessor) : DefAccessor(info(s),rename(name(s)),source(s),index(s),acc-dir(s)) (s) : map(to-stmt,s) diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index 1904f92f..23591f45 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -36,6 +36,7 @@ defn get-width (t:Type) -> String : match(t) : (t:UIntType) : emit(width(t)) (t:SIntType) : emit(width(t)) + (t:ClockType) : emit(IntWidth(1)) (t) : error("Non-supported type.") defn remove-subfield (e:Expression) -> Expression : @@ -140,8 +141,8 @@ defn get-name (e:Expression) -> Symbol : (e) : error("Shouldn't be here") defn emit-module (m:InModule) : - val vdecs = Vector>() ; all declarations - val decs = HashTable(symbol-hash) ; all declarations + val vdecs = Vector>() ; all declarations in order, to preserve ordering + val decs = HashTable(symbol-hash) ; all declarations, for fast lookups val cons = HashTable(symbol-hash) ; all connections val ens = HashTable(symbol-hash) ; all enables defn build-table (m:InModule) : @@ -166,7 +167,7 @@ defn emit-module (m:InModule) : val regs = Vector() val inits = Vector() val assigns = Vector() - val updates = Vector() + val updates = HashTable>(symbol-hash) val insts = HashTable(symbol-hash) ; inst -> module val inst-ports = HashTable>(symbol-hash) @@ -180,12 +181,14 @@ defn emit-module (m:InModule) : add(assigns,["assign " sym " = " emit(cons[sym]) ";"]) (s:DefRegister) : add(regs,["reg " get-width(type(s)) " " sym ";"]) + val my-clk-update = get?(updates,get-name(clock(s)),Vector()) if key?(ens,sym) : - add(updates,["if(" emit(ens[sym]) ") begin"]) - add(updates,[" " sym " <= " emit(cons[sym]) ";"]) - add(updates,["end"]) + add(my-clk-update,["if(" emit(ens[sym]) ") begin"]) + add(my-clk-update,[" " sym " <= " emit(cons[sym]) ";"]) + add(my-clk-update,["end"]) else : - add(updates,[sym " <= " emit(cons[sym]) ";"]) + add(my-clk-update,[sym " <= " emit(cons[sym]) ";"]) + updates[get-name(clock(s))] = my-clk-update (s:DefMemory) : val vtype = type(s) as VectorType add(regs,["reg " get-width(type(vtype)) " " sym " [0:" size(vtype) "];"]) @@ -204,15 +207,17 @@ defn emit-module (m:InModule) : if flip(f) == REVERSE : add(assigns,["assign " n* " = " emit(cons[n*]) ";"]) (s:DefAccessor) : + val mem-declaration = decs[name(source(s) as Ref)] as DefMemory switch {_ == acc-dir(s)} : READ : - val mem-declaration = decs[name(source(s) as Ref)] - if seq?(mem-declaration as DefMemory) : + if seq?(mem-declaration) : ; to make it sequential, register the index for an additional cycle val index* = Ref(firrtl-gensym(name(index(s) as Ref),sh),type(index(s))) add(regs,[ "reg " get-width(type(index*)) " " name(index*) ";"]) add(inits,[name(index*) " = {" width!(type(index*)) "{$random}};"]) - add(updates,[name(index*) " <= " emit(index(s)) ";"]) + val my-clk-update = get?(updates,get-name(clock(mem-declaration)),Vector()) + add(my-clk-update,[name(index*) " <= " emit(index(s)) ";"]) + updates[get-name(clock(mem-declaration))] = my-clk-update ; emit read accessor add(wires,["wire " get-width(type(type(source(s)) as VectorType)) " " sym ";"]) @@ -222,27 +227,28 @@ defn emit-module (m:InModule) : add(wires,["wire " get-width(type(type(source(s)) as VectorType)) " " sym ";"]) add(assigns,["assign " sym " = " emit(source(s)) "[" emit(index(s)) "];"]) WRITE : + val my-clk-update = get?(updates,get-name(clock(mem-declaration)),Vector()) if key?(ens,sym) : - add(updates,["if(" emit(ens[sym]) ") begin"]) - add(updates,[" " emit(source(s)) "[" emit(index(s)) "] <= " emit(cons[sym]) ";"]) - add(updates,["end"]) + add(my-clk-update,["if(" emit(ens[sym]) ") begin"]) + add(my-clk-update,[" " emit(source(s)) "[" emit(index(s)) "] <= " emit(cons[sym]) ";"]) + add(my-clk-update,["end"]) else : - add(updates,[emit(source(s)) "[" emit(index(s)) "] <= " emit(cons[sym]) ";"]) + add(my-clk-update,[emit(source(s)) "[" emit(index(s)) "] <= " emit(cons[sym]) ";"]) + updates[get-name(clock(mem-declaration))] = my-clk-update ;==== Actually printing module ===== val port-indent = " " - print-all(["module " name(m) "(input clk, input reset,\n"]) + print-all(["module " name(m) "(\n"]) for (p in ports(m),i in 1 to false) do : - if name(p) !=`reset : - var end = ",\n" - if length(ports(m)) - 1 == i : - end = "\n);\n" - switch {_ == direction(p)} : - INPUT : - print-all([port-indent "input " get-width(type(p)) " " name(p) end]) - OUTPUT : - print-all([port-indent "output " get-width(type(p)) " " name(p) end]) - add(assigns,["assign " name(p) " = " emit(cons[name(p)]) ";"]) + var end = ",\n" + if length(ports(m)) == i : + end = "\n);\n" + switch {_ == direction(p)} : + INPUT : + print-all([port-indent "input " get-width(type(p)) " " name(p) end]) + OUTPUT : + print-all([port-indent "output " get-width(type(p)) " " name(p) end]) + add(assigns,["assign " name(p) " = " emit(cons[name(p)]) ";"]) for w in wires do : print(" ") @@ -268,23 +274,22 @@ defn emit-module (m:InModule) : for x in insts do : println-all([" " value(x) " " key(x) " ("]) - print(" ") - print-all([".clk( clk )"]) + ;print-all([".clk( clk )"]) for (y in inst-ports[key(x)],i in 1 to false) do : - print(",\n") print(" ") print-all(y) - ;if length(inst-ports[key(x)]) != i : - ;print(",\n") + if length(inst-ports[key(x)]) != i : + print(",\n") println("\n );") - if length(updates) != 0 : - println(" always @(posedge clk) begin") - for u in updates do : - print(" ") - println-all(u) - println(" end") - + for x in updates do : + if length(value(x)) != 0 : + println-all([" always @(posedge " key(x) ") begin"]) + for u in value(x) do : + print(" ") + println-all(u) + println(" end") + println("endmodule") diff --git a/test/chisel3/ALUTop.fir b/test/chisel3/ALUTop.fir index a6fdfd95..df7235b7 100644 --- a/test/chisel3/ALUTop.fir +++ b/test/chisel3/ALUTop.fir @@ -1,5 +1,5 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s -;CHECK: Done! +; CHECK: Done! circuit ALUTop : module ALU : @@ -10,23 +10,23 @@ circuit ALUTop : input alu_op : UInt<4> node shamt = bits(B, 4, 0) - node T_157 = add-wrap(A, B) - node T_158 = sub-wrap(A, B) - node T_159 = as-SInt(A) + node T_157 = addw(A, B) + node T_158 = subw(A, B) + node T_159 = asSInt(A) node T_160 = dshr(T_159, shamt) - node T_161 = as-UInt(T_160) + node T_161 = asUInt(T_160) node T_162 = dshr(A, shamt) node T_163 = dshl(A, shamt) node T_164 = bits(T_163, 31, 0) - node T_165 = convert(A) - node T_166 = convert(B) + node T_165 = cvt(A) + node T_166 = cvt(B) node T_167 = lt(T_165, T_166) - node T_168 = as-UInt(T_167) + node T_168 = asUInt(T_167) node T_169 = lt(A, B) - node T_170 = as-UInt(T_169) - node T_171 = bit-and(A, B) - node T_172 = bit-or(A, B) - node T_173 = bit-xor(A, B) + node T_170 = asUInt(T_169) + node T_171 = and(A, B) + node T_172 = or(A, B) + node T_173 = xor(A, B) node T_174 = eq(UInt<4>(10), alu_op) node T_175 = mux(T_174, A, B) node T_176 = eq(UInt<4>(4), alu_op) @@ -52,9 +52,9 @@ circuit ALUTop : node T_195 = bits(oot, 31, 0) out := T_195 node T_196 = bit(alu_op, 0) - node T_197 = sub-wrap(UInt<1>(0), B) + node T_197 = subw(UInt<1>(0), B) node T_198 = mux(T_196, T_197, B) - node T_199 = add-wrap(A, T_198) + node T_199 = addw(A, T_198) sum := T_199 module ALUdec : input opcode : UInt<7> diff --git a/test/chisel3/Control.fir b/test/chisel3/Control.fir index 28bb3d87..08824c33 100644 --- a/test/chisel3/Control.fir +++ b/test/chisel3/Control.fir @@ -3,93 +3,95 @@ circuit Control : module Control : + input clk : Clock + input reset : UInt<1> output ctrl : {flip inst : UInt<32>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>, pc_sel : UInt<1>, inst_re : UInt<1>, flip stall : UInt<1>, data_re : UInt<1>, inst_type : UInt<1>, A_sel : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>} - node T_831 = bit-and(UInt<7>(127), ctrl.inst) + node T_831 = and(UInt<7>(127), ctrl.inst) node T_832 = eq(T_831, UInt<6>(55)) - node T_833 = bit-and(UInt<7>(127), ctrl.inst) + node T_833 = and(UInt<7>(127), ctrl.inst) node T_834 = eq(T_833, UInt<5>(23)) - node T_835 = bit-and(UInt<7>(127), ctrl.inst) + node T_835 = and(UInt<7>(127), ctrl.inst) node T_836 = eq(T_835, UInt<7>(111)) - node T_837 = bit-and(UInt<15>(28799), ctrl.inst) + node T_837 = and(UInt<15>(28799), ctrl.inst) node T_838 = eq(T_837, UInt<7>(103)) - node T_839 = bit-and(UInt<15>(28799), ctrl.inst) + node T_839 = and(UInt<15>(28799), ctrl.inst) node T_840 = eq(T_839, UInt<7>(99)) - node T_841 = bit-and(UInt<15>(28799), ctrl.inst) + node T_841 = and(UInt<15>(28799), ctrl.inst) node T_842 = eq(T_841, UInt<13>(4195)) - node T_843 = bit-and(UInt<15>(28799), ctrl.inst) + node T_843 = and(UInt<15>(28799), ctrl.inst) node T_844 = eq(T_843, UInt<15>(16483)) - node T_845 = bit-and(UInt<15>(28799), ctrl.inst) + node T_845 = and(UInt<15>(28799), ctrl.inst) node T_846 = eq(T_845, UInt<15>(20579)) - node T_847 = bit-and(UInt<15>(28799), ctrl.inst) + node T_847 = and(UInt<15>(28799), ctrl.inst) node T_848 = eq(T_847, UInt<15>(24675)) - node T_849 = bit-and(UInt<15>(28799), ctrl.inst) + node T_849 = and(UInt<15>(28799), ctrl.inst) node T_850 = eq(T_849, UInt<15>(28771)) - node T_851 = bit-and(UInt<15>(28799), ctrl.inst) + node T_851 = and(UInt<15>(28799), ctrl.inst) node T_852 = eq(T_851, UInt<2>(3)) - node T_853 = bit-and(UInt<15>(28799), ctrl.inst) + node T_853 = and(UInt<15>(28799), ctrl.inst) node T_854 = eq(T_853, UInt<13>(4099)) - node T_855 = bit-and(UInt<15>(28799), ctrl.inst) + node T_855 = and(UInt<15>(28799), ctrl.inst) node T_856 = eq(T_855, UInt<14>(8195)) - node T_857 = bit-and(UInt<15>(28799), ctrl.inst) + node T_857 = and(UInt<15>(28799), ctrl.inst) node T_858 = eq(T_857, UInt<15>(16387)) - node T_859 = bit-and(UInt<15>(28799), ctrl.inst) + node T_859 = and(UInt<15>(28799), ctrl.inst) node T_860 = eq(T_859, UInt<15>(20483)) - node T_861 = bit-and(UInt<15>(28799), ctrl.inst) + node T_861 = and(UInt<15>(28799), ctrl.inst) node T_862 = eq(T_861, UInt<6>(35)) - node T_863 = bit-and(UInt<15>(28799), ctrl.inst) + node T_863 = and(UInt<15>(28799), ctrl.inst) node T_864 = eq(T_863, UInt<13>(4131)) - node T_865 = bit-and(UInt<15>(28799), ctrl.inst) + node T_865 = and(UInt<15>(28799), ctrl.inst) node T_866 = eq(T_865, UInt<14>(8227)) - node T_867 = bit-and(UInt<15>(28799), ctrl.inst) + node T_867 = and(UInt<15>(28799), ctrl.inst) node T_868 = eq(T_867, UInt<5>(19)) - node T_869 = bit-and(UInt<15>(28799), ctrl.inst) + node T_869 = and(UInt<15>(28799), ctrl.inst) node T_870 = eq(T_869, UInt<14>(8211)) - node T_871 = bit-and(UInt<15>(28799), ctrl.inst) + node T_871 = and(UInt<15>(28799), ctrl.inst) node T_872 = eq(T_871, UInt<14>(12307)) - node T_873 = bit-and(UInt<15>(28799), ctrl.inst) + node T_873 = and(UInt<15>(28799), ctrl.inst) node T_874 = eq(T_873, UInt<15>(16403)) - node T_875 = bit-and(UInt<15>(28799), ctrl.inst) + node T_875 = and(UInt<15>(28799), ctrl.inst) node T_876 = eq(T_875, UInt<15>(24595)) - node T_877 = bit-and(UInt<15>(28799), ctrl.inst) + node T_877 = and(UInt<15>(28799), ctrl.inst) node T_878 = eq(T_877, UInt<15>(28691)) - node T_879 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_879 = and(UInt<32>(4261441663), ctrl.inst) node T_880 = eq(T_879, UInt<13>(4115)) - node T_881 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_881 = and(UInt<32>(4261441663), ctrl.inst) node T_882 = eq(T_881, UInt<15>(20499)) - node T_883 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_883 = and(UInt<32>(4261441663), ctrl.inst) node T_884 = eq(T_883, UInt<31>(1073762323)) - node T_885 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_885 = and(UInt<32>(4261441663), ctrl.inst) node T_886 = eq(T_885, UInt<6>(51)) - node T_887 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_887 = and(UInt<32>(4261441663), ctrl.inst) node T_888 = eq(T_887, UInt<31>(1073741875)) - node T_889 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_889 = and(UInt<32>(4261441663), ctrl.inst) node T_890 = eq(T_889, UInt<13>(4147)) - node T_891 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_891 = and(UInt<32>(4261441663), ctrl.inst) node T_892 = eq(T_891, UInt<14>(8243)) - node T_893 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_893 = and(UInt<32>(4261441663), ctrl.inst) node T_894 = eq(T_893, UInt<14>(12339)) - node T_895 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_895 = and(UInt<32>(4261441663), ctrl.inst) node T_896 = eq(T_895, UInt<15>(16435)) - node T_897 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_897 = and(UInt<32>(4261441663), ctrl.inst) node T_898 = eq(T_897, UInt<15>(20531)) - node T_899 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_899 = and(UInt<32>(4261441663), ctrl.inst) node T_900 = eq(T_899, UInt<31>(1073762355)) - node T_901 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_901 = and(UInt<32>(4261441663), ctrl.inst) node T_902 = eq(T_901, UInt<15>(24627)) - node T_903 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_903 = and(UInt<32>(4261441663), ctrl.inst) node T_904 = eq(T_903, UInt<15>(28723)) - node T_905 = bit-and(UInt<15>(28799), ctrl.inst) + node T_905 = and(UInt<15>(28799), ctrl.inst) node T_906 = eq(T_905, UInt<13>(4211)) - node T_907 = bit-and(UInt<15>(28799), ctrl.inst) + node T_907 = and(UInt<15>(28799), ctrl.inst) node T_908 = eq(T_907, UInt<14>(8307)) - node T_909 = bit-and(UInt<15>(28799), ctrl.inst) + node T_909 = and(UInt<15>(28799), ctrl.inst) node T_910 = eq(T_909, UInt<14>(12403)) - node T_911 = bit-and(UInt<15>(28799), ctrl.inst) + node T_911 = and(UInt<15>(28799), ctrl.inst) node T_912 = eq(T_911, UInt<15>(20595)) - node T_913 = bit-and(UInt<15>(28799), ctrl.inst) + node T_913 = and(UInt<15>(28799), ctrl.inst) node T_914 = eq(T_913, UInt<15>(24691)) - node T_915 = bit-and(UInt<15>(28799), ctrl.inst) + node T_915 = and(UInt<15>(28799), ctrl.inst) node T_916 = eq(T_915, UInt<15>(28787)) node T_917 = mux(T_916, UInt<1>(0), UInt<1>(0)) node T_918 = mux(T_914, UInt<1>(0), T_917) @@ -609,20 +611,20 @@ circuit Control : node T_1432 = mux(T_832, UInt<2>(0), T_1431) node rs1_addr = bits(ctrl.inst, 19, 15) node rs2_addr = bits(ctrl.inst, 24, 20) - reg st_type : UInt<2> - reg ld_type : UInt<3> - reg wb_sel : UInt<2> + reg st_type : UInt<2>, clk, reset + reg ld_type : UInt<3>, clk, reset + reg wb_sel : UInt<2>, clk, reset node T_1433 = bit(T_1389, 0) - reg wb_en : UInt<1> - reg csr_cmd : UInt<2> + reg wb_en : UInt<1>, clk, reset + reg csr_cmd : UInt<2>, clk, reset ctrl.pc_sel := T_959 - node T_1434 = bit-not(ctrl.stall) - node T_1435 = bit-not(ctrl.data_re) - node T_1436 = bit-and(T_1434, T_1435) + node T_1434 = not(ctrl.stall) + node T_1435 = not(ctrl.data_re) + node T_1436 = and(T_1434, T_1435) ctrl.inst_re := T_1436 node T_1437 = neq(T_1303, UInt<3>(7)) node T_1438 = bit(T_1217, 0) - node T_1439 = bit-or(T_1437, T_1438) + node T_1439 = or(T_1437, T_1438) node T_1440 = mux(T_1439, UInt<1>(1), UInt<1>(0)) ctrl.inst_type := T_1440 ctrl.A_sel := T_1002 @@ -631,7 +633,7 @@ circuit Control : ctrl.alu_op := T_1131 ctrl.br_type := T_1174 ctrl.st_type := T_1260 - node T_1441 = bit-not(ctrl.stall) + node T_1441 = not(ctrl.stall) when T_1441 : st_type := ctrl.st_type ld_type := T_1303 diff --git a/test/chisel3/Core.fir b/test/chisel3/Core.fir index e9aef65f..7e87bb07 100644 --- a/test/chisel3/Core.fir +++ b/test/chisel3/Core.fir @@ -364,646 +364,648 @@ circuit Core : regFile.waddr := ex_rd_addr regFile.wdata := regWrite module Control : - output ctrl : {flip inst : UInt<32>, flip stall : UInt<1>, pc_sel : UInt<1>, inst_re : UInt<1>, inst_type : UInt<1>, A_sel : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>, data_re : UInt<1>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>} + input clk : Clock + input reset : UInt<1> + output ctrl : {flip inst : UInt<32>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>, pc_sel : UInt<1>, inst_re : UInt<1>, flip stall : UInt<1>, data_re : UInt<1>, inst_type : UInt<1>, A_sel : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>} - node T_1436 = bit-and(UInt<7>(127), ctrl.inst) - node T_1437 = eq(T_1436, UInt<6>(55)) - node T_1438 = bit-and(UInt<7>(127), ctrl.inst) - node T_1439 = eq(T_1438, UInt<5>(23)) - node T_1440 = bit-and(UInt<7>(127), ctrl.inst) - node T_1441 = eq(T_1440, UInt<7>(111)) - node T_1442 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1443 = eq(T_1442, UInt<7>(103)) - node T_1444 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1445 = eq(T_1444, UInt<7>(99)) - node T_1446 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1447 = eq(T_1446, UInt<13>(4195)) - node T_1448 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1449 = eq(T_1448, UInt<15>(16483)) - node T_1450 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1451 = eq(T_1450, UInt<15>(20579)) - node T_1452 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1453 = eq(T_1452, UInt<15>(24675)) - node T_1454 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1455 = eq(T_1454, UInt<15>(28771)) - node T_1456 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1457 = eq(T_1456, UInt<2>(3)) - node T_1458 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1459 = eq(T_1458, UInt<13>(4099)) - node T_1460 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1461 = eq(T_1460, UInt<14>(8195)) - node T_1462 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1463 = eq(T_1462, UInt<15>(16387)) - node T_1464 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1465 = eq(T_1464, UInt<15>(20483)) - node T_1466 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1467 = eq(T_1466, UInt<6>(35)) - node T_1468 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1469 = eq(T_1468, UInt<13>(4131)) - node T_1470 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1471 = eq(T_1470, UInt<14>(8227)) - node T_1472 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1473 = eq(T_1472, UInt<5>(19)) - node T_1474 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1475 = eq(T_1474, UInt<14>(8211)) - node T_1476 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1477 = eq(T_1476, UInt<14>(12307)) - node T_1478 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1479 = eq(T_1478, UInt<15>(16403)) - node T_1480 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1481 = eq(T_1480, UInt<15>(24595)) - node T_1482 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1483 = eq(T_1482, UInt<15>(28691)) - node T_1484 = bit-and(UInt<32>(4261441663), ctrl.inst) - node T_1485 = eq(T_1484, UInt<13>(4115)) - node T_1486 = bit-and(UInt<32>(4261441663), ctrl.inst) - node T_1487 = eq(T_1486, UInt<15>(20499)) - node T_1488 = bit-and(UInt<32>(4261441663), ctrl.inst) - node T_1489 = eq(T_1488, UInt<31>(1073762323)) - node T_1490 = bit-and(UInt<32>(4261441663), ctrl.inst) - node T_1491 = eq(T_1490, UInt<6>(51)) - node T_1492 = bit-and(UInt<32>(4261441663), ctrl.inst) - node T_1493 = eq(T_1492, UInt<31>(1073741875)) - node T_1494 = bit-and(UInt<32>(4261441663), ctrl.inst) - node T_1495 = eq(T_1494, UInt<13>(4147)) - node T_1496 = bit-and(UInt<32>(4261441663), ctrl.inst) - node T_1497 = eq(T_1496, UInt<14>(8243)) - node T_1498 = bit-and(UInt<32>(4261441663), ctrl.inst) - node T_1499 = eq(T_1498, UInt<14>(12339)) - node T_1500 = bit-and(UInt<32>(4261441663), ctrl.inst) - node T_1501 = eq(T_1500, UInt<15>(16435)) - node T_1502 = bit-and(UInt<32>(4261441663), ctrl.inst) - node T_1503 = eq(T_1502, UInt<15>(20531)) - node T_1504 = bit-and(UInt<32>(4261441663), ctrl.inst) - node T_1505 = eq(T_1504, UInt<31>(1073762355)) - node T_1506 = bit-and(UInt<32>(4261441663), ctrl.inst) - node T_1507 = eq(T_1506, UInt<15>(24627)) - node T_1508 = bit-and(UInt<32>(4261441663), ctrl.inst) - node T_1509 = eq(T_1508, UInt<15>(28723)) - node T_1510 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1511 = eq(T_1510, UInt<13>(4211)) - node T_1512 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1513 = eq(T_1512, UInt<14>(8307)) - node T_1514 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1515 = eq(T_1514, UInt<14>(12403)) - node T_1516 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1517 = eq(T_1516, UInt<15>(20595)) - node T_1518 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1519 = eq(T_1518, UInt<15>(24691)) - node T_1520 = bit-and(UInt<15>(28799), ctrl.inst) - node T_1521 = eq(T_1520, UInt<15>(28787)) - node T_1522 = mux(T_1521, UInt<1>(0), UInt<1>(0)) - node T_1523 = mux(T_1519, UInt<1>(0), T_1522) - node T_1524 = mux(T_1517, UInt<1>(0), T_1523) - node T_1525 = mux(T_1515, UInt<1>(0), T_1524) - node T_1526 = mux(T_1513, UInt<1>(0), T_1525) - node T_1527 = mux(T_1511, UInt<1>(0), T_1526) - node T_1528 = mux(T_1509, UInt<1>(0), T_1527) - node T_1529 = mux(T_1507, UInt<1>(0), T_1528) - node T_1530 = mux(T_1505, UInt<1>(0), T_1529) - node T_1531 = mux(T_1503, UInt<1>(0), T_1530) - node T_1532 = mux(T_1501, UInt<1>(0), T_1531) - node T_1533 = mux(T_1499, UInt<1>(0), T_1532) - node T_1534 = mux(T_1497, UInt<1>(0), T_1533) - node T_1535 = mux(T_1495, UInt<1>(0), T_1534) - node T_1536 = mux(T_1493, UInt<1>(0), T_1535) - node T_1537 = mux(T_1491, UInt<1>(0), T_1536) - node T_1538 = mux(T_1489, UInt<1>(0), T_1537) - node T_1539 = mux(T_1487, UInt<1>(0), T_1538) - node T_1540 = mux(T_1485, UInt<1>(0), T_1539) - node T_1541 = mux(T_1483, UInt<1>(0), T_1540) - node T_1542 = mux(T_1481, UInt<1>(0), T_1541) - node T_1543 = mux(T_1479, UInt<1>(0), T_1542) - node T_1544 = mux(T_1477, UInt<1>(0), T_1543) - node T_1545 = mux(T_1475, UInt<1>(0), T_1544) - node T_1546 = mux(T_1473, UInt<1>(0), T_1545) - node T_1547 = mux(T_1471, UInt<1>(0), T_1546) - node T_1548 = mux(T_1469, UInt<1>(0), T_1547) - node T_1549 = mux(T_1467, UInt<1>(0), T_1548) - node T_1550 = mux(T_1465, UInt<1>(0), T_1549) - node T_1551 = mux(T_1463, UInt<1>(0), T_1550) - node T_1552 = mux(T_1461, UInt<1>(0), T_1551) - node T_1553 = mux(T_1459, UInt<1>(0), T_1552) - node T_1554 = mux(T_1457, UInt<1>(0), T_1553) - node T_1555 = mux(T_1455, UInt<1>(0), T_1554) - node T_1556 = mux(T_1453, UInt<1>(0), T_1555) - node T_1557 = mux(T_1451, UInt<1>(0), T_1556) - node T_1558 = mux(T_1449, UInt<1>(0), T_1557) - node T_1559 = mux(T_1447, UInt<1>(0), T_1558) - node T_1560 = mux(T_1445, UInt<1>(0), T_1559) - node T_1561 = mux(T_1443, UInt<1>(1), T_1560) - node T_1562 = mux(T_1441, UInt<1>(1), T_1561) - node T_1563 = mux(T_1439, UInt<1>(0), T_1562) - node T_1564 = mux(T_1437, UInt<1>(0), T_1563) - node T_1565 = mux(T_1521, UInt<1>(1), UInt<1>(1)) - node T_1566 = mux(T_1519, UInt<1>(1), T_1565) - node T_1567 = mux(T_1517, UInt<1>(1), T_1566) - node T_1568 = mux(T_1515, UInt<1>(0), T_1567) - node T_1569 = mux(T_1513, UInt<1>(0), T_1568) - node T_1570 = mux(T_1511, UInt<1>(0), T_1569) - node T_1571 = mux(T_1509, UInt<1>(0), T_1570) - node T_1572 = mux(T_1507, UInt<1>(0), T_1571) - node T_1573 = mux(T_1505, UInt<1>(0), T_1572) - node T_1574 = mux(T_1503, UInt<1>(0), T_1573) - node T_1575 = mux(T_1501, UInt<1>(0), T_1574) - node T_1576 = mux(T_1499, UInt<1>(0), T_1575) - node T_1577 = mux(T_1497, UInt<1>(0), T_1576) - node T_1578 = mux(T_1495, UInt<1>(0), T_1577) - node T_1579 = mux(T_1493, UInt<1>(0), T_1578) - node T_1580 = mux(T_1491, UInt<1>(0), T_1579) - node T_1581 = mux(T_1489, UInt<1>(0), T_1580) - node T_1582 = mux(T_1487, UInt<1>(0), T_1581) - node T_1583 = mux(T_1485, UInt<1>(0), T_1582) - node T_1584 = mux(T_1483, UInt<1>(0), T_1583) - node T_1585 = mux(T_1481, UInt<1>(0), T_1584) - node T_1586 = mux(T_1479, UInt<1>(0), T_1585) - node T_1587 = mux(T_1477, UInt<1>(0), T_1586) - node T_1588 = mux(T_1475, UInt<1>(0), T_1587) - node T_1589 = mux(T_1473, UInt<1>(0), T_1588) - node T_1590 = mux(T_1471, UInt<1>(0), T_1589) - node T_1591 = mux(T_1469, UInt<1>(0), T_1590) - node T_1592 = mux(T_1467, UInt<1>(0), T_1591) - node T_1593 = mux(T_1465, UInt<1>(0), T_1592) - node T_1594 = mux(T_1463, UInt<1>(0), T_1593) - node T_1595 = mux(T_1461, UInt<1>(0), T_1594) - node T_1596 = mux(T_1459, UInt<1>(0), T_1595) - node T_1597 = mux(T_1457, UInt<1>(0), T_1596) - node T_1598 = mux(T_1455, UInt<1>(1), T_1597) - node T_1599 = mux(T_1453, UInt<1>(1), T_1598) - node T_1600 = mux(T_1451, UInt<1>(1), T_1599) - node T_1601 = mux(T_1449, UInt<1>(1), T_1600) - node T_1602 = mux(T_1447, UInt<1>(1), T_1601) - node T_1603 = mux(T_1445, UInt<1>(1), T_1602) - node T_1604 = mux(T_1443, UInt<1>(0), T_1603) - node T_1605 = mux(T_1441, UInt<1>(1), T_1604) - node T_1606 = mux(T_1439, UInt<1>(1), T_1605) - node T_1607 = mux(T_1437, UInt<1>(1), T_1606) - node T_1608 = mux(T_1521, UInt<1>(1), UInt<1>(0)) - node T_1609 = mux(T_1519, UInt<1>(1), T_1608) - node T_1610 = mux(T_1517, UInt<1>(1), T_1609) - node T_1611 = mux(T_1515, UInt<1>(0), T_1610) - node T_1612 = mux(T_1513, UInt<1>(0), T_1611) - node T_1613 = mux(T_1511, UInt<1>(0), T_1612) - node T_1614 = mux(T_1509, UInt<1>(0), T_1613) - node T_1615 = mux(T_1507, UInt<1>(0), T_1614) - node T_1616 = mux(T_1505, UInt<1>(0), T_1615) - node T_1617 = mux(T_1503, UInt<1>(0), T_1616) - node T_1618 = mux(T_1501, UInt<1>(0), T_1617) - node T_1619 = mux(T_1499, UInt<1>(0), T_1618) - node T_1620 = mux(T_1497, UInt<1>(0), T_1619) - node T_1621 = mux(T_1495, UInt<1>(0), T_1620) - node T_1622 = mux(T_1493, UInt<1>(0), T_1621) - node T_1623 = mux(T_1491, UInt<1>(0), T_1622) - node T_1624 = mux(T_1489, UInt<1>(1), T_1623) - node T_1625 = mux(T_1487, UInt<1>(1), T_1624) - node T_1626 = mux(T_1485, UInt<1>(1), T_1625) - node T_1627 = mux(T_1483, UInt<1>(1), T_1626) - node T_1628 = mux(T_1481, UInt<1>(1), T_1627) - node T_1629 = mux(T_1479, UInt<1>(1), T_1628) - node T_1630 = mux(T_1477, UInt<1>(1), T_1629) - node T_1631 = mux(T_1475, UInt<1>(1), T_1630) - node T_1632 = mux(T_1473, UInt<1>(1), T_1631) - node T_1633 = mux(T_1471, UInt<1>(1), T_1632) - node T_1634 = mux(T_1469, UInt<1>(1), T_1633) - node T_1635 = mux(T_1467, UInt<1>(1), T_1634) - node T_1636 = mux(T_1465, UInt<1>(1), T_1635) - node T_1637 = mux(T_1463, UInt<1>(1), T_1636) - node T_1638 = mux(T_1461, UInt<1>(1), T_1637) - node T_1639 = mux(T_1459, UInt<1>(1), T_1638) - node T_1640 = mux(T_1457, UInt<1>(1), T_1639) - node T_1641 = mux(T_1455, UInt<1>(1), T_1640) - node T_1642 = mux(T_1453, UInt<1>(1), T_1641) - node T_1643 = mux(T_1451, UInt<1>(1), T_1642) - node T_1644 = mux(T_1449, UInt<1>(1), T_1643) - node T_1645 = mux(T_1447, UInt<1>(1), T_1644) - node T_1646 = mux(T_1445, UInt<1>(1), T_1645) - node T_1647 = mux(T_1443, UInt<1>(1), T_1646) - node T_1648 = mux(T_1441, UInt<1>(1), T_1647) - node T_1649 = mux(T_1439, UInt<1>(1), T_1648) - node T_1650 = mux(T_1437, UInt<1>(1), T_1649) - node T_1651 = mux(T_1521, UInt<3>(5), UInt<3>(7)) - node T_1652 = mux(T_1519, UInt<3>(5), T_1651) - node T_1653 = mux(T_1517, UInt<3>(5), T_1652) - node T_1654 = mux(T_1515, UInt<3>(5), T_1653) - node T_1655 = mux(T_1513, UInt<3>(5), T_1654) - node T_1656 = mux(T_1511, UInt<3>(5), T_1655) - node T_1657 = mux(T_1509, UInt<3>(7), T_1656) - node T_1658 = mux(T_1507, UInt<3>(7), T_1657) - node T_1659 = mux(T_1505, UInt<3>(7), T_1658) - node T_1660 = mux(T_1503, UInt<3>(7), T_1659) - node T_1661 = mux(T_1501, UInt<3>(7), T_1660) - node T_1662 = mux(T_1499, UInt<3>(7), T_1661) - node T_1663 = mux(T_1497, UInt<3>(7), T_1662) - node T_1664 = mux(T_1495, UInt<3>(7), T_1663) - node T_1665 = mux(T_1493, UInt<3>(7), T_1664) - node T_1666 = mux(T_1491, UInt<3>(7), T_1665) - node T_1667 = mux(T_1489, UInt<3>(0), T_1666) - node T_1668 = mux(T_1487, UInt<3>(0), T_1667) - node T_1669 = mux(T_1485, UInt<3>(0), T_1668) - node T_1670 = mux(T_1483, UInt<3>(0), T_1669) - node T_1671 = mux(T_1481, UInt<3>(0), T_1670) - node T_1672 = mux(T_1479, UInt<3>(0), T_1671) - node T_1673 = mux(T_1477, UInt<3>(0), T_1672) - node T_1674 = mux(T_1475, UInt<3>(0), T_1673) - node T_1675 = mux(T_1473, UInt<3>(0), T_1674) - node T_1676 = mux(T_1471, UInt<3>(1), T_1675) - node T_1677 = mux(T_1469, UInt<3>(1), T_1676) - node T_1678 = mux(T_1467, UInt<3>(1), T_1677) - node T_1679 = mux(T_1465, UInt<3>(0), T_1678) - node T_1680 = mux(T_1463, UInt<3>(0), T_1679) - node T_1681 = mux(T_1461, UInt<3>(0), T_1680) - node T_1682 = mux(T_1459, UInt<3>(0), T_1681) - node T_1683 = mux(T_1457, UInt<3>(0), T_1682) - node T_1684 = mux(T_1455, UInt<3>(4), T_1683) - node T_1685 = mux(T_1453, UInt<3>(4), T_1684) - node T_1686 = mux(T_1451, UInt<3>(4), T_1685) - node T_1687 = mux(T_1449, UInt<3>(4), T_1686) - node T_1688 = mux(T_1447, UInt<3>(4), T_1687) - node T_1689 = mux(T_1445, UInt<3>(4), T_1688) - node T_1690 = mux(T_1443, UInt<3>(0), T_1689) - node T_1691 = mux(T_1441, UInt<3>(3), T_1690) - node T_1692 = mux(T_1439, UInt<3>(2), T_1691) - node T_1693 = mux(T_1437, UInt<3>(2), T_1692) - node T_1694 = mux(T_1521, UInt<4>(11), UInt<4>(15)) - node T_1695 = mux(T_1519, UInt<4>(11), T_1694) - node T_1696 = mux(T_1517, UInt<4>(11), T_1695) - node T_1697 = mux(T_1515, UInt<4>(10), T_1696) - node T_1698 = mux(T_1513, UInt<4>(10), T_1697) - node T_1699 = mux(T_1511, UInt<4>(10), T_1698) - node T_1700 = mux(T_1509, UInt<4>(2), T_1699) - node T_1701 = mux(T_1507, UInt<4>(3), T_1700) - node T_1702 = mux(T_1505, UInt<4>(9), T_1701) - node T_1703 = mux(T_1503, UInt<4>(8), T_1702) - node T_1704 = mux(T_1501, UInt<4>(4), T_1703) - node T_1705 = mux(T_1499, UInt<4>(7), T_1704) - node T_1706 = mux(T_1497, UInt<4>(5), T_1705) - node T_1707 = mux(T_1495, UInt<4>(6), T_1706) - node T_1708 = mux(T_1493, UInt<4>(1), T_1707) - node T_1709 = mux(T_1491, UInt<4>(0), T_1708) - node T_1710 = mux(T_1489, UInt<4>(9), T_1709) - node T_1711 = mux(T_1487, UInt<4>(8), T_1710) - node T_1712 = mux(T_1485, UInt<4>(6), T_1711) - node T_1713 = mux(T_1483, UInt<4>(2), T_1712) - node T_1714 = mux(T_1481, UInt<4>(3), T_1713) - node T_1715 = mux(T_1479, UInt<4>(4), T_1714) - node T_1716 = mux(T_1477, UInt<4>(7), T_1715) - node T_1717 = mux(T_1475, UInt<4>(5), T_1716) - node T_1718 = mux(T_1473, UInt<4>(0), T_1717) - node T_1719 = mux(T_1471, UInt<4>(0), T_1718) - node T_1720 = mux(T_1469, UInt<4>(0), T_1719) - node T_1721 = mux(T_1467, UInt<4>(0), T_1720) - node T_1722 = mux(T_1465, UInt<4>(0), T_1721) - node T_1723 = mux(T_1463, UInt<4>(0), T_1722) - node T_1724 = mux(T_1461, UInt<4>(0), T_1723) - node T_1725 = mux(T_1459, UInt<4>(0), T_1724) - node T_1726 = mux(T_1457, UInt<4>(0), T_1725) - node T_1727 = mux(T_1455, UInt<4>(0), T_1726) - node T_1728 = mux(T_1453, UInt<4>(0), T_1727) - node T_1729 = mux(T_1451, UInt<4>(0), T_1728) - node T_1730 = mux(T_1449, UInt<4>(0), T_1729) - node T_1731 = mux(T_1447, UInt<4>(0), T_1730) - node T_1732 = mux(T_1445, UInt<4>(0), T_1731) - node T_1733 = mux(T_1443, UInt<4>(0), T_1732) - node T_1734 = mux(T_1441, UInt<4>(0), T_1733) - node T_1735 = mux(T_1439, UInt<4>(0), T_1734) - node T_1736 = mux(T_1437, UInt<4>(11), T_1735) - node T_1737 = mux(T_1521, UInt<3>(7), UInt<3>(7)) - node T_1738 = mux(T_1519, UInt<3>(7), T_1737) - node T_1739 = mux(T_1517, UInt<3>(7), T_1738) - node T_1740 = mux(T_1515, UInt<3>(7), T_1739) - node T_1741 = mux(T_1513, UInt<3>(7), T_1740) - node T_1742 = mux(T_1511, UInt<3>(7), T_1741) - node T_1743 = mux(T_1509, UInt<3>(7), T_1742) - node T_1744 = mux(T_1507, UInt<3>(7), T_1743) - node T_1745 = mux(T_1505, UInt<3>(7), T_1744) - node T_1746 = mux(T_1503, UInt<3>(7), T_1745) - node T_1747 = mux(T_1501, UInt<3>(7), T_1746) - node T_1748 = mux(T_1499, UInt<3>(7), T_1747) - node T_1749 = mux(T_1497, UInt<3>(7), T_1748) - node T_1750 = mux(T_1495, UInt<3>(7), T_1749) - node T_1751 = mux(T_1493, UInt<3>(7), T_1750) - node T_1752 = mux(T_1491, UInt<3>(7), T_1751) - node T_1753 = mux(T_1489, UInt<3>(7), T_1752) - node T_1754 = mux(T_1487, UInt<3>(7), T_1753) - node T_1755 = mux(T_1485, UInt<3>(7), T_1754) - node T_1756 = mux(T_1483, UInt<3>(7), T_1755) - node T_1757 = mux(T_1481, UInt<3>(7), T_1756) - node T_1758 = mux(T_1479, UInt<3>(7), T_1757) - node T_1759 = mux(T_1477, UInt<3>(7), T_1758) - node T_1760 = mux(T_1475, UInt<3>(7), T_1759) - node T_1761 = mux(T_1473, UInt<3>(7), T_1760) - node T_1762 = mux(T_1471, UInt<3>(7), T_1761) - node T_1763 = mux(T_1469, UInt<3>(7), T_1762) - node T_1764 = mux(T_1467, UInt<3>(7), T_1763) - node T_1765 = mux(T_1465, UInt<3>(7), T_1764) - node T_1766 = mux(T_1463, UInt<3>(7), T_1765) - node T_1767 = mux(T_1461, UInt<3>(7), T_1766) - node T_1768 = mux(T_1459, UInt<3>(7), T_1767) - node T_1769 = mux(T_1457, UInt<3>(7), T_1768) - node T_1770 = mux(T_1455, UInt<3>(4), T_1769) - node T_1771 = mux(T_1453, UInt<3>(0), T_1770) - node T_1772 = mux(T_1451, UInt<3>(5), T_1771) - node T_1773 = mux(T_1449, UInt<3>(1), T_1772) - node T_1774 = mux(T_1447, UInt<3>(6), T_1773) - node T_1775 = mux(T_1445, UInt<3>(2), T_1774) - node T_1776 = mux(T_1443, UInt<3>(7), T_1775) - node T_1777 = mux(T_1441, UInt<3>(7), T_1776) - node T_1778 = mux(T_1439, UInt<3>(7), T_1777) - node T_1779 = mux(T_1437, UInt<3>(7), T_1778) - node T_1780 = mux(T_1521, UInt<1>(0), UInt<1>(0)) - node T_1781 = mux(T_1519, UInt<1>(0), T_1780) - node T_1782 = mux(T_1517, UInt<1>(0), T_1781) - node T_1783 = mux(T_1515, UInt<1>(0), T_1782) - node T_1784 = mux(T_1513, UInt<1>(0), T_1783) - node T_1785 = mux(T_1511, UInt<1>(0), T_1784) - node T_1786 = mux(T_1509, UInt<1>(0), T_1785) - node T_1787 = mux(T_1507, UInt<1>(0), T_1786) - node T_1788 = mux(T_1505, UInt<1>(0), T_1787) - node T_1789 = mux(T_1503, UInt<1>(0), T_1788) - node T_1790 = mux(T_1501, UInt<1>(0), T_1789) - node T_1791 = mux(T_1499, UInt<1>(0), T_1790) - node T_1792 = mux(T_1497, UInt<1>(0), T_1791) - node T_1793 = mux(T_1495, UInt<1>(0), T_1792) - node T_1794 = mux(T_1493, UInt<1>(0), T_1793) - node T_1795 = mux(T_1491, UInt<1>(0), T_1794) - node T_1796 = mux(T_1489, UInt<1>(0), T_1795) - node T_1797 = mux(T_1487, UInt<1>(0), T_1796) - node T_1798 = mux(T_1485, UInt<1>(0), T_1797) - node T_1799 = mux(T_1483, UInt<1>(0), T_1798) - node T_1800 = mux(T_1481, UInt<1>(0), T_1799) - node T_1801 = mux(T_1479, UInt<1>(0), T_1800) - node T_1802 = mux(T_1477, UInt<1>(0), T_1801) - node T_1803 = mux(T_1475, UInt<1>(0), T_1802) - node T_1804 = mux(T_1473, UInt<1>(0), T_1803) - node T_1805 = mux(T_1471, UInt<1>(0), T_1804) - node T_1806 = mux(T_1469, UInt<1>(0), T_1805) - node T_1807 = mux(T_1467, UInt<1>(0), T_1806) - node T_1808 = mux(T_1465, UInt<1>(0), T_1807) - node T_1809 = mux(T_1463, UInt<1>(0), T_1808) - node T_1810 = mux(T_1461, UInt<1>(0), T_1809) - node T_1811 = mux(T_1459, UInt<1>(0), T_1810) - node T_1812 = mux(T_1457, UInt<1>(0), T_1811) - node T_1813 = mux(T_1455, UInt<1>(0), T_1812) - node T_1814 = mux(T_1453, UInt<1>(0), T_1813) - node T_1815 = mux(T_1451, UInt<1>(0), T_1814) - node T_1816 = mux(T_1449, UInt<1>(0), T_1815) - node T_1817 = mux(T_1447, UInt<1>(0), T_1816) - node T_1818 = mux(T_1445, UInt<1>(0), T_1817) - node T_1819 = mux(T_1443, UInt<1>(1), T_1818) - node T_1820 = mux(T_1441, UInt<1>(1), T_1819) - node T_1821 = mux(T_1439, UInt<1>(0), T_1820) - node T_1822 = mux(T_1437, UInt<1>(0), T_1821) - node T_1823 = mux(T_1521, UInt<2>(3), UInt<2>(3)) - node T_1824 = mux(T_1519, UInt<2>(3), T_1823) - node T_1825 = mux(T_1517, UInt<2>(3), T_1824) - node T_1826 = mux(T_1515, UInt<2>(3), T_1825) - node T_1827 = mux(T_1513, UInt<2>(3), T_1826) - node T_1828 = mux(T_1511, UInt<2>(3), T_1827) - node T_1829 = mux(T_1509, UInt<2>(3), T_1828) - node T_1830 = mux(T_1507, UInt<2>(3), T_1829) - node T_1831 = mux(T_1505, UInt<2>(3), T_1830) - node T_1832 = mux(T_1503, UInt<2>(3), T_1831) - node T_1833 = mux(T_1501, UInt<2>(3), T_1832) - node T_1834 = mux(T_1499, UInt<2>(3), T_1833) - node T_1835 = mux(T_1497, UInt<2>(3), T_1834) - node T_1836 = mux(T_1495, UInt<2>(3), T_1835) - node T_1837 = mux(T_1493, UInt<2>(3), T_1836) - node T_1838 = mux(T_1491, UInt<2>(3), T_1837) - node T_1839 = mux(T_1489, UInt<2>(3), T_1838) - node T_1840 = mux(T_1487, UInt<2>(3), T_1839) - node T_1841 = mux(T_1485, UInt<2>(3), T_1840) - node T_1842 = mux(T_1483, UInt<2>(3), T_1841) - node T_1843 = mux(T_1481, UInt<2>(3), T_1842) - node T_1844 = mux(T_1479, UInt<2>(3), T_1843) - node T_1845 = mux(T_1477, UInt<2>(3), T_1844) - node T_1846 = mux(T_1475, UInt<2>(3), T_1845) - node T_1847 = mux(T_1473, UInt<2>(3), T_1846) - node T_1848 = mux(T_1471, UInt<2>(0), T_1847) - node T_1849 = mux(T_1469, UInt<2>(1), T_1848) - node T_1850 = mux(T_1467, UInt<2>(2), T_1849) - node T_1851 = mux(T_1465, UInt<2>(3), T_1850) - node T_1852 = mux(T_1463, UInt<2>(3), T_1851) - node T_1853 = mux(T_1461, UInt<2>(3), T_1852) - node T_1854 = mux(T_1459, UInt<2>(3), T_1853) - node T_1855 = mux(T_1457, UInt<2>(3), T_1854) - node T_1856 = mux(T_1455, UInt<2>(3), T_1855) - node T_1857 = mux(T_1453, UInt<2>(3), T_1856) - node T_1858 = mux(T_1451, UInt<2>(3), T_1857) - node T_1859 = mux(T_1449, UInt<2>(3), T_1858) - node T_1860 = mux(T_1447, UInt<2>(3), T_1859) - node T_1861 = mux(T_1445, UInt<2>(3), T_1860) - node T_1862 = mux(T_1443, UInt<2>(3), T_1861) - node T_1863 = mux(T_1441, UInt<2>(3), T_1862) - node T_1864 = mux(T_1439, UInt<2>(3), T_1863) - node T_1865 = mux(T_1437, UInt<2>(3), T_1864) - node T_1866 = mux(T_1521, UInt<3>(7), UInt<3>(7)) - node T_1867 = mux(T_1519, UInt<3>(7), T_1866) - node T_1868 = mux(T_1517, UInt<3>(7), T_1867) - node T_1869 = mux(T_1515, UInt<3>(7), T_1868) - node T_1870 = mux(T_1513, UInt<3>(7), T_1869) - node T_1871 = mux(T_1511, UInt<3>(7), T_1870) - node T_1872 = mux(T_1509, UInt<3>(7), T_1871) - node T_1873 = mux(T_1507, UInt<3>(7), T_1872) - node T_1874 = mux(T_1505, UInt<3>(7), T_1873) - node T_1875 = mux(T_1503, UInt<3>(7), T_1874) - node T_1876 = mux(T_1501, UInt<3>(7), T_1875) - node T_1877 = mux(T_1499, UInt<3>(7), T_1876) - node T_1878 = mux(T_1497, UInt<3>(7), T_1877) - node T_1879 = mux(T_1495, UInt<3>(7), T_1878) - node T_1880 = mux(T_1493, UInt<3>(7), T_1879) - node T_1881 = mux(T_1491, UInt<3>(7), T_1880) - node T_1882 = mux(T_1489, UInt<3>(7), T_1881) - node T_1883 = mux(T_1487, UInt<3>(7), T_1882) - node T_1884 = mux(T_1485, UInt<3>(7), T_1883) - node T_1885 = mux(T_1483, UInt<3>(7), T_1884) - node T_1886 = mux(T_1481, UInt<3>(7), T_1885) - node T_1887 = mux(T_1479, UInt<3>(7), T_1886) - node T_1888 = mux(T_1477, UInt<3>(7), T_1887) - node T_1889 = mux(T_1475, UInt<3>(7), T_1888) - node T_1890 = mux(T_1473, UInt<3>(7), T_1889) - node T_1891 = mux(T_1471, UInt<3>(7), T_1890) - node T_1892 = mux(T_1469, UInt<3>(7), T_1891) - node T_1893 = mux(T_1467, UInt<3>(7), T_1892) - node T_1894 = mux(T_1465, UInt<3>(3), T_1893) - node T_1895 = mux(T_1463, UInt<3>(4), T_1894) - node T_1896 = mux(T_1461, UInt<3>(0), T_1895) - node T_1897 = mux(T_1459, UInt<3>(1), T_1896) - node T_1898 = mux(T_1457, UInt<3>(2), T_1897) - node T_1899 = mux(T_1455, UInt<3>(7), T_1898) - node T_1900 = mux(T_1453, UInt<3>(7), T_1899) - node T_1901 = mux(T_1451, UInt<3>(7), T_1900) - node T_1902 = mux(T_1449, UInt<3>(7), T_1901) - node T_1903 = mux(T_1447, UInt<3>(7), T_1902) - node T_1904 = mux(T_1445, UInt<3>(7), T_1903) - node T_1905 = mux(T_1443, UInt<3>(7), T_1904) - node T_1906 = mux(T_1441, UInt<3>(7), T_1905) - node T_1907 = mux(T_1439, UInt<3>(7), T_1906) - node T_1908 = mux(T_1437, UInt<3>(7), T_1907) - node T_1909 = mux(T_1521, UInt<2>(3), UInt<2>(0)) - node T_1910 = mux(T_1519, UInt<2>(3), T_1909) - node T_1911 = mux(T_1517, UInt<2>(3), T_1910) - node T_1912 = mux(T_1515, UInt<2>(3), T_1911) - node T_1913 = mux(T_1513, UInt<2>(3), T_1912) - node T_1914 = mux(T_1511, UInt<2>(3), T_1913) - node T_1915 = mux(T_1509, UInt<2>(0), T_1914) - node T_1916 = mux(T_1507, UInt<2>(0), T_1915) - node T_1917 = mux(T_1505, UInt<2>(0), T_1916) - node T_1918 = mux(T_1503, UInt<2>(0), T_1917) - node T_1919 = mux(T_1501, UInt<2>(0), T_1918) - node T_1920 = mux(T_1499, UInt<2>(0), T_1919) - node T_1921 = mux(T_1497, UInt<2>(0), T_1920) - node T_1922 = mux(T_1495, UInt<2>(0), T_1921) - node T_1923 = mux(T_1493, UInt<2>(0), T_1922) - node T_1924 = mux(T_1491, UInt<2>(0), T_1923) - node T_1925 = mux(T_1489, UInt<2>(0), T_1924) - node T_1926 = mux(T_1487, UInt<2>(0), T_1925) - node T_1927 = mux(T_1485, UInt<2>(0), T_1926) - node T_1928 = mux(T_1483, UInt<2>(0), T_1927) - node T_1929 = mux(T_1481, UInt<2>(0), T_1928) - node T_1930 = mux(T_1479, UInt<2>(0), T_1929) - node T_1931 = mux(T_1477, UInt<2>(0), T_1930) - node T_1932 = mux(T_1475, UInt<2>(0), T_1931) - node T_1933 = mux(T_1473, UInt<2>(0), T_1932) - node T_1934 = mux(T_1471, UInt<2>(0), T_1933) - node T_1935 = mux(T_1469, UInt<2>(0), T_1934) - node T_1936 = mux(T_1467, UInt<2>(0), T_1935) - node T_1937 = mux(T_1465, UInt<2>(1), T_1936) - node T_1938 = mux(T_1463, UInt<2>(1), T_1937) - node T_1939 = mux(T_1461, UInt<2>(1), T_1938) - node T_1940 = mux(T_1459, UInt<2>(1), T_1939) - node T_1941 = mux(T_1457, UInt<2>(1), T_1940) - node T_1942 = mux(T_1455, UInt<2>(0), T_1941) - node T_1943 = mux(T_1453, UInt<2>(0), T_1942) - node T_1944 = mux(T_1451, UInt<2>(0), T_1943) - node T_1945 = mux(T_1449, UInt<2>(0), T_1944) - node T_1946 = mux(T_1447, UInt<2>(0), T_1945) - node T_1947 = mux(T_1445, UInt<2>(0), T_1946) - node T_1948 = mux(T_1443, UInt<2>(2), T_1947) - node T_1949 = mux(T_1441, UInt<2>(2), T_1948) - node T_1950 = mux(T_1439, UInt<2>(0), T_1949) - node T_1951 = mux(T_1437, UInt<2>(0), T_1950) - node T_1952 = mux(T_1521, UInt<1>(0), UInt<1>(0)) - node T_1953 = mux(T_1519, UInt<1>(0), T_1952) - node T_1954 = mux(T_1517, UInt<1>(0), T_1953) - node T_1955 = mux(T_1515, UInt<1>(0), T_1954) - node T_1956 = mux(T_1513, UInt<1>(0), T_1955) - node T_1957 = mux(T_1511, UInt<1>(0), T_1956) - node T_1958 = mux(T_1509, UInt<1>(1), T_1957) - node T_1959 = mux(T_1507, UInt<1>(1), T_1958) - node T_1960 = mux(T_1505, UInt<1>(1), T_1959) - node T_1961 = mux(T_1503, UInt<1>(1), T_1960) - node T_1962 = mux(T_1501, UInt<1>(1), T_1961) - node T_1963 = mux(T_1499, UInt<1>(1), T_1962) - node T_1964 = mux(T_1497, UInt<1>(1), T_1963) - node T_1965 = mux(T_1495, UInt<1>(1), T_1964) - node T_1966 = mux(T_1493, UInt<1>(1), T_1965) - node T_1967 = mux(T_1491, UInt<1>(1), T_1966) - node T_1968 = mux(T_1489, UInt<1>(1), T_1967) - node T_1969 = mux(T_1487, UInt<1>(1), T_1968) - node T_1970 = mux(T_1485, UInt<1>(1), T_1969) - node T_1971 = mux(T_1483, UInt<1>(1), T_1970) - node T_1972 = mux(T_1481, UInt<1>(1), T_1971) - node T_1973 = mux(T_1479, UInt<1>(1), T_1972) - node T_1974 = mux(T_1477, UInt<1>(1), T_1973) - node T_1975 = mux(T_1475, UInt<1>(1), T_1974) - node T_1976 = mux(T_1473, UInt<1>(1), T_1975) - node T_1977 = mux(T_1471, UInt<1>(0), T_1976) - node T_1978 = mux(T_1469, UInt<1>(0), T_1977) - node T_1979 = mux(T_1467, UInt<1>(0), T_1978) - node T_1980 = mux(T_1465, UInt<1>(1), T_1979) - node T_1981 = mux(T_1463, UInt<1>(1), T_1980) - node T_1982 = mux(T_1461, UInt<1>(1), T_1981) - node T_1983 = mux(T_1459, UInt<1>(1), T_1982) - node T_1984 = mux(T_1457, UInt<1>(1), T_1983) - node T_1985 = mux(T_1455, UInt<1>(0), T_1984) - node T_1986 = mux(T_1453, UInt<1>(0), T_1985) - node T_1987 = mux(T_1451, UInt<1>(0), T_1986) - node T_1988 = mux(T_1449, UInt<1>(0), T_1987) - node T_1989 = mux(T_1447, UInt<1>(0), T_1988) - node T_1990 = mux(T_1445, UInt<1>(0), T_1989) - node T_1991 = mux(T_1443, UInt<1>(1), T_1990) - node T_1992 = mux(T_1441, UInt<1>(1), T_1991) - node T_1993 = mux(T_1439, UInt<1>(1), T_1992) - node T_1994 = mux(T_1437, UInt<1>(1), T_1993) - node T_1995 = mux(T_1521, UInt<2>(3), UInt<2>(0)) - node T_1996 = mux(T_1519, UInt<2>(2), T_1995) - node T_1997 = mux(T_1517, UInt<2>(1), T_1996) - node T_1998 = mux(T_1515, UInt<2>(3), T_1997) - node T_1999 = mux(T_1513, UInt<2>(2), T_1998) - node T_2000 = mux(T_1511, UInt<2>(1), T_1999) - node T_2001 = mux(T_1509, UInt<2>(0), T_2000) - node T_2002 = mux(T_1507, UInt<2>(0), T_2001) - node T_2003 = mux(T_1505, UInt<2>(0), T_2002) - node T_2004 = mux(T_1503, UInt<2>(0), T_2003) - node T_2005 = mux(T_1501, UInt<2>(0), T_2004) - node T_2006 = mux(T_1499, UInt<2>(0), T_2005) - node T_2007 = mux(T_1497, UInt<2>(0), T_2006) - node T_2008 = mux(T_1495, UInt<2>(0), T_2007) - node T_2009 = mux(T_1493, UInt<2>(0), T_2008) - node T_2010 = mux(T_1491, UInt<2>(0), T_2009) - node T_2011 = mux(T_1489, UInt<2>(0), T_2010) - node T_2012 = mux(T_1487, UInt<2>(0), T_2011) - node T_2013 = mux(T_1485, UInt<2>(0), T_2012) - node T_2014 = mux(T_1483, UInt<2>(0), T_2013) - node T_2015 = mux(T_1481, UInt<2>(0), T_2014) - node T_2016 = mux(T_1479, UInt<2>(0), T_2015) - node T_2017 = mux(T_1477, UInt<2>(0), T_2016) - node T_2018 = mux(T_1475, UInt<2>(0), T_2017) - node T_2019 = mux(T_1473, UInt<2>(0), T_2018) - node T_2020 = mux(T_1471, UInt<2>(0), T_2019) - node T_2021 = mux(T_1469, UInt<2>(0), T_2020) - node T_2022 = mux(T_1467, UInt<2>(0), T_2021) - node T_2023 = mux(T_1465, UInt<2>(0), T_2022) - node T_2024 = mux(T_1463, UInt<2>(0), T_2023) - node T_2025 = mux(T_1461, UInt<2>(0), T_2024) - node T_2026 = mux(T_1459, UInt<2>(0), T_2025) - node T_2027 = mux(T_1457, UInt<2>(0), T_2026) - node T_2028 = mux(T_1455, UInt<2>(0), T_2027) - node T_2029 = mux(T_1453, UInt<2>(0), T_2028) - node T_2030 = mux(T_1451, UInt<2>(0), T_2029) - node T_2031 = mux(T_1449, UInt<2>(0), T_2030) - node T_2032 = mux(T_1447, UInt<2>(0), T_2031) - node T_2033 = mux(T_1445, UInt<2>(0), T_2032) - node T_2034 = mux(T_1443, UInt<2>(0), T_2033) - node T_2035 = mux(T_1441, UInt<2>(0), T_2034) - node T_2036 = mux(T_1439, UInt<2>(0), T_2035) - node T_2037 = mux(T_1437, UInt<2>(0), T_2036) + node T_831 = and(UInt<7>(127), ctrl.inst) + node T_832 = eq(T_831, UInt<6>(55)) + node T_833 = and(UInt<7>(127), ctrl.inst) + node T_834 = eq(T_833, UInt<5>(23)) + node T_835 = and(UInt<7>(127), ctrl.inst) + node T_836 = eq(T_835, UInt<7>(111)) + node T_837 = and(UInt<15>(28799), ctrl.inst) + node T_838 = eq(T_837, UInt<7>(103)) + node T_839 = and(UInt<15>(28799), ctrl.inst) + node T_840 = eq(T_839, UInt<7>(99)) + node T_841 = and(UInt<15>(28799), ctrl.inst) + node T_842 = eq(T_841, UInt<13>(4195)) + node T_843 = and(UInt<15>(28799), ctrl.inst) + node T_844 = eq(T_843, UInt<15>(16483)) + node T_845 = and(UInt<15>(28799), ctrl.inst) + node T_846 = eq(T_845, UInt<15>(20579)) + node T_847 = and(UInt<15>(28799), ctrl.inst) + node T_848 = eq(T_847, UInt<15>(24675)) + node T_849 = and(UInt<15>(28799), ctrl.inst) + node T_850 = eq(T_849, UInt<15>(28771)) + node T_851 = and(UInt<15>(28799), ctrl.inst) + node T_852 = eq(T_851, UInt<2>(3)) + node T_853 = and(UInt<15>(28799), ctrl.inst) + node T_854 = eq(T_853, UInt<13>(4099)) + node T_855 = and(UInt<15>(28799), ctrl.inst) + node T_856 = eq(T_855, UInt<14>(8195)) + node T_857 = and(UInt<15>(28799), ctrl.inst) + node T_858 = eq(T_857, UInt<15>(16387)) + node T_859 = and(UInt<15>(28799), ctrl.inst) + node T_860 = eq(T_859, UInt<15>(20483)) + node T_861 = and(UInt<15>(28799), ctrl.inst) + node T_862 = eq(T_861, UInt<6>(35)) + node T_863 = and(UInt<15>(28799), ctrl.inst) + node T_864 = eq(T_863, UInt<13>(4131)) + node T_865 = and(UInt<15>(28799), ctrl.inst) + node T_866 = eq(T_865, UInt<14>(8227)) + node T_867 = and(UInt<15>(28799), ctrl.inst) + node T_868 = eq(T_867, UInt<5>(19)) + node T_869 = and(UInt<15>(28799), ctrl.inst) + node T_870 = eq(T_869, UInt<14>(8211)) + node T_871 = and(UInt<15>(28799), ctrl.inst) + node T_872 = eq(T_871, UInt<14>(12307)) + node T_873 = and(UInt<15>(28799), ctrl.inst) + node T_874 = eq(T_873, UInt<15>(16403)) + node T_875 = and(UInt<15>(28799), ctrl.inst) + node T_876 = eq(T_875, UInt<15>(24595)) + node T_877 = and(UInt<15>(28799), ctrl.inst) + node T_878 = eq(T_877, UInt<15>(28691)) + node T_879 = and(UInt<32>(4261441663), ctrl.inst) + node T_880 = eq(T_879, UInt<13>(4115)) + node T_881 = and(UInt<32>(4261441663), ctrl.inst) + node T_882 = eq(T_881, UInt<15>(20499)) + node T_883 = and(UInt<32>(4261441663), ctrl.inst) + node T_884 = eq(T_883, UInt<31>(1073762323)) + node T_885 = and(UInt<32>(4261441663), ctrl.inst) + node T_886 = eq(T_885, UInt<6>(51)) + node T_887 = and(UInt<32>(4261441663), ctrl.inst) + node T_888 = eq(T_887, UInt<31>(1073741875)) + node T_889 = and(UInt<32>(4261441663), ctrl.inst) + node T_890 = eq(T_889, UInt<13>(4147)) + node T_891 = and(UInt<32>(4261441663), ctrl.inst) + node T_892 = eq(T_891, UInt<14>(8243)) + node T_893 = and(UInt<32>(4261441663), ctrl.inst) + node T_894 = eq(T_893, UInt<14>(12339)) + node T_895 = and(UInt<32>(4261441663), ctrl.inst) + node T_896 = eq(T_895, UInt<15>(16435)) + node T_897 = and(UInt<32>(4261441663), ctrl.inst) + node T_898 = eq(T_897, UInt<15>(20531)) + node T_899 = and(UInt<32>(4261441663), ctrl.inst) + node T_900 = eq(T_899, UInt<31>(1073762355)) + node T_901 = and(UInt<32>(4261441663), ctrl.inst) + node T_902 = eq(T_901, UInt<15>(24627)) + node T_903 = and(UInt<32>(4261441663), ctrl.inst) + node T_904 = eq(T_903, UInt<15>(28723)) + node T_905 = and(UInt<15>(28799), ctrl.inst) + node T_906 = eq(T_905, UInt<13>(4211)) + node T_907 = and(UInt<15>(28799), ctrl.inst) + node T_908 = eq(T_907, UInt<14>(8307)) + node T_909 = and(UInt<15>(28799), ctrl.inst) + node T_910 = eq(T_909, UInt<14>(12403)) + node T_911 = and(UInt<15>(28799), ctrl.inst) + node T_912 = eq(T_911, UInt<15>(20595)) + node T_913 = and(UInt<15>(28799), ctrl.inst) + node T_914 = eq(T_913, UInt<15>(24691)) + node T_915 = and(UInt<15>(28799), ctrl.inst) + node T_916 = eq(T_915, UInt<15>(28787)) + node T_917 = mux(T_916, UInt<1>(0), UInt<1>(0)) + node T_918 = mux(T_914, UInt<1>(0), T_917) + node T_919 = mux(T_912, UInt<1>(0), T_918) + node T_920 = mux(T_910, UInt<1>(0), T_919) + node T_921 = mux(T_908, UInt<1>(0), T_920) + node T_922 = mux(T_906, UInt<1>(0), T_921) + node T_923 = mux(T_904, UInt<1>(0), T_922) + node T_924 = mux(T_902, UInt<1>(0), T_923) + node T_925 = mux(T_900, UInt<1>(0), T_924) + node T_926 = mux(T_898, UInt<1>(0), T_925) + node T_927 = mux(T_896, UInt<1>(0), T_926) + node T_928 = mux(T_894, UInt<1>(0), T_927) + node T_929 = mux(T_892, UInt<1>(0), T_928) + node T_930 = mux(T_890, UInt<1>(0), T_929) + node T_931 = mux(T_888, UInt<1>(0), T_930) + node T_932 = mux(T_886, UInt<1>(0), T_931) + node T_933 = mux(T_884, UInt<1>(0), T_932) + node T_934 = mux(T_882, UInt<1>(0), T_933) + node T_935 = mux(T_880, UInt<1>(0), T_934) + node T_936 = mux(T_878, UInt<1>(0), T_935) + node T_937 = mux(T_876, UInt<1>(0), T_936) + node T_938 = mux(T_874, UInt<1>(0), T_937) + node T_939 = mux(T_872, UInt<1>(0), T_938) + node T_940 = mux(T_870, UInt<1>(0), T_939) + node T_941 = mux(T_868, UInt<1>(0), T_940) + node T_942 = mux(T_866, UInt<1>(0), T_941) + node T_943 = mux(T_864, UInt<1>(0), T_942) + node T_944 = mux(T_862, UInt<1>(0), T_943) + node T_945 = mux(T_860, UInt<1>(0), T_944) + node T_946 = mux(T_858, UInt<1>(0), T_945) + node T_947 = mux(T_856, UInt<1>(0), T_946) + node T_948 = mux(T_854, UInt<1>(0), T_947) + node T_949 = mux(T_852, UInt<1>(0), T_948) + node T_950 = mux(T_850, UInt<1>(0), T_949) + node T_951 = mux(T_848, UInt<1>(0), T_950) + node T_952 = mux(T_846, UInt<1>(0), T_951) + node T_953 = mux(T_844, UInt<1>(0), T_952) + node T_954 = mux(T_842, UInt<1>(0), T_953) + node T_955 = mux(T_840, UInt<1>(0), T_954) + node T_956 = mux(T_838, UInt<1>(1), T_955) + node T_957 = mux(T_836, UInt<1>(1), T_956) + node T_958 = mux(T_834, UInt<1>(0), T_957) + node T_959 = mux(T_832, UInt<1>(0), T_958) + node T_960 = mux(T_916, UInt<1>(1), UInt<1>(1)) + node T_961 = mux(T_914, UInt<1>(1), T_960) + node T_962 = mux(T_912, UInt<1>(1), T_961) + node T_963 = mux(T_910, UInt<1>(0), T_962) + node T_964 = mux(T_908, UInt<1>(0), T_963) + node T_965 = mux(T_906, UInt<1>(0), T_964) + node T_966 = mux(T_904, UInt<1>(0), T_965) + node T_967 = mux(T_902, UInt<1>(0), T_966) + node T_968 = mux(T_900, UInt<1>(0), T_967) + node T_969 = mux(T_898, UInt<1>(0), T_968) + node T_970 = mux(T_896, UInt<1>(0), T_969) + node T_971 = mux(T_894, UInt<1>(0), T_970) + node T_972 = mux(T_892, UInt<1>(0), T_971) + node T_973 = mux(T_890, UInt<1>(0), T_972) + node T_974 = mux(T_888, UInt<1>(0), T_973) + node T_975 = mux(T_886, UInt<1>(0), T_974) + node T_976 = mux(T_884, UInt<1>(0), T_975) + node T_977 = mux(T_882, UInt<1>(0), T_976) + node T_978 = mux(T_880, UInt<1>(0), T_977) + node T_979 = mux(T_878, UInt<1>(0), T_978) + node T_980 = mux(T_876, UInt<1>(0), T_979) + node T_981 = mux(T_874, UInt<1>(0), T_980) + node T_982 = mux(T_872, UInt<1>(0), T_981) + node T_983 = mux(T_870, UInt<1>(0), T_982) + node T_984 = mux(T_868, UInt<1>(0), T_983) + node T_985 = mux(T_866, UInt<1>(0), T_984) + node T_986 = mux(T_864, UInt<1>(0), T_985) + node T_987 = mux(T_862, UInt<1>(0), T_986) + node T_988 = mux(T_860, UInt<1>(0), T_987) + node T_989 = mux(T_858, UInt<1>(0), T_988) + node T_990 = mux(T_856, UInt<1>(0), T_989) + node T_991 = mux(T_854, UInt<1>(0), T_990) + node T_992 = mux(T_852, UInt<1>(0), T_991) + node T_993 = mux(T_850, UInt<1>(1), T_992) + node T_994 = mux(T_848, UInt<1>(1), T_993) + node T_995 = mux(T_846, UInt<1>(1), T_994) + node T_996 = mux(T_844, UInt<1>(1), T_995) + node T_997 = mux(T_842, UInt<1>(1), T_996) + node T_998 = mux(T_840, UInt<1>(1), T_997) + node T_999 = mux(T_838, UInt<1>(0), T_998) + node T_1000 = mux(T_836, UInt<1>(1), T_999) + node T_1001 = mux(T_834, UInt<1>(1), T_1000) + node T_1002 = mux(T_832, UInt<1>(1), T_1001) + node T_1003 = mux(T_916, UInt<1>(1), UInt<1>(0)) + node T_1004 = mux(T_914, UInt<1>(1), T_1003) + node T_1005 = mux(T_912, UInt<1>(1), T_1004) + node T_1006 = mux(T_910, UInt<1>(0), T_1005) + node T_1007 = mux(T_908, UInt<1>(0), T_1006) + node T_1008 = mux(T_906, UInt<1>(0), T_1007) + node T_1009 = mux(T_904, UInt<1>(0), T_1008) + node T_1010 = mux(T_902, UInt<1>(0), T_1009) + node T_1011 = mux(T_900, UInt<1>(0), T_1010) + node T_1012 = mux(T_898, UInt<1>(0), T_1011) + node T_1013 = mux(T_896, UInt<1>(0), T_1012) + node T_1014 = mux(T_894, UInt<1>(0), T_1013) + node T_1015 = mux(T_892, UInt<1>(0), T_1014) + node T_1016 = mux(T_890, UInt<1>(0), T_1015) + node T_1017 = mux(T_888, UInt<1>(0), T_1016) + node T_1018 = mux(T_886, UInt<1>(0), T_1017) + node T_1019 = mux(T_884, UInt<1>(1), T_1018) + node T_1020 = mux(T_882, UInt<1>(1), T_1019) + node T_1021 = mux(T_880, UInt<1>(1), T_1020) + node T_1022 = mux(T_878, UInt<1>(1), T_1021) + node T_1023 = mux(T_876, UInt<1>(1), T_1022) + node T_1024 = mux(T_874, UInt<1>(1), T_1023) + node T_1025 = mux(T_872, UInt<1>(1), T_1024) + node T_1026 = mux(T_870, UInt<1>(1), T_1025) + node T_1027 = mux(T_868, UInt<1>(1), T_1026) + node T_1028 = mux(T_866, UInt<1>(1), T_1027) + node T_1029 = mux(T_864, UInt<1>(1), T_1028) + node T_1030 = mux(T_862, UInt<1>(1), T_1029) + node T_1031 = mux(T_860, UInt<1>(1), T_1030) + node T_1032 = mux(T_858, UInt<1>(1), T_1031) + node T_1033 = mux(T_856, UInt<1>(1), T_1032) + node T_1034 = mux(T_854, UInt<1>(1), T_1033) + node T_1035 = mux(T_852, UInt<1>(1), T_1034) + node T_1036 = mux(T_850, UInt<1>(1), T_1035) + node T_1037 = mux(T_848, UInt<1>(1), T_1036) + node T_1038 = mux(T_846, UInt<1>(1), T_1037) + node T_1039 = mux(T_844, UInt<1>(1), T_1038) + node T_1040 = mux(T_842, UInt<1>(1), T_1039) + node T_1041 = mux(T_840, UInt<1>(1), T_1040) + node T_1042 = mux(T_838, UInt<1>(1), T_1041) + node T_1043 = mux(T_836, UInt<1>(1), T_1042) + node T_1044 = mux(T_834, UInt<1>(1), T_1043) + node T_1045 = mux(T_832, UInt<1>(1), T_1044) + node T_1046 = mux(T_916, UInt<3>(5), UInt<3>(7)) + node T_1047 = mux(T_914, UInt<3>(5), T_1046) + node T_1048 = mux(T_912, UInt<3>(5), T_1047) + node T_1049 = mux(T_910, UInt<3>(5), T_1048) + node T_1050 = mux(T_908, UInt<3>(5), T_1049) + node T_1051 = mux(T_906, UInt<3>(5), T_1050) + node T_1052 = mux(T_904, UInt<3>(7), T_1051) + node T_1053 = mux(T_902, UInt<3>(7), T_1052) + node T_1054 = mux(T_900, UInt<3>(7), T_1053) + node T_1055 = mux(T_898, UInt<3>(7), T_1054) + node T_1056 = mux(T_896, UInt<3>(7), T_1055) + node T_1057 = mux(T_894, UInt<3>(7), T_1056) + node T_1058 = mux(T_892, UInt<3>(7), T_1057) + node T_1059 = mux(T_890, UInt<3>(7), T_1058) + node T_1060 = mux(T_888, UInt<3>(7), T_1059) + node T_1061 = mux(T_886, UInt<3>(7), T_1060) + node T_1062 = mux(T_884, UInt<3>(0), T_1061) + node T_1063 = mux(T_882, UInt<3>(0), T_1062) + node T_1064 = mux(T_880, UInt<3>(0), T_1063) + node T_1065 = mux(T_878, UInt<3>(0), T_1064) + node T_1066 = mux(T_876, UInt<3>(0), T_1065) + node T_1067 = mux(T_874, UInt<3>(0), T_1066) + node T_1068 = mux(T_872, UInt<3>(0), T_1067) + node T_1069 = mux(T_870, UInt<3>(0), T_1068) + node T_1070 = mux(T_868, UInt<3>(0), T_1069) + node T_1071 = mux(T_866, UInt<3>(1), T_1070) + node T_1072 = mux(T_864, UInt<3>(1), T_1071) + node T_1073 = mux(T_862, UInt<3>(1), T_1072) + node T_1074 = mux(T_860, UInt<3>(0), T_1073) + node T_1075 = mux(T_858, UInt<3>(0), T_1074) + node T_1076 = mux(T_856, UInt<3>(0), T_1075) + node T_1077 = mux(T_854, UInt<3>(0), T_1076) + node T_1078 = mux(T_852, UInt<3>(0), T_1077) + node T_1079 = mux(T_850, UInt<3>(4), T_1078) + node T_1080 = mux(T_848, UInt<3>(4), T_1079) + node T_1081 = mux(T_846, UInt<3>(4), T_1080) + node T_1082 = mux(T_844, UInt<3>(4), T_1081) + node T_1083 = mux(T_842, UInt<3>(4), T_1082) + node T_1084 = mux(T_840, UInt<3>(4), T_1083) + node T_1085 = mux(T_838, UInt<3>(0), T_1084) + node T_1086 = mux(T_836, UInt<3>(3), T_1085) + node T_1087 = mux(T_834, UInt<3>(2), T_1086) + node T_1088 = mux(T_832, UInt<3>(2), T_1087) + node T_1089 = mux(T_916, UInt<4>(11), UInt<4>(15)) + node T_1090 = mux(T_914, UInt<4>(11), T_1089) + node T_1091 = mux(T_912, UInt<4>(11), T_1090) + node T_1092 = mux(T_910, UInt<4>(10), T_1091) + node T_1093 = mux(T_908, UInt<4>(10), T_1092) + node T_1094 = mux(T_906, UInt<4>(10), T_1093) + node T_1095 = mux(T_904, UInt<4>(2), T_1094) + node T_1096 = mux(T_902, UInt<4>(3), T_1095) + node T_1097 = mux(T_900, UInt<4>(9), T_1096) + node T_1098 = mux(T_898, UInt<4>(8), T_1097) + node T_1099 = mux(T_896, UInt<4>(4), T_1098) + node T_1100 = mux(T_894, UInt<4>(7), T_1099) + node T_1101 = mux(T_892, UInt<4>(5), T_1100) + node T_1102 = mux(T_890, UInt<4>(6), T_1101) + node T_1103 = mux(T_888, UInt<4>(1), T_1102) + node T_1104 = mux(T_886, UInt<4>(0), T_1103) + node T_1105 = mux(T_884, UInt<4>(9), T_1104) + node T_1106 = mux(T_882, UInt<4>(8), T_1105) + node T_1107 = mux(T_880, UInt<4>(6), T_1106) + node T_1108 = mux(T_878, UInt<4>(2), T_1107) + node T_1109 = mux(T_876, UInt<4>(3), T_1108) + node T_1110 = mux(T_874, UInt<4>(4), T_1109) + node T_1111 = mux(T_872, UInt<4>(7), T_1110) + node T_1112 = mux(T_870, UInt<4>(5), T_1111) + node T_1113 = mux(T_868, UInt<4>(0), T_1112) + node T_1114 = mux(T_866, UInt<4>(0), T_1113) + node T_1115 = mux(T_864, UInt<4>(0), T_1114) + node T_1116 = mux(T_862, UInt<4>(0), T_1115) + node T_1117 = mux(T_860, UInt<4>(0), T_1116) + node T_1118 = mux(T_858, UInt<4>(0), T_1117) + node T_1119 = mux(T_856, UInt<4>(0), T_1118) + node T_1120 = mux(T_854, UInt<4>(0), T_1119) + node T_1121 = mux(T_852, UInt<4>(0), T_1120) + node T_1122 = mux(T_850, UInt<4>(0), T_1121) + node T_1123 = mux(T_848, UInt<4>(0), T_1122) + node T_1124 = mux(T_846, UInt<4>(0), T_1123) + node T_1125 = mux(T_844, UInt<4>(0), T_1124) + node T_1126 = mux(T_842, UInt<4>(0), T_1125) + node T_1127 = mux(T_840, UInt<4>(0), T_1126) + node T_1128 = mux(T_838, UInt<4>(0), T_1127) + node T_1129 = mux(T_836, UInt<4>(0), T_1128) + node T_1130 = mux(T_834, UInt<4>(0), T_1129) + node T_1131 = mux(T_832, UInt<4>(11), T_1130) + node T_1132 = mux(T_916, UInt<3>(7), UInt<3>(7)) + node T_1133 = mux(T_914, UInt<3>(7), T_1132) + node T_1134 = mux(T_912, UInt<3>(7), T_1133) + node T_1135 = mux(T_910, UInt<3>(7), T_1134) + node T_1136 = mux(T_908, UInt<3>(7), T_1135) + node T_1137 = mux(T_906, UInt<3>(7), T_1136) + node T_1138 = mux(T_904, UInt<3>(7), T_1137) + node T_1139 = mux(T_902, UInt<3>(7), T_1138) + node T_1140 = mux(T_900, UInt<3>(7), T_1139) + node T_1141 = mux(T_898, UInt<3>(7), T_1140) + node T_1142 = mux(T_896, UInt<3>(7), T_1141) + node T_1143 = mux(T_894, UInt<3>(7), T_1142) + node T_1144 = mux(T_892, UInt<3>(7), T_1143) + node T_1145 = mux(T_890, UInt<3>(7), T_1144) + node T_1146 = mux(T_888, UInt<3>(7), T_1145) + node T_1147 = mux(T_886, UInt<3>(7), T_1146) + node T_1148 = mux(T_884, UInt<3>(7), T_1147) + node T_1149 = mux(T_882, UInt<3>(7), T_1148) + node T_1150 = mux(T_880, UInt<3>(7), T_1149) + node T_1151 = mux(T_878, UInt<3>(7), T_1150) + node T_1152 = mux(T_876, UInt<3>(7), T_1151) + node T_1153 = mux(T_874, UInt<3>(7), T_1152) + node T_1154 = mux(T_872, UInt<3>(7), T_1153) + node T_1155 = mux(T_870, UInt<3>(7), T_1154) + node T_1156 = mux(T_868, UInt<3>(7), T_1155) + node T_1157 = mux(T_866, UInt<3>(7), T_1156) + node T_1158 = mux(T_864, UInt<3>(7), T_1157) + node T_1159 = mux(T_862, UInt<3>(7), T_1158) + node T_1160 = mux(T_860, UInt<3>(7), T_1159) + node T_1161 = mux(T_858, UInt<3>(7), T_1160) + node T_1162 = mux(T_856, UInt<3>(7), T_1161) + node T_1163 = mux(T_854, UInt<3>(7), T_1162) + node T_1164 = mux(T_852, UInt<3>(7), T_1163) + node T_1165 = mux(T_850, UInt<3>(4), T_1164) + node T_1166 = mux(T_848, UInt<3>(0), T_1165) + node T_1167 = mux(T_846, UInt<3>(5), T_1166) + node T_1168 = mux(T_844, UInt<3>(1), T_1167) + node T_1169 = mux(T_842, UInt<3>(6), T_1168) + node T_1170 = mux(T_840, UInt<3>(2), T_1169) + node T_1171 = mux(T_838, UInt<3>(7), T_1170) + node T_1172 = mux(T_836, UInt<3>(7), T_1171) + node T_1173 = mux(T_834, UInt<3>(7), T_1172) + node T_1174 = mux(T_832, UInt<3>(7), T_1173) + node T_1175 = mux(T_916, UInt<1>(0), UInt<1>(0)) + node T_1176 = mux(T_914, UInt<1>(0), T_1175) + node T_1177 = mux(T_912, UInt<1>(0), T_1176) + node T_1178 = mux(T_910, UInt<1>(0), T_1177) + node T_1179 = mux(T_908, UInt<1>(0), T_1178) + node T_1180 = mux(T_906, UInt<1>(0), T_1179) + node T_1181 = mux(T_904, UInt<1>(0), T_1180) + node T_1182 = mux(T_902, UInt<1>(0), T_1181) + node T_1183 = mux(T_900, UInt<1>(0), T_1182) + node T_1184 = mux(T_898, UInt<1>(0), T_1183) + node T_1185 = mux(T_896, UInt<1>(0), T_1184) + node T_1186 = mux(T_894, UInt<1>(0), T_1185) + node T_1187 = mux(T_892, UInt<1>(0), T_1186) + node T_1188 = mux(T_890, UInt<1>(0), T_1187) + node T_1189 = mux(T_888, UInt<1>(0), T_1188) + node T_1190 = mux(T_886, UInt<1>(0), T_1189) + node T_1191 = mux(T_884, UInt<1>(0), T_1190) + node T_1192 = mux(T_882, UInt<1>(0), T_1191) + node T_1193 = mux(T_880, UInt<1>(0), T_1192) + node T_1194 = mux(T_878, UInt<1>(0), T_1193) + node T_1195 = mux(T_876, UInt<1>(0), T_1194) + node T_1196 = mux(T_874, UInt<1>(0), T_1195) + node T_1197 = mux(T_872, UInt<1>(0), T_1196) + node T_1198 = mux(T_870, UInt<1>(0), T_1197) + node T_1199 = mux(T_868, UInt<1>(0), T_1198) + node T_1200 = mux(T_866, UInt<1>(0), T_1199) + node T_1201 = mux(T_864, UInt<1>(0), T_1200) + node T_1202 = mux(T_862, UInt<1>(0), T_1201) + node T_1203 = mux(T_860, UInt<1>(0), T_1202) + node T_1204 = mux(T_858, UInt<1>(0), T_1203) + node T_1205 = mux(T_856, UInt<1>(0), T_1204) + node T_1206 = mux(T_854, UInt<1>(0), T_1205) + node T_1207 = mux(T_852, UInt<1>(0), T_1206) + node T_1208 = mux(T_850, UInt<1>(0), T_1207) + node T_1209 = mux(T_848, UInt<1>(0), T_1208) + node T_1210 = mux(T_846, UInt<1>(0), T_1209) + node T_1211 = mux(T_844, UInt<1>(0), T_1210) + node T_1212 = mux(T_842, UInt<1>(0), T_1211) + node T_1213 = mux(T_840, UInt<1>(0), T_1212) + node T_1214 = mux(T_838, UInt<1>(1), T_1213) + node T_1215 = mux(T_836, UInt<1>(1), T_1214) + node T_1216 = mux(T_834, UInt<1>(0), T_1215) + node T_1217 = mux(T_832, UInt<1>(0), T_1216) + node T_1218 = mux(T_916, UInt<2>(3), UInt<2>(3)) + node T_1219 = mux(T_914, UInt<2>(3), T_1218) + node T_1220 = mux(T_912, UInt<2>(3), T_1219) + node T_1221 = mux(T_910, UInt<2>(3), T_1220) + node T_1222 = mux(T_908, UInt<2>(3), T_1221) + node T_1223 = mux(T_906, UInt<2>(3), T_1222) + node T_1224 = mux(T_904, UInt<2>(3), T_1223) + node T_1225 = mux(T_902, UInt<2>(3), T_1224) + node T_1226 = mux(T_900, UInt<2>(3), T_1225) + node T_1227 = mux(T_898, UInt<2>(3), T_1226) + node T_1228 = mux(T_896, UInt<2>(3), T_1227) + node T_1229 = mux(T_894, UInt<2>(3), T_1228) + node T_1230 = mux(T_892, UInt<2>(3), T_1229) + node T_1231 = mux(T_890, UInt<2>(3), T_1230) + node T_1232 = mux(T_888, UInt<2>(3), T_1231) + node T_1233 = mux(T_886, UInt<2>(3), T_1232) + node T_1234 = mux(T_884, UInt<2>(3), T_1233) + node T_1235 = mux(T_882, UInt<2>(3), T_1234) + node T_1236 = mux(T_880, UInt<2>(3), T_1235) + node T_1237 = mux(T_878, UInt<2>(3), T_1236) + node T_1238 = mux(T_876, UInt<2>(3), T_1237) + node T_1239 = mux(T_874, UInt<2>(3), T_1238) + node T_1240 = mux(T_872, UInt<2>(3), T_1239) + node T_1241 = mux(T_870, UInt<2>(3), T_1240) + node T_1242 = mux(T_868, UInt<2>(3), T_1241) + node T_1243 = mux(T_866, UInt<2>(0), T_1242) + node T_1244 = mux(T_864, UInt<2>(1), T_1243) + node T_1245 = mux(T_862, UInt<2>(2), T_1244) + node T_1246 = mux(T_860, UInt<2>(3), T_1245) + node T_1247 = mux(T_858, UInt<2>(3), T_1246) + node T_1248 = mux(T_856, UInt<2>(3), T_1247) + node T_1249 = mux(T_854, UInt<2>(3), T_1248) + node T_1250 = mux(T_852, UInt<2>(3), T_1249) + node T_1251 = mux(T_850, UInt<2>(3), T_1250) + node T_1252 = mux(T_848, UInt<2>(3), T_1251) + node T_1253 = mux(T_846, UInt<2>(3), T_1252) + node T_1254 = mux(T_844, UInt<2>(3), T_1253) + node T_1255 = mux(T_842, UInt<2>(3), T_1254) + node T_1256 = mux(T_840, UInt<2>(3), T_1255) + node T_1257 = mux(T_838, UInt<2>(3), T_1256) + node T_1258 = mux(T_836, UInt<2>(3), T_1257) + node T_1259 = mux(T_834, UInt<2>(3), T_1258) + node T_1260 = mux(T_832, UInt<2>(3), T_1259) + node T_1261 = mux(T_916, UInt<3>(7), UInt<3>(7)) + node T_1262 = mux(T_914, UInt<3>(7), T_1261) + node T_1263 = mux(T_912, UInt<3>(7), T_1262) + node T_1264 = mux(T_910, UInt<3>(7), T_1263) + node T_1265 = mux(T_908, UInt<3>(7), T_1264) + node T_1266 = mux(T_906, UInt<3>(7), T_1265) + node T_1267 = mux(T_904, UInt<3>(7), T_1266) + node T_1268 = mux(T_902, UInt<3>(7), T_1267) + node T_1269 = mux(T_900, UInt<3>(7), T_1268) + node T_1270 = mux(T_898, UInt<3>(7), T_1269) + node T_1271 = mux(T_896, UInt<3>(7), T_1270) + node T_1272 = mux(T_894, UInt<3>(7), T_1271) + node T_1273 = mux(T_892, UInt<3>(7), T_1272) + node T_1274 = mux(T_890, UInt<3>(7), T_1273) + node T_1275 = mux(T_888, UInt<3>(7), T_1274) + node T_1276 = mux(T_886, UInt<3>(7), T_1275) + node T_1277 = mux(T_884, UInt<3>(7), T_1276) + node T_1278 = mux(T_882, UInt<3>(7), T_1277) + node T_1279 = mux(T_880, UInt<3>(7), T_1278) + node T_1280 = mux(T_878, UInt<3>(7), T_1279) + node T_1281 = mux(T_876, UInt<3>(7), T_1280) + node T_1282 = mux(T_874, UInt<3>(7), T_1281) + node T_1283 = mux(T_872, UInt<3>(7), T_1282) + node T_1284 = mux(T_870, UInt<3>(7), T_1283) + node T_1285 = mux(T_868, UInt<3>(7), T_1284) + node T_1286 = mux(T_866, UInt<3>(7), T_1285) + node T_1287 = mux(T_864, UInt<3>(7), T_1286) + node T_1288 = mux(T_862, UInt<3>(7), T_1287) + node T_1289 = mux(T_860, UInt<3>(3), T_1288) + node T_1290 = mux(T_858, UInt<3>(4), T_1289) + node T_1291 = mux(T_856, UInt<3>(0), T_1290) + node T_1292 = mux(T_854, UInt<3>(1), T_1291) + node T_1293 = mux(T_852, UInt<3>(2), T_1292) + node T_1294 = mux(T_850, UInt<3>(7), T_1293) + node T_1295 = mux(T_848, UInt<3>(7), T_1294) + node T_1296 = mux(T_846, UInt<3>(7), T_1295) + node T_1297 = mux(T_844, UInt<3>(7), T_1296) + node T_1298 = mux(T_842, UInt<3>(7), T_1297) + node T_1299 = mux(T_840, UInt<3>(7), T_1298) + node T_1300 = mux(T_838, UInt<3>(7), T_1299) + node T_1301 = mux(T_836, UInt<3>(7), T_1300) + node T_1302 = mux(T_834, UInt<3>(7), T_1301) + node T_1303 = mux(T_832, UInt<3>(7), T_1302) + node T_1304 = mux(T_916, UInt<2>(3), UInt<2>(0)) + node T_1305 = mux(T_914, UInt<2>(3), T_1304) + node T_1306 = mux(T_912, UInt<2>(3), T_1305) + node T_1307 = mux(T_910, UInt<2>(3), T_1306) + node T_1308 = mux(T_908, UInt<2>(3), T_1307) + node T_1309 = mux(T_906, UInt<2>(3), T_1308) + node T_1310 = mux(T_904, UInt<2>(0), T_1309) + node T_1311 = mux(T_902, UInt<2>(0), T_1310) + node T_1312 = mux(T_900, UInt<2>(0), T_1311) + node T_1313 = mux(T_898, UInt<2>(0), T_1312) + node T_1314 = mux(T_896, UInt<2>(0), T_1313) + node T_1315 = mux(T_894, UInt<2>(0), T_1314) + node T_1316 = mux(T_892, UInt<2>(0), T_1315) + node T_1317 = mux(T_890, UInt<2>(0), T_1316) + node T_1318 = mux(T_888, UInt<2>(0), T_1317) + node T_1319 = mux(T_886, UInt<2>(0), T_1318) + node T_1320 = mux(T_884, UInt<2>(0), T_1319) + node T_1321 = mux(T_882, UInt<2>(0), T_1320) + node T_1322 = mux(T_880, UInt<2>(0), T_1321) + node T_1323 = mux(T_878, UInt<2>(0), T_1322) + node T_1324 = mux(T_876, UInt<2>(0), T_1323) + node T_1325 = mux(T_874, UInt<2>(0), T_1324) + node T_1326 = mux(T_872, UInt<2>(0), T_1325) + node T_1327 = mux(T_870, UInt<2>(0), T_1326) + node T_1328 = mux(T_868, UInt<2>(0), T_1327) + node T_1329 = mux(T_866, UInt<2>(0), T_1328) + node T_1330 = mux(T_864, UInt<2>(0), T_1329) + node T_1331 = mux(T_862, UInt<2>(0), T_1330) + node T_1332 = mux(T_860, UInt<2>(1), T_1331) + node T_1333 = mux(T_858, UInt<2>(1), T_1332) + node T_1334 = mux(T_856, UInt<2>(1), T_1333) + node T_1335 = mux(T_854, UInt<2>(1), T_1334) + node T_1336 = mux(T_852, UInt<2>(1), T_1335) + node T_1337 = mux(T_850, UInt<2>(0), T_1336) + node T_1338 = mux(T_848, UInt<2>(0), T_1337) + node T_1339 = mux(T_846, UInt<2>(0), T_1338) + node T_1340 = mux(T_844, UInt<2>(0), T_1339) + node T_1341 = mux(T_842, UInt<2>(0), T_1340) + node T_1342 = mux(T_840, UInt<2>(0), T_1341) + node T_1343 = mux(T_838, UInt<2>(2), T_1342) + node T_1344 = mux(T_836, UInt<2>(2), T_1343) + node T_1345 = mux(T_834, UInt<2>(0), T_1344) + node T_1346 = mux(T_832, UInt<2>(0), T_1345) + node T_1347 = mux(T_916, UInt<1>(0), UInt<1>(0)) + node T_1348 = mux(T_914, UInt<1>(0), T_1347) + node T_1349 = mux(T_912, UInt<1>(0), T_1348) + node T_1350 = mux(T_910, UInt<1>(0), T_1349) + node T_1351 = mux(T_908, UInt<1>(0), T_1350) + node T_1352 = mux(T_906, UInt<1>(0), T_1351) + node T_1353 = mux(T_904, UInt<1>(1), T_1352) + node T_1354 = mux(T_902, UInt<1>(1), T_1353) + node T_1355 = mux(T_900, UInt<1>(1), T_1354) + node T_1356 = mux(T_898, UInt<1>(1), T_1355) + node T_1357 = mux(T_896, UInt<1>(1), T_1356) + node T_1358 = mux(T_894, UInt<1>(1), T_1357) + node T_1359 = mux(T_892, UInt<1>(1), T_1358) + node T_1360 = mux(T_890, UInt<1>(1), T_1359) + node T_1361 = mux(T_888, UInt<1>(1), T_1360) + node T_1362 = mux(T_886, UInt<1>(1), T_1361) + node T_1363 = mux(T_884, UInt<1>(1), T_1362) + node T_1364 = mux(T_882, UInt<1>(1), T_1363) + node T_1365 = mux(T_880, UInt<1>(1), T_1364) + node T_1366 = mux(T_878, UInt<1>(1), T_1365) + node T_1367 = mux(T_876, UInt<1>(1), T_1366) + node T_1368 = mux(T_874, UInt<1>(1), T_1367) + node T_1369 = mux(T_872, UInt<1>(1), T_1368) + node T_1370 = mux(T_870, UInt<1>(1), T_1369) + node T_1371 = mux(T_868, UInt<1>(1), T_1370) + node T_1372 = mux(T_866, UInt<1>(0), T_1371) + node T_1373 = mux(T_864, UInt<1>(0), T_1372) + node T_1374 = mux(T_862, UInt<1>(0), T_1373) + node T_1375 = mux(T_860, UInt<1>(1), T_1374) + node T_1376 = mux(T_858, UInt<1>(1), T_1375) + node T_1377 = mux(T_856, UInt<1>(1), T_1376) + node T_1378 = mux(T_854, UInt<1>(1), T_1377) + node T_1379 = mux(T_852, UInt<1>(1), T_1378) + node T_1380 = mux(T_850, UInt<1>(0), T_1379) + node T_1381 = mux(T_848, UInt<1>(0), T_1380) + node T_1382 = mux(T_846, UInt<1>(0), T_1381) + node T_1383 = mux(T_844, UInt<1>(0), T_1382) + node T_1384 = mux(T_842, UInt<1>(0), T_1383) + node T_1385 = mux(T_840, UInt<1>(0), T_1384) + node T_1386 = mux(T_838, UInt<1>(1), T_1385) + node T_1387 = mux(T_836, UInt<1>(1), T_1386) + node T_1388 = mux(T_834, UInt<1>(1), T_1387) + node T_1389 = mux(T_832, UInt<1>(1), T_1388) + node T_1390 = mux(T_916, UInt<2>(3), UInt<2>(0)) + node T_1391 = mux(T_914, UInt<2>(2), T_1390) + node T_1392 = mux(T_912, UInt<2>(1), T_1391) + node T_1393 = mux(T_910, UInt<2>(3), T_1392) + node T_1394 = mux(T_908, UInt<2>(2), T_1393) + node T_1395 = mux(T_906, UInt<2>(1), T_1394) + node T_1396 = mux(T_904, UInt<2>(0), T_1395) + node T_1397 = mux(T_902, UInt<2>(0), T_1396) + node T_1398 = mux(T_900, UInt<2>(0), T_1397) + node T_1399 = mux(T_898, UInt<2>(0), T_1398) + node T_1400 = mux(T_896, UInt<2>(0), T_1399) + node T_1401 = mux(T_894, UInt<2>(0), T_1400) + node T_1402 = mux(T_892, UInt<2>(0), T_1401) + node T_1403 = mux(T_890, UInt<2>(0), T_1402) + node T_1404 = mux(T_888, UInt<2>(0), T_1403) + node T_1405 = mux(T_886, UInt<2>(0), T_1404) + node T_1406 = mux(T_884, UInt<2>(0), T_1405) + node T_1407 = mux(T_882, UInt<2>(0), T_1406) + node T_1408 = mux(T_880, UInt<2>(0), T_1407) + node T_1409 = mux(T_878, UInt<2>(0), T_1408) + node T_1410 = mux(T_876, UInt<2>(0), T_1409) + node T_1411 = mux(T_874, UInt<2>(0), T_1410) + node T_1412 = mux(T_872, UInt<2>(0), T_1411) + node T_1413 = mux(T_870, UInt<2>(0), T_1412) + node T_1414 = mux(T_868, UInt<2>(0), T_1413) + node T_1415 = mux(T_866, UInt<2>(0), T_1414) + node T_1416 = mux(T_864, UInt<2>(0), T_1415) + node T_1417 = mux(T_862, UInt<2>(0), T_1416) + node T_1418 = mux(T_860, UInt<2>(0), T_1417) + node T_1419 = mux(T_858, UInt<2>(0), T_1418) + node T_1420 = mux(T_856, UInt<2>(0), T_1419) + node T_1421 = mux(T_854, UInt<2>(0), T_1420) + node T_1422 = mux(T_852, UInt<2>(0), T_1421) + node T_1423 = mux(T_850, UInt<2>(0), T_1422) + node T_1424 = mux(T_848, UInt<2>(0), T_1423) + node T_1425 = mux(T_846, UInt<2>(0), T_1424) + node T_1426 = mux(T_844, UInt<2>(0), T_1425) + node T_1427 = mux(T_842, UInt<2>(0), T_1426) + node T_1428 = mux(T_840, UInt<2>(0), T_1427) + node T_1429 = mux(T_838, UInt<2>(0), T_1428) + node T_1430 = mux(T_836, UInt<2>(0), T_1429) + node T_1431 = mux(T_834, UInt<2>(0), T_1430) + node T_1432 = mux(T_832, UInt<2>(0), T_1431) node rs1_addr = bits(ctrl.inst, 19, 15) node rs2_addr = bits(ctrl.inst, 24, 20) - reg st_type : UInt<2> - reg ld_type : UInt<3> - reg wb_sel : UInt<2> - node T_2038 = bit(T_1994, 0) - reg wb_en : UInt<1> - reg csr_cmd : UInt<2> - ctrl.pc_sel := T_1564 - node T_2039 = bit-not(ctrl.stall) - node T_2040 = bit-not(ctrl.data_re) - node T_2041 = bit-and(T_2039, T_2040) - ctrl.inst_re := T_2041 - node T_2042 = neq(T_1908, UInt<3>(7)) - node T_2043 = bit(T_1822, 0) - node T_2044 = bit-or(T_2042, T_2043) - node T_2045 = mux(T_2044, UInt<1>(1), UInt<1>(0)) - ctrl.inst_type := T_2045 - ctrl.A_sel := T_1607 - ctrl.B_sel := T_1650 - ctrl.imm_sel := T_1693 - ctrl.alu_op := T_1736 - ctrl.br_type := T_1779 - ctrl.st_type := T_1865 - node T_2046 = bit-not(ctrl.stall) - when T_2046 : + reg st_type : UInt<2>, clk, reset + reg ld_type : UInt<3>, clk, reset + reg wb_sel : UInt<2>, clk, reset + node T_1433 = bit(T_1389, 0) + reg wb_en : UInt<1>, clk, reset + reg csr_cmd : UInt<2>, clk, reset + ctrl.pc_sel := T_959 + node T_1434 = not(ctrl.stall) + node T_1435 = not(ctrl.data_re) + node T_1436 = and(T_1434, T_1435) + ctrl.inst_re := T_1436 + node T_1437 = neq(T_1303, UInt<3>(7)) + node T_1438 = bit(T_1217, 0) + node T_1439 = or(T_1437, T_1438) + node T_1440 = mux(T_1439, UInt<1>(1), UInt<1>(0)) + ctrl.inst_type := T_1440 + ctrl.A_sel := T_1002 + ctrl.B_sel := T_1045 + ctrl.imm_sel := T_1088 + ctrl.alu_op := T_1131 + ctrl.br_type := T_1174 + ctrl.st_type := T_1260 + node T_1441 = not(ctrl.stall) + when T_1441 : st_type := ctrl.st_type - ld_type := T_1908 - wb_sel := T_1951 - node T_2047 = bit(T_1994, 0) - wb_en := T_2047 - csr_cmd := T_2037 - node T_2048 = neq(ctrl.ld_type, UInt<3>(7)) - node T_2049 = neq(T_1908, UInt<3>(7)) - node T_2050 = mux(ctrl.stall, T_2048, T_2049) - ctrl.data_re := T_2050 + ld_type := T_1303 + wb_sel := T_1346 + node T_1442 = bit(T_1389, 0) + wb_en := T_1442 + csr_cmd := T_1432 + node T_1443 = neq(ctrl.ld_type, UInt<3>(7)) + node T_1444 = neq(T_1303, UInt<3>(7)) + node T_1445 = mux(ctrl.stall, T_1443, T_1444) + ctrl.data_re := T_1445 ctrl.ld_type := ld_type ctrl.wb_en := wb_en ctrl.wb_sel := wb_sel diff --git a/test/chisel3/Datapath.fir b/test/chisel3/Datapath.fir index c2752a37..1315041a 100644 --- a/test/chisel3/Datapath.fir +++ b/test/chisel3/Datapath.fir @@ -10,23 +10,23 @@ circuit Datapath : input alu_op : UInt<4> node shamt = bits(B, 4, 0) - node T_433 = add-wrap(A, B) - node T_434 = sub-wrap(A, B) - node T_435 = as-SInt(A) + node T_433 = addw(A, B) + node T_434 = subw(A, B) + node T_435 = asSInt(A) node T_436 = dshr(T_435, shamt) - node T_437 = as-UInt(T_436) + node T_437 = asUInt(T_436) node T_438 = dshr(A, shamt) node T_439 = dshl(A, shamt) node T_440 = bits(T_439, 31, 0) - node T_441 = as-SInt(A) - node T_442 = as-SInt(B) + node T_441 = asSInt(A) + node T_442 = asSInt(B) node T_443 = lt(T_441, T_442) - node T_444 = as-UInt(T_443) + node T_444 = asUInt(T_443) node T_445 = lt(A, B) - node T_446 = as-UInt(T_445) - node T_447 = bit-and(A, B) - node T_448 = bit-or(A, B) - node T_449 = bit-xor(A, B) + node T_446 = asUInt(T_445) + node T_447 = and(A, B) + node T_448 = or(A, B) + node T_449 = xor(A, B) node T_450 = eq(UInt<4>(10), alu_op) node T_451 = mux(T_450, A, B) node T_452 = eq(UInt<4>(4), alu_op) @@ -52,9 +52,9 @@ circuit Datapath : node T_471 = bits(oot, 31, 0) out := T_471 node T_472 = bit(alu_op, 0) - node T_473 = sub-wrap(UInt<1>(0), B) + node T_473 = subw(UInt<1>(0), B) node T_474 = mux(T_472, T_473, B) - node T_475 = add-wrap(A, T_474) + node T_475 = addw(A, T_474) sum := T_475 module BrCond : input rs1 : UInt<32> @@ -63,32 +63,33 @@ circuit Datapath : input br_type : UInt<3> node eq = eq(rs1, rs2) - node neq = bit-not(eq) - node T_476 = as-SInt(rs1) - node T_477 = as-SInt(rs2) + node neq = not(eq) + node T_476 = asSInt(rs1) + node T_477 = asSInt(rs2) node lt = lt(T_476, T_477) - node ge = bit-not(lt) + node ge = not(lt) node ltu = lt(rs1, rs2) - node geu = bit-not(ltu) + node geu = not(ltu) node T_478 = eq(br_type, UInt<3>(2)) - node T_479 = bit-and(T_478, eq) + node T_479 = and(T_478, eq) node T_480 = eq(br_type, UInt<3>(6)) - node T_481 = bit-and(T_480, neq) - node T_482 = bit-or(T_479, T_481) + node T_481 = and(T_480, neq) + node T_482 = or(T_479, T_481) node T_483 = eq(br_type, UInt<3>(1)) - node T_484 = bit-and(T_483, lt) - node T_485 = bit-or(T_482, T_484) + node T_484 = and(T_483, lt) + node T_485 = or(T_482, T_484) node T_486 = eq(br_type, UInt<3>(5)) - node T_487 = bit-and(T_486, ge) - node T_488 = bit-or(T_485, T_487) + node T_487 = and(T_486, ge) + node T_488 = or(T_485, T_487) node T_489 = eq(br_type, UInt<3>(0)) - node T_490 = bit-and(T_489, ltu) - node T_491 = bit-or(T_488, T_490) + node T_490 = and(T_489, ltu) + node T_491 = or(T_488, T_490) node T_492 = eq(br_type, UInt<3>(4)) - node T_493 = bit-and(T_492, geu) - node T_494 = bit-or(T_491, T_493) + node T_493 = and(T_492, geu) + node T_494 = or(T_491, T_493) taken := T_494 module RegFile : + input clk : Clock input raddr1 : UInt<5> input raddr2 : UInt<5> output rdata1 : UInt<32> @@ -97,20 +98,20 @@ circuit Datapath : input waddr : UInt<5> input wdata : UInt<32> - cmem regs : UInt<32>[32] + cmem regs : UInt<32>[32], clk node T_495 = eq(raddr1, UInt<1>(0)) - node T_496 = bit-not(T_495) + node T_496 = not(T_495) infer accessor T_497 = regs[raddr1] node T_498 = mux(T_496, T_497, UInt<1>(0)) rdata1 := T_498 node T_499 = eq(raddr2, UInt<1>(0)) - node T_500 = bit-not(T_499) + node T_500 = not(T_499) infer accessor T_501 = regs[raddr2] node T_502 = mux(T_500, T_501, UInt<1>(0)) rdata2 := T_502 node T_503 = eq(waddr, UInt<1>(0)) - node T_504 = bit-not(T_503) - node T_505 = bit-and(wen, T_504) + node T_504 = not(T_503) + node T_505 = and(wen, T_504) when T_505 : infer accessor T_506 = regs[waddr] T_506 := wdata @@ -120,11 +121,11 @@ circuit Datapath : input sel : UInt<3> node T_507 = bits(inst, 31, 20) - node Iimm = as-SInt(T_507) + node Iimm = asSInt(T_507) node T_508 = bits(inst, 31, 25) node T_509 = bits(inst, 11, 7) node T_510 = cat(T_508, T_509) - node Simm = as-SInt(T_510) + node Simm = asSInt(T_510) node T_511 = bit(inst, 31) node T_512 = bit(inst, 7) node T_513 = bits(inst, 30, 25) @@ -133,10 +134,10 @@ circuit Datapath : node T_516 = cat(T_514, UInt<1>(0)) node T_517 = cat(T_513, T_516) node T_518 = cat(T_515, T_517) - node Bimm = as-SInt(T_518) + node Bimm = asSInt(T_518) node T_519 = bits(inst, 31, 12) node T_520 = cat(T_519, UInt<12>(0)) - node Uimm = as-SInt(T_520) + node Uimm = asSInt(T_520) node T_521 = bit(inst, 31) node T_522 = bits(inst, 19, 12) node T_523 = bit(inst, 20) @@ -147,10 +148,10 @@ circuit Datapath : node T_528 = cat(T_525, UInt<1>(0)) node T_529 = cat(T_524, T_528) node T_530 = cat(T_527, T_529) - node Jimm = as-SInt(T_530) + node Jimm = asSInt(T_530) node T_531 = bits(inst, 19, 15) node T_532 = pad(T_531, 32) - node Zimm = as-SInt(T_532) + node Zimm = asSInt(T_532) node T_533 = eq(UInt<3>(3), sel) node T_534 = mux(T_533, Jimm, Zimm) node T_535 = eq(UInt<3>(2), sel) @@ -161,19 +162,21 @@ circuit Datapath : node T_540 = mux(T_539, Simm, T_538) node T_541 = eq(UInt<3>(0), sel) node T_542 = mux(T_541, Iimm, T_540) - node T_543 = as-UInt(T_542) + node T_543 = asUInt(T_542) out := T_543 module CSR : + input clk : Clock + input reset : UInt<1> output host : {status : UInt<32>, tohost : UInt<32>, flip hid : UInt<1>} input src : UInt<32> input cmd : UInt<2> output data : UInt<32> input addr : UInt<12> - reg reg_tohost : UInt<32> - on-reset reg_tohost := UInt<32>(0) - reg reg_status : UInt<32> - on-reset reg_status := UInt<32>(0) + reg reg_tohost : UInt<32>, clk, reset + onreset reg_tohost := UInt<32>(0) + reg reg_status : UInt<32>, clk, reset + onreset reg_status := UInt<32>(0) host.tohost := reg_tohost host.status := reg_status node T_544 = eq(UInt<12>(1291), addr) @@ -191,33 +194,35 @@ circuit Datapath : when T_552 : reg_status := src node T_553 = eq(cmd, UInt<2>(2)) node T_554 = neq(src, UInt<1>(0)) - node T_555 = bit-and(T_553, T_554) + node T_555 = and(T_553, T_554) when T_555 : node T_556 = eq(addr, UInt<12>(1310)) when T_556 : node T_557 = dshl(UInt<1>(1), bits(src,5,0)) - node T_558 = bit-or(data, T_557) + node T_558 = or(data, T_557) reg_tohost := T_558 node T_559 = eq(addr, UInt<12>(1290)) when T_559 : node T_560 = dshl(UInt<1>(1), bits(src,5,0)) - node T_561 = bit-or(data, T_560) + node T_561 = or(data, T_560) reg_status := T_561 node T_562 = eq(cmd, UInt<2>(3)) node T_563 = neq(src, UInt<1>(0)) - node T_564 = bit-and(T_562, T_563) + node T_564 = and(T_562, T_563) when T_564 : node T_565 = eq(addr, UInt<12>(1310)) when T_565 : node T_566 = dshl(UInt<1>(0), bits(src,5,0)) - node T_567 = bit-and(data, T_566) + node T_567 = and(data, T_566) reg_tohost := T_567 node T_568 = eq(addr, UInt<12>(1290)) when T_568 : node T_569 = dshl(UInt<1>(0), bits(src,5,0)) - node T_570 = bit-and(data, T_569) + node T_570 = and(data, T_569) reg_status := T_570 module Datapath : + input clk : Clock + input reset : UInt<1> output host : {status : UInt<32>, tohost : UInt<32>, flip hid : UInt<1>} input ctrl : {flip inst : UInt<32>, pc_sel : UInt<1>, inst_type : UInt<1>, inst_re : UInt<1>, flip stall : UInt<1>, imm_sel : UInt<3>, wb_en : UInt<1>, wb_sel : UInt<2>, A_sel : UInt<1>, B_sel : UInt<1>, alu_op : UInt<4>, br_type : UInt<3>, data_re : UInt<1>, st_type : UInt<2>, ld_type : UInt<3>, csr_cmd : UInt<2>} output icache : {re : UInt<1>, flip dout : UInt<32>, we : UInt<4>, addr : UInt<32>, din : UInt<32>} @@ -227,35 +232,36 @@ circuit Datapath : inst alu of ALU inst brCond of BrCond inst regFile of RegFile + regFile.clk := clk inst immGen of ImmGenWire - reg fe_inst : UInt<32> - on-reset fe_inst := UInt<32>(0) - reg fe_pc : UInt - reg ew_inst : UInt<32> - on-reset ew_inst := UInt<32>(0) - reg ew_pc : UInt - reg ew_alu : UInt - node T_571 = sub-wrap(UInt<14>(8192), UInt<32>(4)) - reg pc : UInt<32> - on-reset pc := T_571 + reg fe_inst : UInt<32>, clk, reset + onreset fe_inst := UInt<32>(0) + reg fe_pc : UInt, clk, reset + reg ew_inst : UInt<32>, clk, reset + onreset ew_inst := UInt<32>(0) + reg ew_pc : UInt, clk, reset + reg ew_alu : UInt, clk, reset + node T_571 = subw(UInt<14>(8192), UInt<32>(4)) + reg pc : UInt<32>, clk, reset + onreset pc := T_571 node T_572 = eq(ctrl.pc_sel, UInt<1>(1)) - node T_573 = bit-or(T_572, brCond.taken) - node T_574 = add-wrap(pc, UInt<3>(4)) + node T_573 = or(T_572, brCond.taken) + node T_574 = addw(pc, UInt<3>(4)) node iaddr = mux(T_573, alu.sum, T_574) node T_575 = eq(ctrl.inst_type, UInt<1>(1)) - node T_576 = bit-or(T_575, brCond.taken) + node T_576 = or(T_575, brCond.taken) node inst = mux(T_576, UInt<32>(19), icache.dout) icache.we := UInt<1>(0) icache.din := UInt<1>(0) icache.addr := iaddr icache.re := ctrl.inst_re node T_577 = eq(dcache.we, UInt<1>(0)) - node T_578 = bit-not(T_577) - node T_579 = bit-not(T_578) - node T_580 = bit-and(icache.re, T_579) + node T_578 = not(T_577) + node T_579 = not(T_578) + node T_580 = and(icache.re, T_579) node T_581 = mux(T_580, iaddr, pc) pc := T_581 - node T_582 = bit-not(stall) + node T_582 = not(stall) when T_582 : fe_pc := pc fe_inst := inst @@ -269,19 +275,19 @@ circuit Datapath : immGen.inst := fe_inst immGen.sel := ctrl.imm_sel node T_583 = eq(rs1_addr, UInt<1>(0)) - node rs1NotZero = bit-not(T_583) + node rs1NotZero = not(T_583) node T_584 = eq(rs2_addr, UInt<1>(0)) - node rs2NotZero = bit-not(T_584) + node rs2NotZero = not(T_584) node T_585 = eq(ctrl.wb_sel, UInt<2>(0)) - node alutype = bit-and(ctrl.wb_en, T_585) + node alutype = and(ctrl.wb_en, T_585) node ex_rd_addr = bits(ew_inst, 11, 7) - node T_586 = bit-and(alutype, rs1NotZero) + node T_586 = and(alutype, rs1NotZero) node T_587 = eq(rs1_addr, ex_rd_addr) - node T_588 = bit-and(T_586, T_587) + node T_588 = and(T_586, T_587) node rs1 = mux(T_588, ew_alu, regFile.rdata1) - node T_589 = bit-and(alutype, rs2NotZero) + node T_589 = and(alutype, rs2NotZero) node T_590 = eq(rs2_addr, ex_rd_addr) - node T_591 = bit-and(T_589, T_590) + node T_591 = and(T_589, T_590) node rs2 = mux(T_591, ew_alu, regFile.rdata2) node T_592 = eq(ctrl.A_sel, UInt<1>(0)) node T_593 = mux(T_592, rs1, fe_pc) @@ -297,7 +303,7 @@ circuit Datapath : node T_597 = dshl(T_596, UInt<3>(4)) node T_598 = bit(alu.sum, 0) node T_599 = dshl(T_598, UInt<2>(3)) - node woffset = bit-or(T_597, T_599) + node woffset = or(T_597, T_599) dcache.re := ctrl.data_re node T_600 = mux(stall, ew_alu, alu.sum) dcache.addr := T_600 @@ -318,7 +324,7 @@ circuit Datapath : node T_614 = dshl(rs2, woffset) node T_615 = bits(T_614, 31, 0) dcache.din := T_615 - node T_616 = bit-not(stall) + node T_616 = not(stall) when T_616 : ew_pc := fe_pc ew_inst := fe_inst @@ -327,16 +333,16 @@ circuit Datapath : node T_618 = dshl(T_617, UInt<3>(4)) node T_619 = bit(ew_alu, 0) node T_620 = dshl(T_619, UInt<2>(3)) - node loffset = bit-or(T_618, T_620) + node loffset = or(T_618, T_620) node lshift = dshr(dcache.dout, loffset) node T_621 = bits(lshift, 15, 0) - node T_622 = as-SInt(T_621) + node T_622 = asSInt(T_621) node T_623 = pad(T_622, 32) - node T_624 = as-UInt(T_623) + node T_624 = asUInt(T_623) node T_625 = bits(lshift, 7, 0) - node T_626 = as-SInt(T_625) + node T_626 = asSInt(T_625) node T_627 = pad(T_626, 32) - node T_628 = as-UInt(T_627) + node T_628 = asUInt(T_627) node T_629 = bits(lshift, 15, 0) node T_630 = bits(lshift, 7, 0) node T_631 = eq(UInt<3>(4), ctrl.ld_type) @@ -348,12 +354,14 @@ circuit Datapath : node T_637 = eq(UInt<3>(1), ctrl.ld_type) node load = mux(T_637, T_624, T_636) inst csr of CSR + csr.reset := reset + csr.clk := clk host := csr.host csr.src := ew_alu node T_638 = bits(ew_inst, 31, 20) csr.addr := T_638 csr.cmd := ctrl.csr_cmd - node T_639 = add-wrap(ew_pc, UInt<3>(4)) + node T_639 = addw(ew_pc, UInt<3>(4)) node T_640 = eq(UInt<2>(3), ctrl.wb_sel) node T_641 = mux(T_640, csr.data, ew_alu) node T_642 = eq(UInt<2>(2), ctrl.wb_sel) diff --git a/test/features/SeqMem.fir b/test/features/SeqMem.fir index 4b346ea9..4714ad4f 100644 --- a/test/features/SeqMem.fir +++ b/test/features/SeqMem.fir @@ -2,6 +2,7 @@ ;CHECK: Done! circuit Top : module Top : + input clk : Clock wire i : UInt<5> i := UInt(1) wire i0 : UInt<5> @@ -9,14 +10,14 @@ circuit Top : i0 := UInt(10) - cmem m-com : UInt<128>[32] + cmem m-com : UInt<128>[32], clk infer accessor r-com = m-com[i] infer accessor w-com = m-com[i] j := r-com w-com := j - smem m-seq : UInt<128>[32] + smem m-seq : UInt<128>[32], clk infer accessor r-seq = m-seq[i] infer accessor w-seq = m-seq[i] j := r-seq diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir index 0daec379..660ce77e 100644 --- a/test/passes/expand-accessors/accessor-mem.fir +++ b/test/passes/expand-accessors/accessor-mem.fir @@ -3,7 +3,8 @@ ;CHECK: Expand Accessors circuit top : module top : - cmem m : UInt<32>[2][2][2] + input clk : Clock + cmem m : UInt<32>[2][2][2], clk wire i : UInt<4> i := UInt(1) infer accessor a = m[i] ;CHECK: read accessor a = m[i] -- cgit v1.2.3 From 9b6d8514a3be860562d8d524fa425c87d1537e8a Mon Sep 17 00:00:00 2001 From: azidar Date: Mon, 13 Jul 2015 16:22:43 -0700 Subject: Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass --- Makefile | 2 +- notes/alpha.txt | 77 +++++++++ src/main/stanza/compilers.stanza | 19 ++- src/main/stanza/custom-compiler.stanza | 8 +- src/main/stanza/errors.stanza | 8 +- src/main/stanza/firrtl-ir.stanza | 7 +- src/main/stanza/passes.stanza | 183 +++++++++++++++++++-- src/main/stanza/verilog.stanza | 1 + test/errors/high-form/Flip-Mem.fir | 5 +- test/errors/high-form/RemoveScope.fir | 17 ++ test/errors/high-form/SpecialChars.fir | 35 ++++ test/errors/high-form/WrongReset.fir | 15 -- test/features/TwoClocks.fir | 21 +++ test/passes/expand-connect-indexed/bundle-vecs.fir | 35 ++-- test/passes/expand-whens/bundle-init.fir | 6 +- test/passes/expand-whens/nested-whens.fir | 10 +- test/passes/expand-whens/one-when.fir | 10 +- test/passes/expand-whens/partial-init.fir | 6 +- test/passes/expand-whens/reg-dwc.fir | 4 +- test/passes/expand-whens/reg-dwoc.fir | 4 +- test/passes/expand-whens/reg-wdc.fir | 4 +- test/passes/expand-whens/reg-wdoc.fir | 8 +- test/passes/expand-whens/scoped-reg.fir | 6 +- test/passes/expand-whens/two-when.fir | 3 +- test/passes/expand-whens/wacc-wdc.fir | 3 +- test/passes/infer-types/gcd.fir | 27 +-- test/passes/infer-types/primops.fir | 52 +++--- test/passes/infer-widths/gcd.fir | 16 +- test/passes/infer-widths/simple.fir | 4 +- test/passes/inline/gcd.fir | 16 +- test/passes/jacktest/ALUTop.fir | 26 +-- test/passes/jacktest/Counter.fir | 8 +- test/passes/jacktest/EnableShiftRegister.fir | 18 +- test/passes/jacktest/LFSR16.fir | 12 +- test/passes/jacktest/MemorySearch.fir | 16 +- test/passes/jacktest/ModuleVec.fir | 4 +- test/passes/jacktest/Mul.fir | 2 +- test/passes/jacktest/RegisterVecShift.fir | 4 +- test/passes/jacktest/Stack.fir | 22 +-- test/passes/jacktest/Tbl.fir | 3 +- test/passes/jacktest/VendingMachine.fir | 6 +- test/passes/jacktest/gcd.fir | 10 +- test/passes/jacktest/risc.fir | 18 +- test/passes/lower-to-ground/accessor.fir | 15 +- test/passes/lower-to-ground/bundle-vecs.fir | 24 +-- test/passes/lower-to-ground/bundle.fir | 59 ++++--- test/passes/lower-to-ground/instance.fir | 8 +- test/passes/lower-to-ground/nested-vec.fir | 31 ++-- test/passes/lower-to-ground/register.fir | 18 +- test/passes/make-explicit-reset/mix-reset.fir | 29 ---- test/passes/resolve-genders/gcd.fir | 18 +- test/passes/resolve-genders/subbundle.fir | 4 +- test/passes/resolve-kinds/gcd.fir | 18 +- test/passes/split-exp/gcd.fir | 16 +- test/passes/to-flo/gcd.fir | 16 +- test/passes/to-verilog/gcd.fir | 17 +- 56 files changed, 696 insertions(+), 338 deletions(-) create mode 100644 notes/alpha.txt create mode 100644 test/errors/high-form/RemoveScope.fir create mode 100644 test/errors/high-form/SpecialChars.fir delete mode 100644 test/errors/high-form/WrongReset.fir create mode 100644 test/features/TwoClocks.fir delete mode 100644 test/passes/make-explicit-reset/mix-reset.fir diff --git a/Makefile b/Makefile index b0c200d5..6eda3cc3 100644 --- a/Makefile +++ b/Makefile @@ -52,7 +52,7 @@ units = ALUTop Datapath Control Core v = $(addsuffix .fir.v, $(units)) $(units): % : - firrtl -X verilog -i test/chisel3/$*.fir -o test/chisel3/$*.fir.v + firrtl -X verilog -i test/chisel3/$*.fir -o test/chisel3/$*.fir.v -p c scp test/chisel3/$*.fir.v adamiz@a5:/scratch/adamiz/firrtl-all/riscv-mini/generated-src/$*.v done: diff --git a/notes/alpha.txt b/notes/alpha.txt new file mode 100644 index 00000000..0f245bf7 --- /dev/null +++ b/notes/alpha.txt @@ -0,0 +1,77 @@ +========= RENAME STRATEGY ========= +Special chars ~!@#$%^*-_+=?/ get renamed to _XX, where XX is a hex representation of the symbol + +a_x +=> +a_XXx + +a_XXx +=> +a_XXXXx + +This guarantees all symbols use a subset of the character set + +Now, I need to rename duplicate symbols, so: + +wire x +when p + wire x + +=> + +wire x%0 +when p + wire x%1 + +We know that all new symbols are unique because they use a special character +At this point, all names are unique. + +-- Bundle Expansion -- +To deal with bundle expansion, use another different special character: + +wire x : {a,b} + +=> + +wire x#a +wire x#b + +-- Vector Expansion -- + +To deal with bundle expansion, use another different special character: + +wire x : UInt<1>[3] + +=> + +wire x$0 : UInt<1> +wire x$1 : UInt<1> +wire x$2 : UInt<1> + +-- Creating Temporaries -- +To deal with creating temporaries, use another different special character: + +node x = a + b * c +=> +node x!0 = b * c +node x!1 = a + x!0 +node x = x!1 + +Finally, to deal with backends that only use subsets of the special characters, do another rename step to remove special characters (must remove $ again!) + +ASCII Hex +_ 5F __ +~ 7E _A +! 21 _B +@ 40 _C +# 23 _D +$ 24 _E +% 25 _F +^ 5E _G +* 2A _H +- 2D _I ++ 2B _J += 3D _K +? 3F _L +/ 2F _M + diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index c458f1e1..b87c654e 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -12,10 +12,11 @@ public defstruct StandardFlo <: Compiler : file: String with: (as-method => true) public defmethod passes (c:StandardFlo) -> List : to-list $ [ - CheckHighForm(expand-delin) + RemoveSpecialChars() + RemoveScopes() + CheckHighForm() ;; TempElimination() ToWorkingIR() - ;; MakeExplicitReset() ResolveKinds() CheckKinds() InferTypes() @@ -31,9 +32,8 @@ public defmethod passes (c:StandardFlo) -> List : Inline() SplitExp() ToRealIR() - SpecialRename(`#,`_) - SpecialRename(`$,`::) - CheckHighForm(`::) + RemoveSpecialChars() + CheckHighForm() CheckLowForm() Flo(file(c)) ] @@ -42,7 +42,9 @@ public defstruct StandardVerilog <: Compiler : file: String with: (as-method => true) public defmethod passes (c:StandardVerilog) -> List : to-list $ [ - CheckHighForm(expand-delin) + RemoveSpecialChars() + RemoveScopes() + CheckHighForm() TempElimination() ToWorkingIR() ;; MakeExplicitReset() @@ -60,9 +62,8 @@ public defmethod passes (c:StandardVerilog) -> List : Pad() SplitExp() ToRealIR() - SpecialRename(`#,`_) - SpecialRename(`$,`__) - CheckHighForm(`__) + RemoveSpecialChars() + CheckHighForm() CheckLowForm() Verilog(file(c)) ] diff --git a/src/main/stanza/custom-compiler.stanza b/src/main/stanza/custom-compiler.stanza index 91732f22..4d63a173 100644 --- a/src/main/stanza/custom-compiler.stanza +++ b/src/main/stanza/custom-compiler.stanza @@ -14,7 +14,9 @@ public defstruct InstrumentedVerilog <: Compiler : public defmethod passes (c:InstrumentedVerilog) -> List : to-list $ [ WhenCoverage(args(c)[0],args(c)[1]) - CheckHighForm(expand-delin) + RemoveSpecialChars() + RemoveScopes() + CheckHighForm() TempElimination() ToWorkingIR() ;; MakeExplicitReset() @@ -31,8 +33,8 @@ public defmethod passes (c:InstrumentedVerilog) -> List : InferWidths() SplitExp() ToRealIR() - SpecialRename(`#,`_) - CheckHighForm(expand-delin) + RemoveSpecialChars() + CheckHighForm() CheckLowForm() Verilog(file(c)) ] diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza index b92939d7..608b47d2 100644 --- a/src/main/stanza/errors.stanza +++ b/src/main/stanza/errors.stanza @@ -39,9 +39,8 @@ defpackage firrtl/errors : ; * Width sizes are positive ; * Primops have the correct number of arguments -public defstruct CheckHighForm <: Pass : - sym : Symbol -public defmethod pass (b:CheckHighForm) -> (Circuit -> Circuit) : check-high-form{_,sym(b)} +public defstruct CheckHighForm <: Pass +public defmethod pass (b:CheckHighForm) -> (Circuit -> Circuit) : check-high-form public defmethod name (b:CheckHighForm) -> String : "High Form Check" public defmethod short-name (b:CheckHighForm) -> String : "high-form-check" @@ -240,7 +239,7 @@ defn check-high-form-primop (e:DoPrim, errors:Vector,info:FileInf BITS-SELECT-OP : correct-num(1,2) ;--------------- Check High Form Pass ------------------- -public defn check-high-form (c:Circuit,sym:Symbol) -> Circuit : +public defn check-high-form (c:Circuit) -> Circuit : val errors = Vector() defn check-valid-loc (info:FileInfo,e:Expression) -> False : @@ -334,7 +333,6 @@ public defn check-high-form (c:Circuit,sym:Symbol) -> Circuit : map(check-high-form-t{info(p),_},type(p)) map(check-high-form-w{info(p),_},type(p)) - names[`reset] = true match(m) : (m:ExModule) : false (m:InModule) : check-high-form-s(body(m),names) diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza index b9d2cee4..b37e974f 100644 --- a/src/main/stanza/firrtl-ir.stanza +++ b/src/main/stanza/firrtl-ir.stanza @@ -5,8 +5,11 @@ defpackage firrtl/ir2 : public defmulti info! (x:?) -> FileInfo public defmethod info! (x:?) : FileInfo() -public val expand-delin = `$ -public val gen-delin = `# +public val vector-expand-delin = `_ +public val bundle-expand-delin = `_ +public val scope-delin = `% +public val temp-delin = `! +public val inline-delin = `^ public definterface PortDirection public val INPUT = new PortDirection diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index f844d7cc..99679cf6 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -9,10 +9,9 @@ defpackage firrtl/passes : ;============== Pass List ================ public val standard-passes = to-list $ [ - CheckHighForm(expand-delin) + CheckHighForm() TempElimination() ToWorkingIR() - ;MakeExplicitReset() ResolveKinds() CheckKinds() InferTypes() @@ -282,6 +281,155 @@ defmethod map (f: Type -> Type, e: WSubfield) : defmethod map (f: Type -> Type, e: WIndex) : WIndex(exp(e), value(e), f(type(e)), gender(e)) +;================= Remove Special Characters ======================== +; Returns a new Circuit where all names have all special characters +; removed, except _. + +public defstruct RemoveSpecialChars <: Pass +public defmethod pass (b:RemoveSpecialChars) -> (Circuit -> Circuit) : remove-special-chars +public defmethod name (b:RemoveSpecialChars) -> String : "Remove Special Characters" +public defmethod short-name (b:RemoveSpecialChars) -> String : "rem-spec-chars" + +;------------ Helper Functions ------------- + +defn get-new-string (n:Char) -> String : + switch {n == _} : + '_' : "__" + '~' : "_A" + '!' : "_B" + '@' : "_C" + '#' : "_D" + '$' : "_E" + '%' : "_F" + '^' : "_G" + '*' : "_H" + '-' : "_I" + '+' : "_J" + '=' : "_K" + '?' : "_L" + '/' : "_M" + else : to-string(n) + +;------------ Pass ------------------ + +defn remove-special-chars (c:Circuit) : + defn rename (n:Symbol) -> Symbol : + val n* = Vector() + for c in to-string(n) do : + add(n*,get-new-string(c)) + symbol-join(n*) + defn rename-t (t:Type) -> Type : + match(map(rename-t,t)) : + (t:BundleType) : BundleType $ + for f in fields(t) map : + Field(rename(name(f)),flip(f),type(f)) + (e) : e + defn rename-e (e:Expression) -> Expression : + map{rename-t,_} $ match(map(rename-e,e)) : + (e:Ref) : Ref(rename(name(e)),type(e)) + (e:Subfield) : Subfield(exp(e),rename(name(e)),type(e)) + (e) : e + defn rename-s (s:Stmt) -> Stmt : + map{rename-t,_} $ match(map(rename-e,s)) : + (s:DefWire) : DefWire(info(s),rename(name(s)),type(s)) + (s:DefRegister) : DefRegister(info(s),rename(name(s)),type(s),clock(s),reset(s)) + (s:DefInstance) : DefInstance(info(s),rename(name(s)),module(s)) + (s:DefMemory) : DefMemory(info(s),rename(name(s)),type(s),seq?(s),clock(s)) + (s:DefNode) : DefNode(info(s),rename(name(s)),value(s)) + (s:DefAccessor) : DefAccessor(info(s),rename(name(s)),source(s),index(s),acc-dir(s)) + (s) : map(rename-s,s) + + Circuit(info(c),modules*, main(c)) where : + val modules* = + for m in modules(c) map : + match(m) : + (m:InModule) : + val ports* = for p in ports(m) map : + Port(info(p),rename(name(p)),direction(p),rename-t(type(p))) + InModule(info(m),rename(name(m)), ports*, rename-s(body(m))) + (m:ExModule) : m + +;================= Remove Scopes ======================== +; Returns a new Circuit where duplicate names have been +; renamed. + +public defstruct RemoveScopes <: Pass +public defmethod pass (b:RemoveScopes) -> (Circuit -> Circuit) : remove-scopes +public defmethod name (b:RemoveScopes) -> String : "Remove Scopes" +public defmethod short-name (b:RemoveScopes) -> String : "rem-scopes" + +;------------ Helper Functions ------------- + +defn lookup (n:Symbol, env:Vector>) -> Symbol : lookup(n,env,length(env) - 1) +defn lookup (n:Symbol, env:Vector>, index:Int) -> Symbol : + if index < 0 : n + else : + if not key?(env[index],n) : lookup(n,env,index - 1) + else : symbol-join([n scope-delin (env[index])[n]]) + +;------------ Pass ------------------ + +defn remove-scopes (c:Circuit) : + defn remove-scopes (m:InModule) : + val occurrences = HashTable(symbol-hash) + val uses = HashTable(symbol-hash) + defn rename (n:Symbol,env:Vector>) -> Symbol : + if occurrences[n] > 1 : + val i = get?(uses,n,0) + uses[n] = i + 1 + env[length(env) - 1][n] = i + symbol-join([n `% i]) + else : n + defn build-s (s:Stmt) : + match(s) : + (s:DefWire|DefRegister|DefInstance|DefMemory|DefNode|DefAccessor) : + occurrences[name(s)] = get?(occurrences,name(s),0) + 1 + (s) : do(build-s,s) + defn remove-scopes-e (e:Expression,env:Vector>) : + match(map(remove-scopes-e{_,env},e)) : + (e:Ref) : Ref(lookup(name(e),env),type(e)) + (e) : e + defn remove-scopes-s (s:Stmt,env:Vector>) -> Stmt : + match(map(remove-scopes-e{_,env},s)) : + (s:DefWire) : DefWire(info(s),rename(name(s),env),type(s)) + (s:DefRegister) : DefRegister(info(s),rename(name(s),env),type(s),clock(s),reset(s)) + (s:DefInstance) : DefInstance(info(s),rename(name(s),env),module(s)) + (s:DefMemory) : DefMemory(info(s),rename(name(s),env),type(s),seq?(s),clock(s)) + (s:DefNode) : DefNode(info(s),rename(name(s),env),value(s)) + (s:DefAccessor) : DefAccessor(info(s),rename(name(s),env),source(s),index(s),acc-dir(s)) + (s:Conditionally) : + add(env,HashTable(symbol-hash)) + val conseq* = remove-scopes-s(conseq(s),env) + pop(env) + + add(env,HashTable(symbol-hash)) + val alt* = remove-scopes-s(alt(s),env) + pop(env) + Conditionally(info(s),pred(s),conseq*,alt*) + (s) : map(remove-scopes-s{_,env},s) + + ;build occurrences table + for p in ports(m) do : + occurrences[name(p)] = get?(occurrences,name(p),0) + 1 + build-s(body(m)) + + ;rename + val env = Vector>() + add(env,HashTable(symbol-hash)) + val ports* = + for p in ports(m) map : + Port(info(p),rename(name(p),env),direction(p),type(p)) + val body* = remove-scopes-s(body(m),env) + + InModule(info(m),name(m), ports*, body*) + + Circuit(info(c),modules*, main(c)) where : + val modules* = + for m in modules(c) map : + match(m) : + (m:InModule) : remove-scopes(m) + (m:ExModule) : m + ;================= Temporary Variable Elimination ======================== ; Returns a new Circuit where temporary variables are removed and returns ; the resulting nested expression @@ -771,18 +919,19 @@ defn index-of-elem (t:BundleType, s:Symbol) -> Int : error("Shouldn't be here") defn generate-entry (n:Symbol,t:Type) -> List : - defn uniquify (n*:Symbol) -> Symbol : symbol-join([n expand-delin n*]) + defn v-uniquify (n*:Symbol) -> Symbol : symbol-join([n vector-expand-delin n*]) + defn b-uniquify (n*:Symbol) -> Symbol : symbol-join([n bundle-expand-delin n*]) match(t) : (t:BundleType) : for f in fields(t) map-append : val es = generate-entry(name(f),type(f)) for e in es map : - NTF(uniquify(name(e)),type(e),flip(e) * flip(f)) + NTF(b-uniquify(name(e)),type(e),flip(e) * flip(f)) (t:VectorType) : for i in 0 to size(t) map-append : val es = generate-entry(to-symbol(i),type(t)) for e in es map : - NTF(uniquify(name(e)),type(e),flip(e)) + NTF(v-uniquify(name(e)),type(e),flip(e)) (t) : list $ NTF(n,t,DEFAULT) defn expand-expr (e:Expression) -> List : @@ -986,9 +1135,9 @@ defn expand-connect-indexed-stmt (s: Stmt,sh:HashTable) -> Stmt : DoPrim(EQUAL-OP,list(e1,e2),List(),UIntType(UnknownWidth())) defn get-name (e:Expression) -> Symbol : match(e) : - (e:WRef) : symbol-join([name(e) gen-delin]) - (e:WSubfield) : symbol-join([get-name(exp(e)) `. name(e) gen-delin]) - (e:WIndex) : symbol-join([get-name(exp(e)) `. to-symbol(value(e)) gen-delin]) + (e:WRef) : symbol-join([name(e) temp-delin]) + (e:WSubfield) : symbol-join([get-name(exp(e)) `. name(e) temp-delin]) + (e:WIndex) : symbol-join([get-name(exp(e)) `. to-symbol(value(e)) temp-delin]) (e) : `T match(s) : (s:ConnectToIndexed) : Begin $ @@ -1857,17 +2006,17 @@ defn inline-instances (c:Circuit) : (e:WSubfield) : match(kind(exp(e) as WRef)) : (k:InstanceKind) : - WRef(symbol-join([name(exp(e) as WRef) expand-delin name(e)]),type(e),k,gender(e)) + WRef(symbol-join([name(exp(e) as WRef) inline-delin name(e)]),type(e),k,gender(e)) (k:MemKind) : e (e) : e - defn rename (ref:Symbol,n:Symbol) -> Symbol : symbol-join([n expand-delin ref]) + defn rename (ref:Symbol,n:Symbol) -> Symbol : symbol-join([n inline-delin ref]) defn rename-e (e:Expression,n:Symbol) -> Expression : match(map(rename-e{_,n},e)) : (e:WRef) : WRef(rename(name(e),n),type(e),kind(e),gender(e)) (e:WSubfield) : match(kind(exp(e) as WRef)) : (k:InstanceKind) : - WRef(symbol-join([name(exp(e) as WRef) expand-delin name(e)]),type(e),k,gender(e)) + WRef(symbol-join([name(exp(e) as WRef) inline-delin name(e)]),type(e),k,gender(e)) (k:MemKind) : e (e) : e defn rename-s (s:Stmt,n:Symbol) -> Stmt : @@ -1911,7 +2060,7 @@ defn split-exp (c:Circuit) : if not all-same-type? : val n* = if n typeof False : firrtl-gensym(`T,sh) - else : firrtl-gensym(symbol-join([n as Symbol gen-delin]),sh) + else : firrtl-gensym(symbol-join([n as Symbol temp-delin]),sh) add(v,DefNode(info,n*,e)) WRef(n*,type(e),NodeKind(),UNKNOWN-GENDER) else : e @@ -1923,10 +2072,12 @@ defn split-exp (c:Circuit) : (s:Conditionally) : add(v,map(split-exp-e{_,full-name(loc(conseq(s) as Connect)),info(s)},s)) do(f,s) - (s:Connect) : - match(loc(s)) : - (e) : add(v,map(split-exp-e{_,full-name(loc(s)),info(s)},s)) - (s:DefNode) : add(v,map(split-exp-e{_,name(s),info(s)},s)) + (s:Connect) : + val exp* = map(split-exp-e{_,full-name(loc(s)),info(s)},exp(s)) + add(v,Connect(info(s),loc(s),exp(s))) + (s:DefNode) : + val exp* = map(split-exp-e{_,name(s),info(s)},value(s)) + add(v,DefNode(info(s),name(s),exp*)) (s) : add(v,map(split-exp-e{_,false,info(s)},s)) false diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index 23591f45..29112271 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -249,6 +249,7 @@ defn emit-module (m:InModule) : OUTPUT : print-all([port-indent "output " get-width(type(p)) " " name(p) end]) add(assigns,["assign " name(p) " = " emit(cons[name(p)]) ";"]) + if length(ports(m)) == 0 : print(");\n") for w in wires do : print(" ") diff --git a/test/errors/high-form/Flip-Mem.fir b/test/errors/high-form/Flip-Mem.fir index 5725aa90..62eba530 100644 --- a/test/errors/high-form/Flip-Mem.fir +++ b/test/errors/high-form/Flip-Mem.fir @@ -4,5 +4,6 @@ circuit Flip-Mem : module Flip-Mem : - cmem m-c : {x : UInt<3>, flip y : UInt<5>}[10] - smem m-s : {x : UInt<3>, flip y : UInt<5>}[10] + input clk : Clock + cmem m-c : {x : UInt<3>, flip y : UInt<5>}[10], clk + smem m-s : {x : UInt<3>, flip y : UInt<5>}[10], clk diff --git a/test/errors/high-form/RemoveScope.fir b/test/errors/high-form/RemoveScope.fir new file mode 100644 index 00000000..1d9f7ef6 --- /dev/null +++ b/test/errors/high-form/RemoveScope.fir @@ -0,0 +1,17 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s +; CHECK: Done! + +circuit Top : + module Top : + wire x : UInt<1> + node p = UInt(1) + when p : + wire x : UInt<1> + x := UInt(1) + node y = add(x,UInt(1)) + else : + wire x : UInt<1> + x := UInt(1) + node z = add(x,UInt(1)) + x := UInt(1) + node w = add(x,UInt(1)) diff --git a/test/errors/high-form/SpecialChars.fir b/test/errors/high-form/SpecialChars.fir new file mode 100644 index 00000000..f224ce68 --- /dev/null +++ b/test/errors/high-form/SpecialChars.fir @@ -0,0 +1,35 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s +; CHECK: Done! + +circuit Top : + module Top : + wire x : UInt<1> + x := UInt(1) + wire x~y : UInt<2> + x~y := UInt(1) + wire x!y : UInt<2> + x!y := UInt(1) + wire x@y : UInt<2> + x@y := UInt(1) + wire x#y : UInt<2> + x#y := UInt(1) + wire x%y : UInt<2> + x%y := UInt(1) + wire x^y : UInt<2> + x^y := UInt(1) + wire x*y : UInt<2> + x*y := UInt(1) + wire x-y : UInt<2> + x-y := UInt(1) + wire x_y : UInt<2> + x_y := UInt(1) + wire x+y : UInt<2> + x+y := UInt(1) + wire x=y : UInt<2> + x=y := UInt(1) + wire x?y : UInt<2> + x?y := UInt(1) + wire x/y : UInt<2> + x/y := UInt(1) + + diff --git a/test/errors/high-form/WrongReset.fir b/test/errors/high-form/WrongReset.fir deleted file mode 100644 index adeadee6..00000000 --- a/test/errors/high-form/WrongReset.fir +++ /dev/null @@ -1,15 +0,0 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s - -; CHECK: Module Top has a reset that is not of type UInt<1>. -; CHECK: Module B has a reset that is not of type UInt<1>. -; CHECK: Module C has a reset that is not of type UInt<1>. - -circuit Top : - module Top : - input reset : SInt<1> - module B : - input reset : UInt - module C : - output reset : UInt<1> - - diff --git a/test/features/TwoClocks.fir b/test/features/TwoClocks.fir new file mode 100644 index 00000000..cbbb01f1 --- /dev/null +++ b/test/features/TwoClocks.fir @@ -0,0 +1,21 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s +circuit Top : + module Top : + input clk1 : Clock + input clk2 : Clock + input reset1 : UInt<1> + input reset2 : UInt<1> + reg src : UInt<10>, clk1, reset1 + reg sink : UInt<10>, clk2, reset2 + + onreset src := UInt(0) + src := addw(src,UInt(1)) + + reg sync_A : UInt<10>, clk2, reset2 + sync_A := src + reg sync_B : UInt<10>, clk2, reset2 + sync_B := sync_A + + sink := sync_B + +;CHECK: Done! diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir index ea453ab1..38bd6fe5 100644 --- a/test/passes/expand-connect-indexed/bundle-vecs.fir +++ b/test/passes/expand-connect-indexed/bundle-vecs.fir @@ -4,27 +4,32 @@ circuit top : module top : wire i : UInt + i := UInt(1) wire j : UInt + j := UInt(1) wire a : { x : UInt<32>, flip y : UInt<32> }[2] - ; CHECK: wire a$0$x : UInt<32> - ; CHECK: wire a$0$y : UInt<32> - ; CHECK: wire a$1$x : UInt<32> - ; CHECK: wire a$1$y : UInt<32> + a[0].x := UInt(1) + a[0].y := UInt(1) + a[1].x := UInt(1) + a[1].y := UInt(1) + ; CHECK: wire a_0_x : UInt<32> + ; CHECK: wire a_0_y : UInt<32> + ; CHECK: wire a_1_x : UInt<32> + ; CHECK: wire a_1_y : UInt<32> + infer accessor b = a[i] - ; CHECK: wire b$x : UInt<32> - ; CHECK: wire b$y : UInt<32> - ; CHECK: b$x := a$0$x - ; CHECK: node i#0 = i - ; CHECK: when eq(i#0, UInt(1)) : - ; CHECK: b$x := a$1$x - ; CHECK: node i#1 = i - ; CHECK: when eq(i#1, UInt(0)) : - ; CHECK: a$0$y := b$y - ; CHECK: when eq(i#1, UInt(1)) : - ; CHECK: a$1$y := b$y + ; CHECK: wire b_x : UInt<32> + ; CHECK: wire b_y : UInt<32> + ; CHECK: b_x := a_0_x + ; CHECK: node i!0 = i + ; CHECK: when eq(i!0, UInt(1)) : b_x := a_1_x + ; CHECK: node i!1 = i + ; CHECK: when eq(i!1, UInt(0)) : a_0_y := b_y + ; CHECK: when eq(i!1, UInt(1)) : a_1_y := b_y j := b.x + b.y := UInt(1) ; CHECK: Finished Expand Indexed Connects diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir index 261ebf02..10da47cf 100644 --- a/test/passes/expand-whens/bundle-init.fir +++ b/test/passes/expand-whens/bundle-init.fir @@ -2,7 +2,9 @@ ; CHECK: Expand Whens circuit top : module top : - reg r : { x : UInt, flip y : UInt} + input clk : Clock + input reset : UInt<1> + reg r : { x : UInt, flip y : UInt},clk,reset wire a : UInt wire b : UInt wire w : { x : UInt, flip y : UInt} @@ -13,7 +15,7 @@ circuit top : w.y := a r.x := a r.y := b - on-reset r := w + onreset r := w ; CHECK: when UInt(1) : r$x := mux(reset, w$x, a) ; CHECK: when UInt(1) : r$y := b diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir index 4d23a549..c81ca485 100644 --- a/test/passes/expand-whens/nested-whens.fir +++ b/test/passes/expand-whens/nested-whens.fir @@ -2,9 +2,11 @@ ; CHECK: Expand Whens circuit top : module top : + input clk : Clock + input reset : UInt<1> wire p : UInt wire q : UInt - reg r : UInt + reg r : UInt, clk, reset wire a : UInt wire b : UInt wire x : UInt @@ -20,12 +22,12 @@ circuit top : z := UInt(1) w := UInt(1) - on-reset r := w + onreset r := w when p : - on-reset r := x + onreset r := x r := a when q : - on-reset r := y + onreset r := y r := b r := z ; CHECK: when UInt(1) : r := mux(reset, mux(q, y, mux(p, x, w)), z) diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir index 4e6ea1e5..1332395c 100644 --- a/test/passes/expand-whens/one-when.fir +++ b/test/passes/expand-whens/one-when.fir @@ -3,16 +3,18 @@ ; CHECK: Expand Whens circuit top : module top : - cmem m : UInt<1>[2] + input clk : Clock + input reset : UInt<1> + cmem m : UInt<1>[2], clk wire i : UInt<1> wire p : UInt<1> wire j : UInt<1> j := UInt(1) - reg r : UInt<1> + reg r : UInt<1>, clk, reset p := j when p : - on-reset r := i + onreset r := i infer accessor a = m[i] i := a infer accessor b = m[i] @@ -27,7 +29,7 @@ circuit top : p := i when e : p := p - on-reset r := p + onreset r := p r := p diff --git a/test/passes/expand-whens/partial-init.fir b/test/passes/expand-whens/partial-init.fir index 03b1f965..f752eccd 100644 --- a/test/passes/expand-whens/partial-init.fir +++ b/test/passes/expand-whens/partial-init.fir @@ -3,7 +3,9 @@ ; CHECK: Expand Whens circuit top : module top : - reg r : UInt<1>[10] + input clk : Clock + input reset : UInt<1> + reg r : UInt<1>[10],clk,reset r[0] := UInt(1) r[1] := UInt(1) r[2] := UInt(1) @@ -14,6 +16,6 @@ circuit top : r[7] := UInt(1) r[8] := UInt(1) r[9] := UInt(1) - on-reset r[3] := UInt(0) + onreset r[3] := UInt(0) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir index 01347fdd..ac0f405b 100644 --- a/test/passes/expand-whens/reg-dwc.fir +++ b/test/passes/expand-whens/reg-dwc.fir @@ -1,9 +1,11 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s circuit top : module top : + input clk : Clock + input reset : UInt<1> wire p : UInt p := UInt(1) - reg r : UInt + reg r : UInt,clk,reset when p : r := UInt(20) diff --git a/test/passes/expand-whens/reg-dwoc.fir b/test/passes/expand-whens/reg-dwoc.fir index 521e1710..ab6f4915 100644 --- a/test/passes/expand-whens/reg-dwoc.fir +++ b/test/passes/expand-whens/reg-dwoc.fir @@ -1,9 +1,11 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s circuit top : module top : + input clk : Clock + input reset : UInt<1> wire p : UInt p := UInt(1) - reg r : UInt + reg r : UInt,clk,reset when p : on-reset r := UInt(10) r := UInt(20) diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir index df6c7034..03f5ade9 100644 --- a/test/passes/expand-whens/reg-wdc.fir +++ b/test/passes/expand-whens/reg-wdc.fir @@ -1,10 +1,12 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s circuit top : module top : + input clk : Clock + input reset : UInt<1> wire p : UInt p := UInt(1) when p : - reg r : UInt + reg r : UInt,clk,reset r := UInt(20) ; CHECK: Expand Whens diff --git a/test/passes/expand-whens/reg-wdoc.fir b/test/passes/expand-whens/reg-wdoc.fir index ad191a01..1de6d8f4 100644 --- a/test/passes/expand-whens/reg-wdoc.fir +++ b/test/passes/expand-whens/reg-wdoc.fir @@ -1,11 +1,13 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s circuit top : module top : + input clk : Clock + input reset : UInt<1> wire p : UInt p := UInt(1) when p : - reg r : UInt - on-reset r := UInt(10) + reg r : UInt,clk,reset + onreset r := UInt(10) r := UInt(20) ; CHECK: Expand Whens @@ -13,7 +15,7 @@ circuit top : ; CHECK: circuit top : ; CHECK: module top : ; CHECK: wire p : UInt -; CHECK: reg r : UInt +; CHECK: reg r : UInt, clk, reset ; CHECK: p := UInt(1) ; CHECK: r := mux(reset, UInt(10), UInt(20)) diff --git a/test/passes/expand-whens/scoped-reg.fir b/test/passes/expand-whens/scoped-reg.fir index d119932f..aec64871 100644 --- a/test/passes/expand-whens/scoped-reg.fir +++ b/test/passes/expand-whens/scoped-reg.fir @@ -1,11 +1,13 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s circuit top : module top : + input clk : Clock + input reset : UInt<1> wire p : UInt p := UInt(1) when p : - reg r : UInt - on-reset r := UInt(10) + reg r : UInt, clk, reset + onreset r := UInt(10) r := UInt(20) ; CHECK: Expand Whens diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir index b6c98263..2203f25e 100644 --- a/test/passes/expand-whens/two-when.fir +++ b/test/passes/expand-whens/two-when.fir @@ -3,7 +3,8 @@ ; CHECK: Expand Whens circuit top : module top : - cmem m :{ x : UInt<1>, y : UInt<1> }[2] + input clk : Clock + cmem m :{ x : UInt<1>, y : UInt<1> }[2], clk wire i : UInt<1> i := UInt(1) wire p : UInt<1> diff --git a/test/passes/expand-whens/wacc-wdc.fir b/test/passes/expand-whens/wacc-wdc.fir index 6e407178..653a3e88 100644 --- a/test/passes/expand-whens/wacc-wdc.fir +++ b/test/passes/expand-whens/wacc-wdc.fir @@ -1,8 +1,9 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s circuit top : module top : + input clk : Clock wire p : UInt - cmem m : UInt<4>[10] + cmem m : UInt<4>[10], clk p := UInt(1) when p : write accessor a = m[UInt(3)] diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir index 6bceda5c..735a69c9 100644 --- a/test/passes/infer-types/gcd.fir +++ b/test/passes/infer-types/gcd.fir @@ -6,30 +6,31 @@ circuit top : input x : UInt input y : UInt output z : UInt - z := sub-wrap(x, y) - ;CHECK: z@ := sub-wrap(x@, y@)@ + z := subw(x, y) + ;CHECK: z@ := subw(x@, y@)@ module gcd : input a : UInt<16> input b : UInt<16> input e : UInt<1> + input clk : Clock + input reset : UInt<1> output z : UInt<16> output v : UInt<1> - reg x : UInt - reg y : UInt + reg x : UInt,clk,reset + reg y : UInt,clk,reset ; CHECK: reg x : UInt - on-reset x := UInt(0) - on-reset y := UInt(42) + onreset x := UInt(0) + onreset y := UInt(42) when gt(x, y) : ;CHECK: when gt(x@, y@)@ : inst s of subtracter - ;CHECK: inst s of subtracter@, flip y : UInt@, z : UInt@, flip reset : UInt<1>@}> + ;CHECK: inst s of subtracter@, flip y : UInt@, z : UInt@}> s.x := x s.y := y x := s.z - ;CHECK: s@, flip y : UInt@, z : UInt@, flip reset : UInt<1>@}>.reset@ := reset@ - ;CHECK: s@, flip y : UInt@, z : UInt@, flip reset : UInt<1>@}>.x@ := x@ - ;CHECK: s@, flip y : UInt@, z : UInt@, flip reset : UInt<1>@}>.y@ := y@ - ;CHECK: x@ := s@, flip y : UInt@, z : UInt@, flip reset : UInt<1>@}>.z@ + ;CHECK: s@, flip y : UInt@, z : UInt@}>.x@ := x@ + ;CHECK: s@, flip y : UInt@, z : UInt@}>.y@ := y@ + ;CHECK: x@ := s@, flip y : UInt@, z : UInt@}>.z@ else : inst s2 of subtracter s2.x := x @@ -44,10 +45,14 @@ circuit top : module top : input a : UInt<16> input b : UInt<16> + input clk : Clock + input reset : UInt<1> output z : UInt inst i of gcd i.a := a i.b := b + i.clk := clk + i.reset := reset i.e := UInt(1) z := i.z diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir index 05e9adf8..61656e9c 100644 --- a/test/passes/infer-types/primops.fir +++ b/test/passes/infer-types/primops.fir @@ -51,17 +51,17 @@ circuit top : node yrem = rem(c, b) ;CHECK: node yrem = rem(c@, b@)@ node zrem = rem(c, d) ;CHECK: node zrem = rem(c@, d@)@ - node vadd-wrap = add-wrap(a, c) ;CHECK: node vadd-wrap = add-wrap(a@, c@)@ - node wadd-wrap = add-wrap(a, b) ;CHECK: node wadd-wrap = add-wrap(a@, b@)@ - node xadd-wrap = add-wrap(a, d) ;CHECK: node xadd-wrap = add-wrap(a@, d@)@ - node yadd-wrap = add-wrap(c, b) ;CHECK: node yadd-wrap = add-wrap(c@, b@)@ - node zadd-wrap = add-wrap(c, d) ;CHECK: node zadd-wrap = add-wrap(c@, d@)@ - - node vsub-wrap = sub-wrap(a, c) ;CHECK: node vsub-wrap = sub-wrap(a@, c@)@ - node wsub-wrap = sub-wrap(a, b) ;CHECK: node wsub-wrap = sub-wrap(a@, b@)@ - node xsub-wrap = sub-wrap(a, d) ;CHECK: node xsub-wrap = sub-wrap(a@, d@)@ - node ysub-wrap = sub-wrap(c, b) ;CHECK: node ysub-wrap = sub-wrap(c@, b@)@ - node zsub-wrap = sub-wrap(c, d) ;CHECK: node zsub-wrap = sub-wrap(c@, d@)@ + node vaddw = addw(a, c) ;CHECK: node vaddw = addw(a@, c@)@ + node waddw = addw(a, b) ;CHECK: node waddw = addw(a@, b@)@ + node xaddw = addw(a, d) ;CHECK: node xaddw = addw(a@, d@)@ + node yaddw = addw(c, b) ;CHECK: node yaddw = addw(c@, b@)@ + node zaddw = addw(c, d) ;CHECK: node zaddw = addw(c@, d@)@ + + node vsubw = subw(a, c) ;CHECK: node vsubw = subw(a@, c@)@ + node wsubw = subw(a, b) ;CHECK: node wsubw = subw(a@, b@)@ + node xsubw = subw(a, d) ;CHECK: node xsubw = subw(a@, d@)@ + node ysubw = subw(c, b) ;CHECK: node ysubw = subw(c@, b@)@ + node zsubw = subw(c, d) ;CHECK: node zsubw = subw(c@, d@)@ node vlt = lt(a, c) ;CHECK: node vlt = lt(a@, c@)@ node wlt = lt(a, b) ;CHECK: node wlt = lt(a@, b@)@ @@ -103,13 +103,13 @@ circuit top : node wpad = pad(a, 10) ;CHECK: node wpad = pad(a@, 10)@ node zpad = pad(c, 10) ;CHECK: node zpad = pad(c@, 10)@ - node vas-UInt = as-UInt(d) ;CHECK: node vas-UInt = as-UInt(d@)@ - node was-UInt = as-UInt(a) ;CHECK: node was-UInt = as-UInt(a@)@ - node zas-UInt = as-UInt(c) ;CHECK: node zas-UInt = as-UInt(c@)@ + node vasUInt = asUInt(d) ;CHECK: node vasUInt = asUInt(d@)@ + node wasUInt = asUInt(a) ;CHECK: node wasUInt = asUInt(a@)@ + node zasUInt = asUInt(c) ;CHECK: node zasUInt = asUInt(c@)@ - node vas-SInt = as-SInt(a) ;CHECK: node vas-SInt = as-SInt(a@)@ - node was-SInt = as-SInt(a) ;CHECK: node was-SInt = as-SInt(a@)@ - node zas-SInt = as-SInt(c) ;CHECK: node zas-SInt = as-SInt(c@)@ + node vasSInt = asSInt(a) ;CHECK: node vasSInt = asSInt(a@)@ + node wasSInt = asSInt(a) ;CHECK: node wasSInt = asSInt(a@)@ + node zasSInt = asSInt(c) ;CHECK: node zasSInt = asSInt(c@)@ node vshl = shl(a, 10) ;CHECK: node vshl = shl(a@, 10)@ node wshl = shl(a, 10) ;CHECK: node wshl = shl(a@, 10)@ @@ -127,23 +127,23 @@ circuit top : node wshr = shr(a, 10) ;CHECK: node wshr = shr(a@, 10)@ node zshr = shr(c, 10) ;CHECK: node zshr = shr(c@, 10)@ - node vconvert = convert(a) ;CHECK: node vconvert = convert(a@)@ - node wconvert = convert(a) ;CHECK: node wconvert = convert(a@)@ - node zconvert = convert(c) ;CHECK: node zconvert = convert(c@)@ + node vcvt = cvt(a) ;CHECK: node vcvt = cvt(a@)@ + node wcvt = cvt(a) ;CHECK: node wcvt = cvt(a@)@ + node zcvt = cvt(c) ;CHECK: node zcvt = cvt(c@)@ node vneg = neg(a) ;CHECK: node vneg = neg(a@)@ node wneg = neg(a) ;CHECK: node wneg = neg(a@)@ node zneg = neg(c) ;CHECK: node zneg = neg(c@)@ - node uand = bit-and(a, b) ;CHECK: node uand = bit-and(a@, b@)@ - node vor = bit-or(a, b) ;CHECK: node vor = bit-or(a@, b@)@ - node wxor = bit-xor(a, b) ;CHECK: node wxor = bit-xor(a@, b@)@ + node uand = and(a, b) ;CHECK: node uand = and(a@, b@)@ + node vor = or(a, b) ;CHECK: node vor = or(a@, b@)@ + node wxor = xor(a, b) ;CHECK: node wxor = xor(a@, b@)@ node xcat = cat(a, b) ;CHECK: node xcat = cat(a@, b@)@ node ybit = bit(a, 0) ;CHECK: node ybit = bit(a@, 0)@ node zbits = bits(a, 2, 0) ;CHECK: node zbits = bits(a@, 2, 0)@ - node uand-reduce = bit-and-reduce(a, b, a) ;CHECK: node uand-reduce = bit-and-reduce(a@, b@, a@)@ - node uor-reduce = bit-or-reduce(a, b, a) ;CHECK: node uor-reduce = bit-or-reduce(a@, b@, a@)@ - node uxor-reduce = bit-xor-reduce(a, b, a) ;CHECK: node uxor-reduce = bit-xor-reduce(a@, b@, a@)@ + node uandr = andr(a, b, a) ;CHECK: node uandr = andr(a@, b@, a@)@ + node uorr = orr(a, b, a) ;CHECK: node uorr = orr(a@, b@, a@)@ + node uxorr = xorr(a, b, a) ;CHECK: node uxorr = xorr(a@, b@, a@)@ ;CHECK: Finished Infer Types diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir index 9e4bf0f5..efed25ad 100644 --- a/test/passes/infer-widths/gcd.fir +++ b/test/passes/infer-widths/gcd.fir @@ -6,17 +6,19 @@ circuit top : input x : UInt input y : UInt output q : UInt - q := sub-wrap(x, y) + q := subw(x, y) module gcd : input a : UInt<16> input b : UInt<16> input e : UInt<1> + input clk : Clock + input reset : UInt<1> output z : UInt<16> output v : UInt<1> - reg x : UInt - reg y : UInt - on-reset x := UInt(0) - on-reset y := UInt(42) + reg x : UInt,clk,reset + reg y : UInt,clk,reset + onreset x := UInt(0) + onreset y := UInt(42) when gt(x, y) : inst s of subtracter s.x := x @@ -35,10 +37,14 @@ circuit top : module top : input a : UInt<16> input b : UInt<16> + input clk : Clock + input reset : UInt<1> output z : UInt inst i of gcd i.a := a i.b := b + i.clk := clk + i.reset := reset i.e := UInt(1) z := i.z diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir index 6a50ae77..1b588c0e 100644 --- a/test/passes/infer-widths/simple.fir +++ b/test/passes/infer-widths/simple.fir @@ -3,9 +3,11 @@ ;CHECK: Infer Widths circuit top : module top : + input clk : Clock + input reset : UInt<1> wire e : UInt<30> e := UInt(1) - reg y : UInt + reg y : UInt,clk,reset y := e wire a : UInt<20> diff --git a/test/passes/inline/gcd.fir b/test/passes/inline/gcd.fir index 2c76bc82..6227520d 100644 --- a/test/passes/inline/gcd.fir +++ b/test/passes/inline/gcd.fir @@ -6,17 +6,19 @@ circuit top : input x : UInt input y : UInt output q : UInt - q := sub-wrap(x, y) + q := subw(x, y) module gcd : input a : UInt<16> input b : UInt<16> input e : UInt<1> + input clk : Clock + input reset : UInt<1> output z : UInt<16> output v : UInt<1> - reg x : UInt - reg y : UInt - on-reset x := UInt(0) - on-reset y := UInt(42) + reg x : UInt,clk,reset + reg y : UInt,clk,reset + onreset x := UInt(0) + onreset y := UInt(42) when gt(x, y) : inst s of subtracter s.x := x @@ -35,10 +37,14 @@ circuit top : module top : input a : UInt<16> input b : UInt<16> + input clk : Clock + input reset : UInt<1> output z : UInt inst i of gcd i.a := a i.b := b + i.clk := clk + i.reset := reset i.e := UInt(1) z := i.z diff --git a/test/passes/jacktest/ALUTop.fir b/test/passes/jacktest/ALUTop.fir index 562787a4..bc803e97 100644 --- a/test/passes/jacktest/ALUTop.fir +++ b/test/passes/jacktest/ALUTop.fir @@ -9,23 +9,23 @@ circuit ALUTop : input alu_op : UInt<4> node shamt = bits(B, 4, 0) - node T_157 = add-wrap(A, B) - node T_158 = sub-wrap(A, B) - node T_159 = convert(A) + node T_157 = addw(A, B) + node T_158 = subw(A, B) + node T_159 = cvt(A) node T_160 = dshr(T_159, shamt) - node T_161 = as-UInt(T_160) + node T_161 = asUInt(T_160) node T_162 = dshr(A, shamt) node T_163 = dshl(A, shamt) node T_164 = bits(T_163, 31, 0) - node T_165 = convert(A) - node T_166 = convert(B) + node T_165 = cvt(A) + node T_166 = cvt(B) node T_167 = lt(T_165, T_166) - node T_168 = as-UInt(T_167) + node T_168 = asUInt(T_167) node T_169 = lt(A, B) - node T_170 = as-UInt(T_169) - node T_171 = bit-and(A, B) - node T_172 = bit-or(A, B) - node T_173 = bit-xor(A, B) + node T_170 = asUInt(T_169) + node T_171 = and(A, B) + node T_172 = or(A, B) + node T_173 = xor(A, B) node T_174 = eq(UInt<4>(10), alu_op) node T_175 = mux(T_174, A, B) node T_176 = eq(UInt<4>(4), alu_op) @@ -51,9 +51,9 @@ circuit ALUTop : node T_195 = bits(oot, 31, 0) out := T_195 node T_196 = bit(alu_op, 0) - node T_197 = sub-wrap(UInt<1>(0), B) + node T_197 = subw(UInt<1>(0), B) node T_198 = mux(T_196, T_197, B) - node T_199 = add-wrap(A, T_198) + node T_199 = addw(A, T_198) sum := T_199 module ALUdec : input opcode : UInt<7> diff --git a/test/passes/jacktest/Counter.fir b/test/passes/jacktest/Counter.fir index 48af58b8..65efb47f 100644 --- a/test/passes/jacktest/Counter.fir +++ b/test/passes/jacktest/Counter.fir @@ -3,13 +3,15 @@ circuit Counter : module Counter : input inc : UInt<1> + input clk : Clock + input reset : UInt<1> output tot : UInt<8> input amt : UInt<4> - reg T_13 : UInt<8> - on-reset T_13 := UInt<8>(0) + reg T_13 : UInt<8>,clk,reset + onreset T_13 := UInt<8>(0) when inc : - node T_14 = add-wrap(T_13, amt) + node T_14 = addw(T_13, amt) node T_15 = gt(T_14, UInt<8>(255)) node T_16 = mux(T_15, UInt<1>(0), T_14) T_13 := T_16 diff --git a/test/passes/jacktest/EnableShiftRegister.fir b/test/passes/jacktest/EnableShiftRegister.fir index b9da2273..4e0387d0 100644 --- a/test/passes/jacktest/EnableShiftRegister.fir +++ b/test/passes/jacktest/EnableShiftRegister.fir @@ -3,17 +3,19 @@ circuit EnableShiftRegister : module EnableShiftRegister : input in : UInt<4> + input clk : Clock + input reset : UInt<1> output out : UInt<4> input shift : UInt<1> - reg r0 : UInt<4> - on-reset r0 := UInt<4>(0) - reg r1 : UInt<4> - on-reset r1 := UInt<4>(0) - reg r2 : UInt<4> - on-reset r2 := UInt<4>(0) - reg r3 : UInt<4> - on-reset r3 := UInt<4>(0) + reg r0 : UInt<4>,clk,reset + onreset r0 := UInt<4>(0) + reg r1 : UInt<4>,clk,reset + onreset r1 := UInt<4>(0) + reg r2 : UInt<4>,clk,reset + onreset r2 := UInt<4>(0) + reg r3 : UInt<4>,clk,reset + onreset r3 := UInt<4>(0) when shift : r0 := in r1 := r0 diff --git a/test/passes/jacktest/LFSR16.fir b/test/passes/jacktest/LFSR16.fir index f45002f5..9baa05a6 100644 --- a/test/passes/jacktest/LFSR16.fir +++ b/test/passes/jacktest/LFSR16.fir @@ -4,17 +4,19 @@ circuit LFSR16 : module LFSR16 : output out : UInt<16> input inc : UInt<1> + input clk : Clock + input reset : UInt<1> - reg res : UInt<16> - on-reset res := UInt<16>(1) + reg res : UInt<16>,clk,reset + onreset res := UInt<16>(1) when inc : node T_16 = bit(res, 0) node T_17 = bit(res, 2) - node T_18 = bit-xor(T_16, T_17) + node T_18 = xor(T_16, T_17) node T_19 = bit(res, 3) - node T_20 = bit-xor(T_18, T_19) + node T_20 = xor(T_18, T_19) node T_21 = bit(res, 5) - node T_22 = bit-xor(T_20, T_21) + node T_22 = xor(T_20, T_21) node T_23 = bits(res, 15, 1) node T_24 = cat(T_22, T_23) res := T_24 diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir index 59352162..ca530ea2 100644 --- a/test/passes/jacktest/MemorySearch.fir +++ b/test/passes/jacktest/MemorySearch.fir @@ -5,10 +5,12 @@ circuit MemorySearch : input target : UInt<4> output address : UInt<3> input en : UInt<1> + input clk : Clock + input reset : UInt<1> output done : UInt<1> - reg index : UInt<3> - on-reset index := UInt<3>(0) + reg index : UInt<3>,clk,reset + onreset index := UInt<3>(0) wire elts : UInt<4>[7] elts[0] := UInt<4>(0) elts[1] := UInt<4>(4) @@ -18,16 +20,16 @@ circuit MemorySearch : elts[5] := UInt<4>(5) elts[6] := UInt<4>(13) infer accessor elt = elts[index] - node T_35 = bit-not(en) + node T_35 = not(en) node T_36 = eq(elt, target) node T_37 = eq(index, UInt<3>(7)) - node T_38 = bit-or(T_36, T_37) - node end = bit-and(T_35, T_38) + node T_38 = or(T_36, T_37) + node end = and(T_35, T_38) when en : index := UInt<1>(0) else : - node T_39 = bit-not(end) + node T_39 = not(end) when T_39 : - node T_40 = add-wrap(index, UInt<1>(1)) + node T_40 = addw(index, UInt<1>(1)) index := T_40 done := end address := index diff --git a/test/passes/jacktest/ModuleVec.fir b/test/passes/jacktest/ModuleVec.fir index 04c119a1..2fde69f3 100644 --- a/test/passes/jacktest/ModuleVec.fir +++ b/test/passes/jacktest/ModuleVec.fir @@ -5,13 +5,13 @@ circuit ModuleVec : input in : UInt<32> output out : UInt<32> - node T_33 = add-wrap(in, UInt<1>(1)) + node T_33 = addw(in, UInt<1>(1)) out := T_33 module PlusOne_25 : input in : UInt<32> output out : UInt<32> - node T_34 = add-wrap(in, UInt<1>(1)) + node T_34 = addw(in, UInt<1>(1)) out := T_34 module ModuleVec : input ins : UInt<32>[2] diff --git a/test/passes/jacktest/Mul.fir b/test/passes/jacktest/Mul.fir index 14db8769..1552e959 100644 --- a/test/passes/jacktest/Mul.fir +++ b/test/passes/jacktest/Mul.fir @@ -24,6 +24,6 @@ circuit Mul : tbl[14] := UInt<4>(6) tbl[15] := UInt<4>(9) node T_42 = shl(x, 2) - node T_43 = bit-or(T_42, y) + node T_43 = or(T_42, y) infer accessor T_44 = tbl[T_43] z := T_44 diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir index d24bc383..cca645d1 100644 --- a/test/passes/jacktest/RegisterVecShift.fir +++ b/test/passes/jacktest/RegisterVecShift.fir @@ -3,11 +3,13 @@ circuit RegisterVecShift : module RegisterVecShift : input load : UInt<1> + input clk : Clock + input reset : UInt<1> output out : UInt<4> input shift : UInt<1> input ins : UInt<4>[4] - reg delays : UInt<4>[4] + reg delays : UInt<4>[4],clk,reset when reset : wire T_33 : UInt<4>[4] T_33[0] := UInt<4>(0) diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir index 4bce2bd4..5bbec6d2 100644 --- a/test/passes/jacktest/Stack.fir +++ b/test/passes/jacktest/Stack.fir @@ -5,31 +5,33 @@ circuit Stack : input push : UInt<1> input pop : UInt<1> input en : UInt<1> + input clk : Clock + input reset : UInt<1> output dataOut : UInt<32> input dataIn : UInt<32> - cmem stack_mem : UInt<32>[16] - reg sp : UInt<5> - on-reset sp := UInt<5>(0) - reg out : UInt<32> - on-reset out := UInt<32>(0) + cmem stack_mem : UInt<32>[16],clk + reg sp : UInt<5>,clk,reset + onreset sp := UInt<5>(0) + reg out : UInt<32>,clk,reset + onreset out := UInt<32>(0) when en : node T_30 = lt(sp, UInt<5>(16)) - node T_31 = bit-and(push, T_30) + node T_31 = and(push, T_30) when T_31 : infer accessor T_32 = stack_mem[sp] T_32 := dataIn - node T_33 = add-wrap(sp, UInt<1>(1)) + node T_33 = addw(sp, UInt<1>(1)) sp := T_33 else : node T_34 = gt(sp, UInt<1>(0)) - node T_35 = bit-and(pop, T_34) + node T_35 = and(pop, T_34) when T_35 : - node T_36 = sub-wrap(sp, UInt<1>(1)) + node T_36 = subw(sp, UInt<1>(1)) sp := T_36 node T_37 = gt(sp, UInt<1>(0)) when T_37 : - node T_38 = sub-wrap(sp, UInt<1>(1)) + node T_38 = subw(sp, UInt<1>(1)) infer accessor T_39 = stack_mem[T_38] out := T_39 dataOut := out diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir index f315aaa9..b916e0f0 100644 --- a/test/passes/jacktest/Tbl.fir +++ b/test/passes/jacktest/Tbl.fir @@ -4,10 +4,11 @@ circuit Tbl : module Tbl : input i : UInt<16> input d : UInt<16> + input clk : Clock output o : UInt<16> input we : UInt<1> - cmem m : UInt<10>[256] + cmem m : UInt<10>[256],clk o := UInt<1>(0) when we : infer accessor T_13 = m[i] diff --git a/test/passes/jacktest/VendingMachine.fir b/test/passes/jacktest/VendingMachine.fir index 10784964..0f4bf941 100644 --- a/test/passes/jacktest/VendingMachine.fir +++ b/test/passes/jacktest/VendingMachine.fir @@ -5,9 +5,11 @@ circuit VendingMachine : output valid : UInt<1> input nickel : UInt<1> input dime : UInt<1> + input clk : Clock + input reset : UInt<1> - reg state : UInt<3> - on-reset state := UInt<3>(0) + reg state : UInt<3>,clk,reset + onreset state := UInt<3>(0) node T_22 = eq(state, UInt<3>(0)) when T_22 : when nickel : state := UInt<3>(1) diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir index a0c1e10a..f3f12017 100644 --- a/test/passes/jacktest/gcd.fir +++ b/test/passes/jacktest/gcd.fir @@ -3,19 +3,21 @@ circuit GCD : module GCD : input e : UInt<1> + input clk : Clock + input reset : UInt<1> output z : UInt<16> output v : UInt<1> input a : UInt<16> input b : UInt<16> - reg x : UInt<16> - reg y : UInt<16> + reg x : UInt<16>,clk,reset + reg y : UInt<16>,clk,reset node T_17 = gt(x, y) when T_17 : - node T_18 = sub-wrap(x, y) + node T_18 = subw(x, y) x := T_18 else : - node T_19 = sub-wrap(y, x) + node T_19 = subw(y, x) y := T_19 when e : x := a diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir index 21030448..fda21820 100644 --- a/test/passes/jacktest/risc.fir +++ b/test/passes/jacktest/risc.fir @@ -1,5 +1,5 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s -;CHECK: Done! +; CHECK: Done! circuit Risc : module Risc : output out : UInt<32> @@ -8,11 +8,13 @@ circuit Risc : input isWr : UInt<1> input wrAddr : UInt<8> input wrData : UInt<32> + input clk : Clock + input reset : UInt<1> - cmem file : UInt<32>[256] - cmem code : UInt<32>[256] - reg pc : UInt<8> - on-reset pc := UInt<8>(0) + cmem file : UInt<32>[256],clk + cmem code : UInt<32>[256],clk + reg pc : UInt<8>,clk,reset + onreset pc := UInt<8>(0) infer accessor inst = code[pc] node op = bits(inst, 31, 24) node rci = bits(inst, 23, 16) @@ -35,12 +37,12 @@ circuit Risc : else : node T_56 = eq(UInt<1>(0), op) when T_56 : - node T_57 = add-wrap(ra, rb) + node T_57 = addw(ra, rb) rc := T_57 node T_58 = eq(UInt<1>(1), op) when T_58 : node T_59 = shl(rai, 8) - node T_60 = bit-or(T_59, rbi) + node T_60 = or(T_59, rbi) rc := T_60 out := rc node T_61 = eq(rci, UInt<8>(255)) @@ -48,5 +50,5 @@ circuit Risc : else : infer accessor T_62 = file[rci] T_62 := rc - node T_63 = add-wrap(pc, UInt<1>(1)) + node T_63 = addw(pc, UInt<1>(1)) pc := T_63 diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir index cede6f43..4858fafb 100644 --- a/test/passes/lower-to-ground/accessor.fir +++ b/test/passes/lower-to-ground/accessor.fir @@ -3,26 +3,27 @@ ; CHECK: Lower To Ground circuit top : module top : + input clk : Clock wire i : UInt<2> wire j : UInt<32> wire a : UInt<32>[4] - ; CHECK: wire a$0 : UInt<32> - ; CHECK: wire a$1 : UInt<32> - ; CHECK: wire a$2 : UInt<32> - ; CHECK: wire a$3 : UInt<32> + ; CHECK: wire a_0 : UInt<32> + ; CHECK: wire a_1 : UInt<32> + ; CHECK: wire a_2 : UInt<32> + ; CHECK: wire a_3 : UInt<32> infer accessor b = a[i] ; CHECK: wire b : UInt<32> - ; CHECK: b := (a$0 a$1 a$2 a$3)[i] + ; CHECK: b := (a_0 a_1 a_2 a_3)[i] j := b infer accessor c = a[i] ; CHECK: wire c : UInt<32> - ; CHECK: (a$0 a$1 a$2 a$3)[i] := c + ; CHECK: (a_0 a_1 a_2 a_3)[i] := c c := j - cmem p : UInt<32>[4] + cmem p : UInt<32>[4],clk infer accessor t = p[i] ; CHECK: accessor t = p[i] j := t diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir index e71e9104..ebf81093 100644 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ b/test/passes/lower-to-ground/bundle-vecs.fir @@ -7,23 +7,23 @@ circuit top : wire j : { x : UInt<32>, flip y : UInt<32> } wire a : { x : UInt<32>, flip y : UInt<32> }[2] - ; CHECK: wire a$0$x : UInt<32> - ; CHECK: wire a$0$y : UInt<32> - ; CHECK: wire a$1$x : UInt<32> - ; CHECK: wire a$1$y : UInt<32> + ; CHECK: wire a_0_x : UInt<32> + ; CHECK: wire a_0_y : UInt<32> + ; CHECK: wire a_1_x : UInt<32> + ; CHECK: wire a_1_y : UInt<32> infer accessor b = a[i] - ; CHECK: wire b$x : UInt<32> - ; CHECK: wire b$y : UInt<32> - ; CHECK: b$x := (a$0$x a$1$x)[i] - ; CHECK: (a$0$y a$1$y)[i] := b$y + ; CHECK: wire b_x : UInt<32> + ; CHECK: wire b_y : UInt<32> + ; CHECK: b_x := (a_0_x a_1_x)[i] + ; CHECK: (a_0_y a_1_y)[i] := b_y j := b infer accessor c = a[i] - ; CHECK: wire c$x : UInt<32> - ; CHECK: wire c$y : UInt<32> - ; CHECK: (a$0$x a$1$x)[i] := c$x - ; CHECK: c$y := (a$0$y a$1$y)[i] + ; CHECK: wire c_x : UInt<32> + ; CHECK: wire c_y : UInt<32> + ; CHECK: (a_0_x a_1_x)[i] := c_x + ; CHECK: c_y := (a_0_y a_1_y)[i] c := j diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir index c0acfecd..7c11cbc5 100644 --- a/test/passes/lower-to-ground/bundle.fir +++ b/test/passes/lower-to-ground/bundle.fir @@ -17,37 +17,34 @@ circuit top : ;CHECK: Lower To Ground ;CHECK: circuit top : ;CHECK: module m : -;CHECK: input a$x : UInt<5> -;CHECK: output a$y : SInt<5> -;CHECK: output b$x : UInt<5> -;CHECK: input b$y : SInt<5> -;CHECK: input reset : UInt<1> +;CHECK: input a_x : UInt<5> +;CHECK: output a_y : SInt<5> +;CHECK: output b_x : UInt<5> +;CHECK: input b_y : SInt<5> ;CHECK: module top : -;CHECK: input c$x$0 : UInt<5> -;CHECK: input c$x$1 : UInt<5> -;CHECK: input c$x$2 : UInt<5> -;CHECK: input c$x$3 : UInt<5> -;CHECK: input c$x$4 : UInt<5> -;CHECK: output c$y$x$0 : UInt<5> -;CHECK: output c$y$x$1 : UInt<5> -;CHECK: output c$y$x$2 : UInt<5> -;CHECK: input c$y$y : SInt<5> -;CHECK: input reset : UInt<1> -;CHECK: wire a$x : UInt<5> -;CHECK: wire a$y : SInt<5> -;CHECK: wire b$x : UInt<5> -;CHECK: wire b$y : SInt<5> -;CHECK: a$x := b$x -;CHECK: b$y := a$y +;CHECK: input c_x_0 : UInt<5> +;CHECK: input c_x_1 : UInt<5> +;CHECK: input c_x_2 : UInt<5> +;CHECK: input c_x_3 : UInt<5> +;CHECK: input c_x_4 : UInt<5> +;CHECK: output c_y_x_0 : UInt<5> +;CHECK: output c_y_x_1 : UInt<5> +;CHECK: output c_y_x_2 : UInt<5> +;CHECK: input c_y_y : SInt<5> +;CHECK: wire a_x : UInt<5> +;CHECK: wire a_y : SInt<5> +;CHECK: wire b_x : UInt<5> +;CHECK: wire b_y : SInt<5> +;CHECK: a_x := b_x +;CHECK: b_y := a_y ;CHECK: inst i of m -;CHECK: i.reset := reset -;CHECK: i.a$x := a$x -;CHECK: a$y := i.a$y -;CHECK: b$x := i.b$x -;CHECK: i.b$y := b$y -;CHECK: wire d$0 : UInt<5> -;CHECK: wire d$1 : UInt<5> -;CHECK: wire d$2 : UInt<5> -;CHECK: wire d$3 : UInt<5> -;CHECK: wire d$4 : UInt<5> +;CHECK: i.a_x := a_x +;CHECK: a_y := i.a_y +;CHECK: b_x := i.b_x +;CHECK: i.b_y := b_y +;CHECK: wire d_0 : UInt<5> +;CHECK: wire d_1 : UInt<5> +;CHECK: wire d_2 : UInt<5> +;CHECK: wire d_3 : UInt<5> +;CHECK: wire d_4 : UInt<5> ;CHECK: Finished Lower To Ground diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir index 420c3c7c..57c68398 100644 --- a/test/passes/lower-to-ground/instance.fir +++ b/test/passes/lower-to-ground/instance.fir @@ -27,9 +27,9 @@ circuit top : ; CHECK: Lower To Ground -; CHECK: connect$data@ := src@.data@ -; CHECK: src@.ready@ := connect$ready@ -; CHECK: snk@.data@ := connect2$data@ -; CHECK: connect2$ready@ := snk@.ready@ +; CHECK: connect_data@ := src@.data@ +; CHECK: src@.ready@ := connect_ready@ +; CHECK: snk@.data@ := connect2_data@ +; CHECK: connect2_ready@ := snk@.ready@ ; CHECK: Finished Lower To Ground diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir index a2eb1215..1f38d10e 100644 --- a/test/passes/lower-to-ground/nested-vec.fir +++ b/test/passes/lower-to-ground/nested-vec.fir @@ -3,34 +3,35 @@ ; CHECK: Lower To Ground circuit top : module top : + input clk : Clock wire i : UInt wire j : { x : UInt<32>, flip y : UInt<32> } wire k : { x : UInt<32>, y : UInt<32> } wire a : { x : UInt<32>, flip y : UInt<32> }[2] - ; CHECK: wire a$0$x : UInt<32> - ; CHECK: wire a$0$y : UInt<32> - ; CHECK: wire a$1$x : UInt<32> - ; CHECK: wire a$1$y : UInt<32> + ; CHECK: wire a_0_x : UInt<32> + ; CHECK: wire a_0_y : UInt<32> + ; CHECK: wire a_1_x : UInt<32> + ; CHECK: wire a_1_y : UInt<32> infer accessor b = a[i] - ; CHECK: wire b$x : UInt<32> - ; CHECK: wire b$y : UInt<32> - ; CHECK: b$x := (a$0$x a$1$x)[i] - ; CHECK: (a$0$y a$1$y)[i] := b$y + ; CHECK: wire b_x : UInt<32> + ; CHECK: wire b_y : UInt<32> + ; CHECK: b_x := (a_0_x a_1_x)[i] + ; CHECK: (a_0_y a_1_y)[i] := b_y j := b - cmem m : { x : UInt<32>, y : UInt<32> }[2] - ; CHECK: cmem m$x : UInt<32>[2] - ; CHECK: cmem m$y : UInt<32>[2] + cmem m : { x : UInt<32>, y : UInt<32> }[2],clk + ; CHECK: cmem m_x : UInt<32>[2] + ; CHECK: cmem m_y : UInt<32>[2] infer accessor c = m[i] ; MALE - ; CHECK: accessor c$x = m$x[i] - ; CHECK: accessor c$y = m$y[i] + ; CHECK: accessor c_x = m_x[i] + ; CHECK: accessor c_y = m_y[i] c := k - ; CHECK: c$x := k$x - ; CHECK: c$y := k$y + ; CHECK: c_x := k_x + ; CHECK: c_y := k_y ; CHECK: Finished Lower To Ground diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir index a3c4f0ae..b045aadc 100644 --- a/test/passes/lower-to-ground/register.fir +++ b/test/passes/lower-to-ground/register.fir @@ -5,17 +5,19 @@ module top : input a : UInt<16> input b : UInt<16> + input clk : Clock + input reset : UInt<1> output z : UInt - reg r1 : { x : UInt, flip y : SInt } + reg r1 : { x : UInt, flip y : SInt },clk,reset wire q : { x : UInt, flip y : SInt } - on-reset r1 := q + onreset r1 := q - ; CHECK: reg r1$x : UInt - ; CHECK: reg r1$y : SInt - ; CHECK: wire q$x : UInt - ; CHECK: wire q$y : SInt - ; CHECK: on-reset r1$x := q$x - ; CHECK: on-reset q$y := r1$y + ; CHECK: reg r1_x : UInt + ; CHECK: reg r1_y : SInt + ; CHECK: wire q_x : UInt + ; CHECK: wire q_y : SInt + ; CHECK: onreset r1_x := q_x + ; CHECK: onreset q_y := r1_y ; CHECK: Finished Lower To Ground diff --git a/test/passes/make-explicit-reset/mix-reset.fir b/test/passes/make-explicit-reset/mix-reset.fir deleted file mode 100644 index 97d32397..00000000 --- a/test/passes/make-explicit-reset/mix-reset.fir +++ /dev/null @@ -1,29 +0,0 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p cd | tee %s.out | FileCheck %s - -; CHECK: Make Explicit Reset -circuit top : - module A : - ;CHECK: input reset : UInt<1> - input x : UInt<16> - output y : UInt<16> - inst b of B - ;CHECK: b.reset := reset - module B : - input reset : UInt<1> - ;CHECK: input reset : UInt<1> - input x : UInt<16> - output y : UInt<16> - inst c of C - ;CHECK: c.reset := reset - module C : - ;CHECK: input reset : UInt<1> - input a : UInt<16> - input b : UInt<16> - module top : - ;CHECK: input reset : UInt<1> - input a : UInt<16> - input b : UInt<16> - output z : UInt<1> - inst x of A - ;CHECK: x.reset := reset -;CHECK: Finished Make Explicit Reset diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir index 6fbaad85..da15cb78 100644 --- a/test/passes/resolve-genders/gcd.fir +++ b/test/passes/resolve-genders/gcd.fir @@ -6,19 +6,21 @@ circuit top : input x : UInt input y : UInt output z : UInt - z := sub-wrap(x, y) - ;CHECK: z@ := sub-wrap(x@, y@) + z := subw(x, y) + ;CHECK: z@ := subw(x@, y@) module gcd : input a : UInt<16> input b : UInt<16> input e : UInt<1> + input clk : Clock + input reset : UInt<1> output z : UInt<16> output v : UInt<1> - reg x : UInt - reg y : UInt + reg x : UInt,clk,reset + reg y : UInt,clk,reset ; CHECK: reg x : UInt - on-reset x := UInt(0) - on-reset y := UInt(42) + onreset x := UInt(0) + onreset y := UInt(42) when gt(x, y) : ;CHECK: when gt(x@, y@) : inst s of subtracter @@ -40,12 +42,16 @@ circuit top : v := eq(v, UInt(0)) z := x module top : + input clk : Clock + input reset : UInt<1> input a : UInt<16> input b : UInt<16> output z : UInt inst i of gcd i.a := a i.b := b + i.clk := clk + i.reset := reset i.e := UInt(1) z := i.z diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir index 383c2a31..354545fb 100644 --- a/test/passes/resolve-genders/subbundle.fir +++ b/test/passes/resolve-genders/subbundle.fir @@ -3,8 +3,10 @@ ;CHECK: Lower To Ground circuit top : module top : + input clk : Clock + input reset : UInt<1> wire w : { flip x : UInt<10>} - reg r : { flip x : UInt<10>} + reg r : { flip x : UInt<10>},clk,reset w := r ; CHECK r$x := w$x w.x := r.x ; CHECK w$x := r$x ; CHECK: Finished Lower To Ground diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir index 341910d4..cd02a463 100644 --- a/test/passes/resolve-kinds/gcd.fir +++ b/test/passes/resolve-kinds/gcd.fir @@ -6,18 +6,20 @@ circuit top : input x : UInt input y : UInt output z : UInt - z := sub-wrap(x, y) - ;CHECK: z@ := sub-wrap(x@, y@) + z := subw(x, y) + ;CHECK: z@ := subw(x@, y@) module gcd : + input clk : Clock + input reset : UInt<1> input a : UInt<16> input b : UInt<16> input e : UInt<1> output z : UInt<16> output v : UInt<1> - reg x : UInt - reg y : UInt - on-reset x := UInt(0) - on-reset y := UInt(42) + reg x : UInt,clk,reset + reg y : UInt,clk,reset + onreset x := UInt(0) + onreset y := UInt(42) when gt(x, y) : inst s of subtracter s.x := x @@ -37,11 +39,15 @@ circuit top : module top : input a : UInt<16> input b : UInt<16> + input clk : Clock + input reset : UInt<1> output z : UInt inst i of gcd ;CHECK: inst i of gcd@ i.a := a i.b := b + i.clk := clk + i.reset := reset i.e := UInt(1) z := i.z ;CHECK: z@ := i@.z diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir index 5af83202..fc49335c 100644 --- a/test/passes/split-exp/gcd.fir +++ b/test/passes/split-exp/gcd.fir @@ -6,17 +6,19 @@ circuit top : input x : UInt input y : UInt output q : UInt - q := sub-wrap(x, y) + q := subw(x, y) module gcd : + input clk : Clock + input reset : UInt<1> input a : UInt<16> input b : UInt<16> input e : UInt<1> output z : UInt<16> output v : UInt<1> - reg x : UInt - reg y : UInt - on-reset x := UInt(0) - on-reset y := UInt(42) + reg x : UInt,clk,reset + reg y : UInt,clk,reset + onreset x := UInt(0) + onreset y := UInt(42) when gt(x, y) : inst s of subtracter s.x := x @@ -33,10 +35,14 @@ circuit top : v := eq(v, UInt(0)) z := x module top : + input clk : Clock + input reset : UInt<1> input a : UInt<16> input b : UInt<16> output z : UInt inst i of gcd + i.clk := clk + i.reset := reset i.a := a i.b := b i.e := UInt(1) diff --git a/test/passes/to-flo/gcd.fir b/test/passes/to-flo/gcd.fir index 3d5ea30f..84998989 100644 --- a/test/passes/to-flo/gcd.fir +++ b/test/passes/to-flo/gcd.fir @@ -6,17 +6,19 @@ circuit top : input x : UInt input y : UInt output q : UInt - q := sub-wrap(x, y) + q := subw(x, y) module gcd : + input clk : Clock + input reset : UInt<1> input a : UInt<16> input b : UInt<16> input e : UInt<1> output z : UInt<16> output v : UInt<1> - reg x : UInt - reg y : UInt - on-reset x := UInt(0) - on-reset y := UInt(42) + reg x : UInt,clk,reset + reg y : UInt,clk,reset + onreset x := UInt(0) + onreset y := UInt(42) when gt(x, y) : inst s of subtracter s.x := x @@ -35,8 +37,12 @@ circuit top : module top : input a : UInt<16> input b : UInt<16> + input clk : Clock + input reset : UInt<1> output z : UInt inst i of gcd + i.clk := clk + i.reset := reset i.a := a i.b := b i.e := UInt(1) diff --git a/test/passes/to-verilog/gcd.fir b/test/passes/to-verilog/gcd.fir index 23a2d4f5..9b8732a6 100644 --- a/test/passes/to-verilog/gcd.fir +++ b/test/passes/to-verilog/gcd.fir @@ -6,17 +6,19 @@ circuit top : input x : UInt input y : UInt output q : UInt - q := sub-wrap(x, y) + q := subw(x, y) module gcd : + input clk : Clock + input reset : UInt<1> input a : UInt<16> input b : UInt<16> input e : UInt<1> output z : UInt<16> output v : UInt<1> - reg x : UInt - reg y : UInt - on-reset x := UInt(0) - on-reset y := UInt(42) + reg x : UInt,clk,reset + reg y : UInt,clk,reset + onreset x := UInt(0) + onreset y := UInt(42) when gt(x, y) : inst s of subtracter s.x := x @@ -35,11 +37,14 @@ circuit top : module top : input a : UInt<16> input b : UInt<16> + input clk : Clock + input reset : UInt<1> output z : UInt inst i of gcd + i.clk := clk + i.reset := reset i.a := a i.b := b i.e := UInt(1) z := i.z ;CHECK: Done! - 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