From 8cb5aa96983210942336beb05a17ae1cade8b11a Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Fri, 10 Apr 2020 12:59:17 -0700
Subject: Split Resolves into separate files

* Remove unused imports
---
 src/main/scala/firrtl/passes/CInferMDir.scala   |  75 ++++++++++++
 src/main/scala/firrtl/passes/ResolveFlows.scala |  46 +++++++
 src/main/scala/firrtl/passes/ResolveKinds.scala |  49 ++++++++
 src/main/scala/firrtl/passes/Resolves.scala     | 155 ------------------------
 4 files changed, 170 insertions(+), 155 deletions(-)
 create mode 100644 src/main/scala/firrtl/passes/CInferMDir.scala
 create mode 100644 src/main/scala/firrtl/passes/ResolveFlows.scala
 create mode 100644 src/main/scala/firrtl/passes/ResolveKinds.scala
 delete mode 100644 src/main/scala/firrtl/passes/Resolves.scala

diff --git a/src/main/scala/firrtl/passes/CInferMDir.scala b/src/main/scala/firrtl/passes/CInferMDir.scala
new file mode 100644
index 00000000..33587741
--- /dev/null
+++ b/src/main/scala/firrtl/passes/CInferMDir.scala
@@ -0,0 +1,75 @@
+// See LICENSE for license details.
+
+package firrtl.passes
+
+import firrtl._
+import firrtl.ir._
+import firrtl.Mappers._
+import firrtl.options.{Dependency, PreservesAll}
+import Utils.throwInternalError
+
+object CInferMDir extends Pass with PreservesAll[Transform] {
+
+  override val prerequisites = firrtl.stage.Forms.ChirrtlForm :+ Dependency(CInferTypes)
+
+  type MPortDirMap = collection.mutable.LinkedHashMap[String, MPortDir]
+
+  def infer_mdir_e(mports: MPortDirMap, dir: MPortDir)(e: Expression): Expression = e match {
+    case e: Reference =>
+      mports get e.name match {
+        case None =>
+        case Some(p) => mports(e.name) = (p, dir) match {
+          case (MInfer, MInfer) => throwInternalError(s"infer_mdir_e: shouldn't be here - $p, $dir")
+          case (MInfer, MWrite) => MWrite
+          case (MInfer, MRead) => MRead
+          case (MInfer, MReadWrite) => MReadWrite
+          case (MWrite, MInfer) => throwInternalError(s"infer_mdir_e: shouldn't be here - $p, $dir")
+          case (MWrite, MWrite) => MWrite
+          case (MWrite, MRead) => MReadWrite
+          case (MWrite, MReadWrite) => MReadWrite
+          case (MRead, MInfer) => throwInternalError(s"infer_mdir_e: shouldn't be here - $p, $dir")
+          case (MRead, MWrite) => MReadWrite
+          case (MRead, MRead) => MRead
+          case (MRead, MReadWrite) => MReadWrite
+          case (MReadWrite, MInfer) => throwInternalError(s"infer_mdir_e: shouldn't be here - $p, $dir")
+          case (MReadWrite, MWrite) => MReadWrite
+          case (MReadWrite, MRead) => MReadWrite
+          case (MReadWrite, MReadWrite) => MReadWrite
+        }
+      }
+      e
+    case e: SubAccess =>
+      infer_mdir_e(mports, dir)(e.expr)
+      infer_mdir_e(mports, MRead)(e.index) // index can't be a write port
+      e
+    case e => e map infer_mdir_e(mports, dir)
+  }
+
+  def infer_mdir_s(mports: MPortDirMap)(s: Statement): Statement = s match {
+    case sx: CDefMPort =>
+       mports(sx.name) = sx.direction
+       sx map infer_mdir_e(mports, MRead)
+    case sx: Connect =>
+       infer_mdir_e(mports, MRead)(sx.expr)
+       infer_mdir_e(mports, MWrite)(sx.loc)
+       sx
+    case sx: PartialConnect =>
+       infer_mdir_e(mports, MRead)(sx.expr)
+       infer_mdir_e(mports, MWrite)(sx.loc)
+       sx
+    case sx => sx map infer_mdir_s(mports) map infer_mdir_e(mports, MRead)
+  }
+
+  def set_mdir_s(mports: MPortDirMap)(s: Statement): Statement = s match {
+    case sx: CDefMPort => sx copy (direction = mports(sx.name))
+    case sx => sx map set_mdir_s(mports)
+  }
+
+  def infer_mdir(m: DefModule): DefModule = {
+    val mports = new MPortDirMap
+    m map infer_mdir_s(mports) map set_mdir_s(mports)
+  }
+
+  def run(c: Circuit): Circuit =
+    c copy (modules = c.modules map infer_mdir)
+}
diff --git a/src/main/scala/firrtl/passes/ResolveFlows.scala b/src/main/scala/firrtl/passes/ResolveFlows.scala
new file mode 100644
index 00000000..8f413082
--- /dev/null
+++ b/src/main/scala/firrtl/passes/ResolveFlows.scala
@@ -0,0 +1,46 @@
+// See LICENSE for license details.
+
+package firrtl.passes
+
+import firrtl._
+import firrtl.ir._
+import firrtl.Mappers._
+import firrtl.options.{Dependency, PreservesAll}
+
+object ResolveFlows extends Pass with PreservesAll[Transform] {
+
+  override val prerequisites =
+    Seq( Dependency(passes.ResolveKinds),
+         Dependency(passes.InferTypes),
+         Dependency(passes.Uniquify) ) ++ firrtl.stage.Forms.WorkingIR
+
+  def resolve_e(g: Flow)(e: Expression): Expression = e match {
+    case ex: WRef => ex copy (flow = g)
+    case WSubField(exp, name, tpe, _) => WSubField(
+      Utils.field_flip(exp.tpe, name) match {
+        case Default => resolve_e(g)(exp)
+        case Flip => resolve_e(Utils.swap(g))(exp)
+      }, name, tpe, g)
+    case WSubIndex(exp, value, tpe, _) =>
+      WSubIndex(resolve_e(g)(exp), value, tpe, g)
+    case WSubAccess(exp, index, tpe, _) =>
+      WSubAccess(resolve_e(g)(exp), resolve_e(SourceFlow)(index), tpe, g)
+    case _ => e map resolve_e(g)
+  }
+
+  def resolve_s(s: Statement): Statement = s match {
+    //TODO(azidar): pretty sure don't need to do anything for Attach, but not positive...
+    case IsInvalid(info, expr) =>
+      IsInvalid(info, resolve_e(SinkFlow)(expr))
+    case Connect(info, loc, expr) =>
+      Connect(info, resolve_e(SinkFlow)(loc), resolve_e(SourceFlow)(expr))
+    case PartialConnect(info, loc, expr) =>
+      PartialConnect(info, resolve_e(SinkFlow)(loc), resolve_e(SourceFlow)(expr))
+    case sx => sx map resolve_e(SourceFlow) map resolve_s
+  }
+
+  def resolve_flow(m: DefModule): DefModule = m map resolve_s
+
+  def run(c: Circuit): Circuit =
+    c copy (modules = c.modules map resolve_flow)
+}
diff --git a/src/main/scala/firrtl/passes/ResolveKinds.scala b/src/main/scala/firrtl/passes/ResolveKinds.scala
new file mode 100644
index 00000000..fb36ccd5
--- /dev/null
+++ b/src/main/scala/firrtl/passes/ResolveKinds.scala
@@ -0,0 +1,49 @@
+// See LICENSE for license details.
+
+package firrtl.passes
+
+import firrtl._
+import firrtl.ir._
+import firrtl.Mappers._
+import firrtl.options.PreservesAll
+
+object ResolveKinds extends Pass with PreservesAll[Transform] {
+
+  override val prerequisites = firrtl.stage.Forms.WorkingIR
+
+  type KindMap = collection.mutable.LinkedHashMap[String, Kind]
+
+  def find_port(kinds: KindMap)(p: Port): Port = {
+    kinds(p.name) = PortKind ; p
+  }
+
+  def find_stmt(kinds: KindMap)(s: Statement):Statement = {
+    s match {
+      case sx: DefWire => kinds(sx.name) = WireKind
+      case sx: DefNode => kinds(sx.name) = NodeKind
+      case sx: DefRegister => kinds(sx.name) = RegKind
+      case sx: WDefInstance => kinds(sx.name) = InstanceKind
+      case sx: DefMemory => kinds(sx.name) = MemKind
+      case _ =>
+    }
+    s map find_stmt(kinds)
+  }
+
+  def resolve_expr(kinds: KindMap)(e: Expression): Expression = e match {
+    case ex: WRef => ex copy (kind = kinds(ex.name))
+    case _ => e map resolve_expr(kinds)
+  }
+
+  def resolve_stmt(kinds: KindMap)(s: Statement): Statement =
+    s map resolve_stmt(kinds) map resolve_expr(kinds)
+
+  def resolve_kinds(m: DefModule): DefModule = {
+    val kinds = new KindMap
+    (m map find_port(kinds)
+       map find_stmt(kinds)
+       map resolve_stmt(kinds))
+  }
+
+  def run(c: Circuit): Circuit =
+    c copy (modules = c.modules map resolve_kinds)
+}
diff --git a/src/main/scala/firrtl/passes/Resolves.scala b/src/main/scala/firrtl/passes/Resolves.scala
deleted file mode 100644
index de54a5c1..00000000
--- a/src/main/scala/firrtl/passes/Resolves.scala
+++ /dev/null
@@ -1,155 +0,0 @@
-// See LICENSE for license details.
-
-package firrtl.passes
-
-import firrtl._
-import firrtl.ir._
-import firrtl.Mappers._
-import firrtl.options.{Dependency, PreservesAll}
-import Utils.throwInternalError
-
-
-object ResolveKinds extends Pass with PreservesAll[Transform] {
-
-  override val prerequisites = firrtl.stage.Forms.WorkingIR
-
-  type KindMap = collection.mutable.LinkedHashMap[String, Kind]
-
-  def find_port(kinds: KindMap)(p: Port): Port = {
-    kinds(p.name) = PortKind ; p
-  }
-
-  def find_stmt(kinds: KindMap)(s: Statement):Statement = {
-    s match {
-      case sx: DefWire => kinds(sx.name) = WireKind
-      case sx: DefNode => kinds(sx.name) = NodeKind
-      case sx: DefRegister => kinds(sx.name) = RegKind
-      case sx: WDefInstance => kinds(sx.name) = InstanceKind
-      case sx: DefMemory => kinds(sx.name) = MemKind
-      case _ =>
-    }
-    s map find_stmt(kinds)
-  }
-
-  def resolve_expr(kinds: KindMap)(e: Expression): Expression = e match {
-    case ex: WRef => ex copy (kind = kinds(ex.name))
-    case _ => e map resolve_expr(kinds)
-  }
-
-  def resolve_stmt(kinds: KindMap)(s: Statement): Statement =
-    s map resolve_stmt(kinds) map resolve_expr(kinds)
-
-  def resolve_kinds(m: DefModule): DefModule = {
-    val kinds = new KindMap
-    (m map find_port(kinds)
-       map find_stmt(kinds)
-       map resolve_stmt(kinds))
-  }
-
-  def run(c: Circuit): Circuit =
-    c copy (modules = c.modules map resolve_kinds)
-}
-
-object ResolveFlows extends Pass with PreservesAll[Transform] {
-
-  override val prerequisites =
-    Seq( Dependency(passes.ResolveKinds),
-         Dependency(passes.InferTypes),
-         Dependency(passes.Uniquify) ) ++ firrtl.stage.Forms.WorkingIR
-
-  def resolve_e(g: Flow)(e: Expression): Expression = e match {
-    case ex: WRef => ex copy (flow = g)
-    case WSubField(exp, name, tpe, _) => WSubField(
-      Utils.field_flip(exp.tpe, name) match {
-        case Default => resolve_e(g)(exp)
-        case Flip => resolve_e(Utils.swap(g))(exp)
-      }, name, tpe, g)
-    case WSubIndex(exp, value, tpe, _) =>
-      WSubIndex(resolve_e(g)(exp), value, tpe, g)
-    case WSubAccess(exp, index, tpe, _) =>
-      WSubAccess(resolve_e(g)(exp), resolve_e(SourceFlow)(index), tpe, g)
-    case _ => e map resolve_e(g)
-  }
-
-  def resolve_s(s: Statement): Statement = s match {
-    //TODO(azidar): pretty sure don't need to do anything for Attach, but not positive...
-    case IsInvalid(info, expr) =>
-      IsInvalid(info, resolve_e(SinkFlow)(expr))
-    case Connect(info, loc, expr) =>
-      Connect(info, resolve_e(SinkFlow)(loc), resolve_e(SourceFlow)(expr))
-    case PartialConnect(info, loc, expr) =>
-      PartialConnect(info, resolve_e(SinkFlow)(loc), resolve_e(SourceFlow)(expr))
-    case sx => sx map resolve_e(SourceFlow) map resolve_s
-  }
-
-  def resolve_flow(m: DefModule): DefModule = m map resolve_s
-
-  def run(c: Circuit): Circuit =
-    c copy (modules = c.modules map resolve_flow)
-}
-
-object CInferMDir extends Pass with PreservesAll[Transform] {
-
-  override val prerequisites = firrtl.stage.Forms.ChirrtlForm :+ Dependency(CInferTypes)
-
-  type MPortDirMap = collection.mutable.LinkedHashMap[String, MPortDir]
-
-  def infer_mdir_e(mports: MPortDirMap, dir: MPortDir)(e: Expression): Expression = e match {
-    case e: Reference =>
-      mports get e.name match {
-        case None =>
-        case Some(p) => mports(e.name) = (p, dir) match {
-          case (MInfer, MInfer) => throwInternalError(s"infer_mdir_e: shouldn't be here - $p, $dir")
-          case (MInfer, MWrite) => MWrite
-          case (MInfer, MRead) => MRead
-          case (MInfer, MReadWrite) => MReadWrite
-          case (MWrite, MInfer) => throwInternalError(s"infer_mdir_e: shouldn't be here - $p, $dir")
-          case (MWrite, MWrite) => MWrite
-          case (MWrite, MRead) => MReadWrite
-          case (MWrite, MReadWrite) => MReadWrite
-          case (MRead, MInfer) => throwInternalError(s"infer_mdir_e: shouldn't be here - $p, $dir")
-          case (MRead, MWrite) => MReadWrite
-          case (MRead, MRead) => MRead
-          case (MRead, MReadWrite) => MReadWrite
-          case (MReadWrite, MInfer) => throwInternalError(s"infer_mdir_e: shouldn't be here - $p, $dir")
-          case (MReadWrite, MWrite) => MReadWrite
-          case (MReadWrite, MRead) => MReadWrite
-          case (MReadWrite, MReadWrite) => MReadWrite
-        }
-      }
-      e
-    case e: SubAccess =>
-      infer_mdir_e(mports, dir)(e.expr)
-      infer_mdir_e(mports, MRead)(e.index) // index can't be a write port
-      e
-    case e => e map infer_mdir_e(mports, dir)
-  }
-
-  def infer_mdir_s(mports: MPortDirMap)(s: Statement): Statement = s match {
-    case sx: CDefMPort =>
-       mports(sx.name) = sx.direction
-       sx map infer_mdir_e(mports, MRead)
-    case sx: Connect =>
-       infer_mdir_e(mports, MRead)(sx.expr)
-       infer_mdir_e(mports, MWrite)(sx.loc)
-       sx
-    case sx: PartialConnect =>
-       infer_mdir_e(mports, MRead)(sx.expr)
-       infer_mdir_e(mports, MWrite)(sx.loc)
-       sx
-    case sx => sx map infer_mdir_s(mports) map infer_mdir_e(mports, MRead)
-  }
-
-  def set_mdir_s(mports: MPortDirMap)(s: Statement): Statement = s match {
-    case sx: CDefMPort => sx copy (direction = mports(sx.name))
-    case sx => sx map set_mdir_s(mports)
-  }
-
-  def infer_mdir(m: DefModule): DefModule = {
-    val mports = new MPortDirMap
-    m map infer_mdir_s(mports) map set_mdir_s(mports)
-  }
-
-  def run(c: Circuit): Circuit =
-    c copy (modules = c.modules map infer_mdir)
-}
-- 
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