From 88a9b1721b799275238c7d601643cf030a73f99c Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 15 Apr 2015 19:38:25 -0700
Subject: Updated todo

---
 TODO                          | 18 ++++++++++++++++--
 src/main/stanza/passes.stanza |  4 ++--
 2 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/TODO b/TODO
index 28e40327..7c243b8a 100644
--- a/TODO
+++ b/TODO
@@ -12,6 +12,7 @@ on-reset
 Write lowering step for primops
 Add bit-reduce-and etc to primops (Jonathan)
 Add source locaters
+Add Unit Tests for each pass
 
 ======== Check Passes ==========
 Parser
@@ -30,7 +31,6 @@ Well-formed low firrtl
    All things only assigned to once
 
 ======== Other Passes ========
-Flo backend
 PrimOp lowering
 
 ======== Think About ========
@@ -46,7 +46,7 @@ Figure out how widths propogate for all updated primops (Adam)
 Add partial bulk connect (Scott, Stephen)
 Add FIFOs to the IR (Palmer)
 Think about supporting generic primops on bundles and vecs (Adam) (wait until front-end more completed)
-   
+
 ======== Update Spec ========
 Add Not to spec
 add assertions and printfs
@@ -63,3 +63,17 @@ Future questions to address in spec:
    Subtracting two unsigned numbers… Should talk to a math guy to figure it out
    What are shift left and shift right operations? HW doesn’t have these concepts. Need justification.
    What is lowered form? What is it for?
+
+======== Pass Ideas ==========
+Bounds checks for accessors
+Overflow checks for add/add-wrap
+Check combinational
+Fast C++ where wires/register/instances are predicated
+
+
+======== Next layer components =======
+Accelerator with config registers
+Schedulable
+   Decouple
+   Nack
+Scheduler
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 63c504a9..664b0a1f 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -2115,7 +2115,7 @@ defn emit! (o:OutputStream, e:Expression,top:Symbol) :
                print(o, " ")
                print(o, const)
       (e) : print-all(o, ["EMIT(" e ")"])
-      ;(e) : emit-all(o, ["mov'" prim-width(type(e)) " " e], top)
+      ;(e) : emit-all(o, ["mov'" prim-width(type(e)) " " e], top) ;TODO, not sure which one is right
 
 defn emit-s (o:OutputStream, s:Stmt, v:List<Symbol>, top:Symbol) :
    match(s) :
@@ -2129,7 +2129,7 @@ defn emit-s (o:OutputStream, s:Stmt, v:List<Symbol>, top:Symbol) :
       (s:Connect) : 
          if loc(s) typeof WritePort :
             val e = loc(s) as WritePort
-            val name = gensym("T")
+            val name = gensym(`F)
             emit-all(o, [top "::" name " = wr'" prim-width(type(e)) " " enable(e) " " top "::" mem(e) " " index(e) " " exp(s) "\n"], top)
          else :
             val n = name(loc(s) as Ref)
-- 
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