From 859d1019e6568585762615217348c7efc1b509e1 Mon Sep 17 00:00:00 2001
From: edwardcwang
Date: Thu, 11 Apr 2019 11:43:21 -0700
Subject: LowerTypesSpec: additional unit test (#1071)

---
 src/test/scala/firrtlTests/LowerTypesSpec.scala | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/src/test/scala/firrtlTests/LowerTypesSpec.scala b/src/test/scala/firrtlTests/LowerTypesSpec.scala
index 27f2c8a0..30ef795b 100644
--- a/src/test/scala/firrtlTests/LowerTypesSpec.scala
+++ b/src/test/scala/firrtlTests/LowerTypesSpec.scala
@@ -66,6 +66,21 @@ class LowerTypesSpec extends FirrtlFlatSpec {
     executeTest(input, expected)
   }
 
+  it should "lower mixed-direction ports" in {
+    val input =
+      """circuit Test :
+        |  module Test :
+        |    input foo : {flip a : UInt<1>, b : UInt<1>}[1]
+        |    foo is invalid
+      """.stripMargin
+    val expected = Seq(
+      "output foo_0_a : UInt<1>",
+      "input foo_0_b : UInt<1>"
+    ) map normalized
+
+    executeTest(input, expected)
+  }
+
   it should "lower registers" in {
     val input =
       """circuit Test :
-- 
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