From 75fd8d3eec98adb2f777e609ae1beea57ee5eedd Mon Sep 17 00:00:00 2001
From: Schuyler Eldridge
Date: Tue, 8 Oct 2019 14:04:44 -0400
Subject: Add test for TopWiringTransform idempotency

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
---
 .../firrtlTests/transforms/TopWiringTest.scala      | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
index 9dd290f8..1c01d6d2 100644
--- a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
+++ b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
@@ -17,7 +17,8 @@ import firrtl.annotations.{
    CircuitName,
    ModuleName,
    ComponentName,
-   Annotation
+   Annotation,
+   Target
 }
 import firrtl.transforms.TopWiring._
 
@@ -626,6 +627,24 @@ class TopWiringTests extends MiddleTransformSpec with TopWiringTestsCommon  {
        case _ => fail
      }
    }
+
+   "TopWiringTransform" should "remove TopWiringAnnotations" in {
+     val input =
+       """|circuit Top:
+          |  module Top:
+          |    wire foo: UInt<1>""".stripMargin
+
+     val bar =
+       Target
+         .deserialize("~Top|Top>foo")
+         .toNamed match { case a: ComponentName => a }
+
+     val annotations = Seq(TopWiringAnnotation(bar, "bar_"))
+     val outputState = (new TopWiringTransform).execute(CircuitState(Parser.parse(input), MidForm, annotations, None))
+
+     outputState.circuit.serialize should include ("output bar_foo")
+     outputState.annotations.toSeq should be (empty)
+   }
 }
 
 class AggregateTopWiringTests extends MiddleTransformSpec with TopWiringTestsCommon {
-- 
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