From ce1a91981e7fab75c8b41363b9ffcaedfcbef2e9 Mon Sep 17 00:00:00 2001
From: azidar
Date: Thu, 3 Nov 2016 10:43:18 -0700
Subject: Added Legalize to MiddleToLowFirrtl

Makes low firrtl more like a netlist, should probably update spec
---
 src/main/scala/firrtl/LoweringCompilers.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index f42d11ba..446df6d0 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -127,7 +127,8 @@ class MiddleFirrtlToLowFirrtl extends Transform with SimpleRun {
     passes.InferTypes,
     passes.ResolveGenders,
     passes.InferWidths,
-    passes.ConvertFixedToSInt)
+    passes.ConvertFixedToSInt,
+    passes.Legalize)
   def execute(circuit: Circuit, annotationMap: AnnotationMap): TransformResult =
     run(circuit, passSeq)
 }
-- 
cgit v1.2.3


From 324157eececc774401012577a92ae05082a7a12d Mon Sep 17 00:00:00 2001
From: azidar
Date: Thu, 3 Nov 2016 10:44:40 -0700
Subject: Updated future release with stricter low firrtl

---
 spec/future-release.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/spec/future-release.txt b/spec/future-release.txt
index a3bdc503..dd9eece5 100644
--- a/spec/future-release.txt
+++ b/spec/future-release.txt
@@ -4,3 +4,4 @@ Change tail -> drop
 Add ranges as a 'width' instead of actually declaring width.
   proposed syntax: wire x: UInt{0,10}
 Add Analog type, and 'attach' statement (see #87)
+Add constraints to low firrtl that assignments are same width, etc.
-- 
cgit v1.2.3