From 5fadf1210fb358e1f9aff628da8d369efdde9b4e Mon Sep 17 00:00:00 2001 From: Adam Izraelevitz Date: Tue, 21 Jul 2015 17:30:43 -0700 Subject: Firrtl generates verilog that compiles, but does not work --- src/main/stanza/compilers.stanza | 2 +- src/main/stanza/verilog.stanza | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index 063feb6f..c087e66e 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -96,6 +96,6 @@ public defn run-passes (c:Circuit,ls:List) : println(STANDARD-ERROR,"===== Time Breakdown =====") for x in time-table do : - println-all(STANDARD-ERROR,[x[0] " --- " to-float(x[1] as Int) / to-float(t - start-time) "%"]) + println-all(STANDARD-ERROR,[x[0] " --- " to-float(x[1] as Int * 100) / to-float(t - start-time) "%"]) println(STANDARD-ERROR,"==========================") println("Done!") diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index 2921c964..50794eeb 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -197,17 +197,14 @@ defn emit-module (m:InModule) : add(my-clk-update,[sym " <= " emit(cons[sym]) ";"]) updates[get-name(clock(s))] = my-clk-update (s:DefMemory) : - println(STANDARD-ERROR, s) val vtype = type(s) as VectorType add(regs,["reg " get-width(type(vtype)) " " sym " [0:" size(vtype) "];"]) add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"]) add(inits,[" " sym "[initvar] = {" width!(type(vtype)) "{$random}};"]) (s:DefNode) : - println(STANDARD-ERROR, s) add(wires,["wire " get-width(type(value(s))) " " sym ";"]) add(assigns,["assign " sym " = " emit(value(s)) ";"]) (s:DefInstance) : - println(STANDARD-ERROR, s) inst-ports[sym] = Vector() insts[sym] = name(module(s) as Ref) for f in fields(type(module(s)) as BundleType) do : -- cgit v1.2.3