From 4fefd791eed5ede508a7d47a3f21bf7790d05514 Mon Sep 17 00:00:00 2001 From: azidar Date: Wed, 30 Sep 2015 09:28:08 -0700 Subject: Fixed naming bug where __1 was matching. Caused lots o issues. --- src/main/stanza/ir-utils.stanza | 14 +++++++++----- src/main/stanza/passes.stanza | 10 +++++----- test/passes/expand-whens/reg-and-when.fir | 2 +- test/passes/infer-types/primops.fir | 4 ++-- test/passes/split-exp/split-in-when.fir | 4 ++-- 5 files changed, 19 insertions(+), 15 deletions(-) diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza index a234ff81..27acedb3 100644 --- a/src/main/stanza/ir-utils.stanza +++ b/src/main/stanza/ir-utils.stanza @@ -9,6 +9,11 @@ public defmulti print-debug (o:OutputStream, e:Expression|Stmt|Type|Port|Field|M ;============== GENSYM STUFF ====================== +defn generated? (s:String) -> False|Int : + for i in 1 to length(s) - 1 find : + val sub = substring(s,i + 1) + s[i] == '_' and digits?(sub) and s[i - 1] != '_' + public defn firrtl-gensym (s:Symbol) -> Symbol : firrtl-gensym(s,HashTable(symbol-hash)) public defn firrtl-gensym (sym-hash:HashTable) -> Symbol : @@ -31,11 +36,11 @@ public defn firrtl-gensym (s:Symbol,sym-hash:HashTable) -> Symbol : sym-hash[s] = 0 s val s* = to-string(s) - val i* = for i in 0 to length(s*) - 1 find : - s*[i] == '_' and digits?(substring(s*,i + 1)) - match(i*) : + val i* = generated?(s*) + val nex = match(i*) : (i:False) : get-name(s) (i:Int) : get-name(to-symbol(substring(s*,0,i))) + nex public defn get-sym-hash (m:InModule) -> HashTable : get-sym-hash(m,list()) @@ -45,8 +50,7 @@ public defn get-sym-hash (m:InModule,keywords:Streamable) -> HashTable False : val s* = to-string(s) - val i* = for i in 0 to length(s*) - 1 find : - s*[i] == '_' and digits?(substring(s*,i + 1)) + val i* = generated?(s*) match(i*) : (i:False) : if key?(sym-hash,s) : diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 9ac427db..5c045867 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -300,7 +300,7 @@ public defmethod short-name (b:RemoveSpecialChars) -> String : "rem-spec-chars" defn get-new-string (n:Char) -> String : switch {n == _} : - '_' : "_" + '_' : "__" '~' : "$A" '!' : "$B" '@' : "$C" @@ -1152,7 +1152,7 @@ defn lower-to-ground (c:Circuit) -> Circuit : ; (e:WRef) : name(e) ; (e:WSubfield) : symbol-join([get-name(exp(e)) `. name(e)]) ; (e:WIndex) : symbol-join([get-name(exp(e)) `. to-symbol(value(e))]) -; (e) : `T +; (e) : `F ; match(s) : ; (s:DecFromIndexer) : Begin $ ; if length(locs(s)) == 0 : list(EmptyStmt()) @@ -1212,7 +1212,7 @@ defn get-name (e:Expression) -> Symbol : (e:WRef) : name(e) (e:WSubfield) : symbol-join([get-name(exp(e)) `. name(e)]) (e:WIndex) : symbol-join([get-name(exp(e)) `. to-symbol(value(e))]) - (e) : `T + (e) : `F defn equality (e1:Expression,i:Int) -> Expression : DoPrim(EQUIV-OP,list(e1,UIntValue(BigIntLit(i),UnknownWidth())), @@ -2266,10 +2266,10 @@ defn split-exp (c:Circuit) : ;all-same-type? = false ;if not all-same-type? : ;val n* = - ; if n typeof False : firrtl-gensym(`T,sh) + ; if n typeof False : firrtl-gensym(`F,sh) ; else : firrtl-gensym(symbol-join([n as Symbol temp-delin]),sh) val n* = - if n typeof False : firrtl-gensym(`T,sh) + if n typeof False : firrtl-gensym(`F,sh) else : firrtl-gensym(n as Symbol,sh) add(v,DefNode(info,n*,map(split-exp-e{_,n,info},e))) WRef(n*,type(e),NodeKind(),UNKNOWN-GENDER) diff --git a/test/passes/expand-whens/reg-and-when.fir b/test/passes/expand-whens/reg-and-when.fir index 9d23acf9..ac678b6d 100644 --- a/test/passes/expand-whens/reg-and-when.fir +++ b/test/passes/expand-whens/reg-and-when.fir @@ -1,5 +1,5 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out ; cat %s.v | FileCheck %s -; CHECK: out_slow_bits <= fromhost_q$deq$valid ? fromhost_q$deq$bits : tohost_q$deq$bits; +; CHECK: out__slow__bits <= fromhost__q$deq$valid ? fromhost__q$deq$bits : tohost__q$deq$bits; circuit Top : module Top : input clock : Clock diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir index 94f481f7..ac057c68 100644 --- a/test/passes/infer-types/primops.fir +++ b/test/passes/infer-types/primops.fir @@ -157,10 +157,10 @@ circuit top : node wnot = not(a) ;CHECK: node wnot = not(a@)@ node unot = not(c) ;CHECK: node unot = not(c@)@ - node wand_ = and(a, b) ;CHECK: node wand_ = and(a@, b@)@ + node WAND = and(a, b) ;CHECK: node WAND = and(a@, b@)@ node uand = and(c, d) ;CHECK: node uand = and(c@, d@)@ - node wor_ = or(a, b) ;CHECK: node wor_ = or(a@, b@)@ + node WOR = or(a, b) ;CHECK: node WOR = or(a@, b@)@ node uor = or(c, d) ;CHECK: node uor = or(c@, d@)@ node wxor = xor(a, b) ;CHECK: node wxor = xor(a@, b@)@ diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir index ddf6a155..58819d22 100644 --- a/test/passes/split-exp/split-in-when.fir +++ b/test/passes/split-exp/split-in-when.fir @@ -13,11 +13,11 @@ circuit Top : when bit(subw(a,c),3) : out := mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b)) -;CHECK: node T = subw(a, c) +;CHECK: node F = subw(a, c) ;CHECK: node out_1 = eqv(UInt("h0"), UInt("hd")) ;CHECK: node out_3 = addw(b, c) ;CHECK: node out_2 = addw(a, out_3) ;CHECK: node out_4 = subw(c, b) -;CHECK: when bit(T, 3) : out := mux(out_1, out_2, out_4) +;CHECK: when bit(F, 3) : out := mux(out_1, out_2, out_4) ;CHECK: Finished Split Expressions -- cgit v1.2.3