From 487a611346d396346d33dae09123df8bab4ac5fa Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 19 Aug 2015 11:11:51 -0700
Subject: Fixed width inference bug where constraints were propagating
 backwards. Updated tests to match.

---
 src/main/stanza/passes.stanza      |  4 +---
 test/passes/infer-types/bundle.fir |  4 ++--
 test/passes/to-verilog/shr.fir     | 30 ++++++++++++++++++++++++++++++
 3 files changed, 33 insertions(+), 5 deletions(-)
 create mode 100644 test/passes/to-verilog/shr.fir

diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index b8bd572a..89f77694 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -215,7 +215,7 @@ defn hasWidth (e:?) :
 defn hasType (e:?) :
    e typeof Ref|Subfield|Index|DoPrim|WRef|WSubfield
       |WIndex|DefWire|DefRegister|DefMemory
-      |VectorType|Port|Field
+      |VectorType|Port|Field|UIntValue|SIntValue
 
 defn hasKind (e:?) :
    e typeof WRef
@@ -1955,13 +1955,11 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod
             val l = h[name(s)]
             val r = gen-constraints(value(s))
             add(v,WGeq(width!(l),width!(type(r))))
-            add(v,WGeq(width!(type(r)),width!(l)))
             DefNode(info(s),name(s),r)
          (s:Connect) : 
             val l = gen-constraints(loc(s))
             val e = gen-constraints(exp(s))
             add(v,WGeq(width!(type(l)),width!(type(e))))
-            add(v,WGeq(width!(type(e)),width!(type(l))))
             Connect(info(s),l,e)
          (s:Conditionally) : 
             val p = gen-constraints(pred(s))
diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir
index 98e48c0c..c24419b9 100644
--- a/test/passes/infer-types/bundle.fir
+++ b/test/passes/infer-types/bundle.fir
@@ -20,10 +20,10 @@ circuit top :
       a[8] := UInt(1)
       a[9] := UInt(1)
       node b = a[2]           ;CHECK: node b = a@<t:UInt<3>[10]@<t:UInt>>[2]@<t:UInt>
-      read accessor c = a[UInt(3)] ;CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt("h3")]
+      read accessor c = a[UInt(3)] ;CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt("h3")@<t:UInt>]
 ; CHECK: Finished Infer Types
 ; CHECK: Resolve Genders 
-; CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt("h3")]   
+; CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt("h3")@<t:UInt>]
 ; CHECK: Finished Resolve Genders 
 
 
diff --git a/test/passes/to-verilog/shr.fir b/test/passes/to-verilog/shr.fir
new file mode 100644
index 00000000..f710dc51
--- /dev/null
+++ b/test/passes/to-verilog/shr.fir
@@ -0,0 +1,30 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p cTd 2>&1 |  tee %s.out | FileCheck %s
+
+;CHECK: Infer Widths
+;CHECK: node s1_addr = cat(dtlb<t:{ resp$ppn : UInt<20><t:UInt<20>>}>.resp$ppn<t:UInt<20>>, bits(s1_req$addr<t:UInt<40>>, 11, 0)<t:UInt<12>>)<t:UInt<32>>
+;CHECK: Finished Infer Widths
+
+circuit HellaCache : 
+  module TLB_60 : 
+    output resp : {ppn : UInt<20>}
+    resp.ppn := UInt<1>("h00")
+
+  module HellaCache : 
+    input clock : Clock
+    input reset : UInt<1>
+
+    inst dtlb of TLB_60
+    reg s1_req : {addr : UInt<40>}, clock, reset
+    reg s2_req : {addr : UInt<40>}, clock, reset
+    reg s1_clk_en : UInt<1>, clock, reset
+
+    node T_928 = bits(s1_req.addr, 11, 0)
+    node s1_addr = cat(dtlb.resp.ppn, T_928)
+    when s1_clk_en :
+      s2_req.addr := s1_addr
+
+    s1_req.addr := UInt<?>(0)
+    s1_clk_en := UInt<?>(0)
+
+    wire foo : UInt<28>
+    foo := shr(s1_addr, 3)
-- 
cgit v1.2.3