From 4726d8b6ca56435d861cb74f52f1237e3b43ae38 Mon Sep 17 00:00:00 2001
From: azidar
Date: Thu, 1 Oct 2015 09:59:38 -0700
Subject: Updated tests for previous change that removed RemoveScope test from
 the StandardVerilogCompiler

---
 TODO                                  | 1 -
 test/errors/high-form/RemoveScope.fir | 1 +
 test/errors/high-form/Unique.fir      | 1 -
 3 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/TODO b/TODO
index b8086632..1c85c5f1 100644
--- a/TODO
+++ b/TODO
@@ -3,7 +3,6 @@ Support ASIC backend
      Mem of vec, should just work?
    ASIC rams (pass to replace smem with black box)
    Readwrite Port
-Move WorkingIR->RealIR right after width inference, update other passes accordingly
 
 ================================================
 ========== ADAM's BIG ARSE TODO LIST ============
diff --git a/test/errors/high-form/RemoveScope.fir b/test/errors/high-form/RemoveScope.fir
index 395c6492..16498fd8 100644
--- a/test/errors/high-form/RemoveScope.fir
+++ b/test/errors/high-form/RemoveScope.fir
@@ -1,4 +1,5 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; XFAIL: *
 ; CHECK: Done!
 
 circuit Top :
diff --git a/test/errors/high-form/Unique.fir b/test/errors/high-form/Unique.fir
index ea2bb881..60201b92 100644
--- a/test/errors/high-form/Unique.fir
+++ b/test/errors/high-form/Unique.fir
@@ -1,5 +1,4 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; XFAIL: *
 
 ; CHECK: Reference x does not have a unique name.
 ; CHECK: Reference p does not have a unique name.
-- 
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