From 144041a23329f258541e9d461b5bcc7f2284e686 Mon Sep 17 00:00:00 2001 From: Donggyu Kim Date: Fri, 2 Sep 2016 17:30:27 -0700 Subject: use case object for Kind --- src/main/scala/firrtl/Emitter.scala | 15 +++++++-------- src/main/scala/firrtl/Utils.scala | 4 ++-- src/main/scala/firrtl/WIR.scala | 16 ++++++++-------- src/main/scala/firrtl/passes/CheckInitialization.scala | 2 +- src/main/scala/firrtl/passes/Checks.scala | 2 +- src/main/scala/firrtl/passes/ExpandWhens.scala | 6 +++--- src/main/scala/firrtl/passes/InferReadWrite.scala | 4 ++-- src/main/scala/firrtl/passes/Inline.scala | 2 +- src/main/scala/firrtl/passes/LowerTypes.scala | 12 ++++++------ src/main/scala/firrtl/passes/MemUtils.scala | 3 +-- src/main/scala/firrtl/passes/Passes.scala | 4 ++-- src/main/scala/firrtl/passes/Resolves.scala | 12 ++++++------ .../scala/firrtl/passes/UpdateDuplicateMemMacros.scala | 2 +- 13 files changed, 41 insertions(+), 43 deletions(-) diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 0af002b2..85955088 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -85,11 +85,11 @@ class VerilogEmitter extends Emitter { else DoPrim(Eq, Seq(e.e1, zero), Nil, UIntType(IntWidth(1))) } - def wref(n: String, t: Type) = WRef(n, t, ExpKind(), UNKNOWNGENDER) + def wref(n: String, t: Type) = WRef(n, t, ExpKind, UNKNOWNGENDER) def remove_root(ex: Expression): Expression = ex match { case ex: WSubField => ex.exp match { case (e: WSubField) => remove_root(e) - case (_: WRef) => WRef(ex.name, ex.tpe, InstanceKind(), UNKNOWNGENDER) + case (_: WRef) => WRef(ex.name, ex.tpe, InstanceKind, UNKNOWNGENDER) } case _ => error("Shouldn't be here") } @@ -261,7 +261,7 @@ class VerilogEmitter extends Emitter { simlist += s s case (s: DefNode) => - val e = WRef(s.name, s.value.tpe, NodeKind(), MALE) + val e = WRef(s.name, s.value.tpe, NodeKind, MALE) netlist(e) = s.value s case (s) => s @@ -434,7 +434,7 @@ class VerilogEmitter extends Emitter { portdefs += Seq(p.direction, " ", p.tpe, " ", p.name) case Output => portdefs += Seq(p.direction, " ", p.tpe, " ", p.name) - val ex = WRef(p.name, p.tpe, PortKind(), FEMALE) + val ex = WRef(p.name, p.tpe, PortKind, FEMALE) assign(ex, netlist(ex)) } } @@ -458,7 +458,7 @@ class VerilogEmitter extends Emitter { s case (s: DefNode) => declare("wire", s.name, s.value.tpe) - assign(WRef(s.name, s.value.tpe, NodeKind(), MALE), s.value) + assign(WRef(s.name, s.value.tpe, NodeKind, MALE), s.value) s case (s: Stop) => val errorString = StringLit(s"${s.ret}\n".getBytes) @@ -468,12 +468,11 @@ class VerilogEmitter extends Emitter { simulate(s.clk, s.en, printf(s.string, s.args), Some("PRINTF_COND")) s case (s: WDefInstance) => - val es = create_exps(WRef(s.name, s.tpe, InstanceKind(), MALE)) + val es = create_exps(WRef(s.name, s.tpe, InstanceKind, MALE)) instantiate(s.name, s.module, es) s case (s: DefMemory) => - val mem = WRef(s.name, MemPortUtils.memType(s), - MemKind(s.readers ++ s.writers ++ s.readwriters), UNKNOWNGENDER) + val mem = WRef(s.name, MemPortUtils.memType(s), MemKind, UNKNOWNGENDER) def mem_exp (p: String, f: String) = { val t1 = field_type(mem.tpe, p) val t2 = field_type(t1, f) diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala index d9c74840..be4700e3 100644 --- a/src/main/scala/firrtl/Utils.scala +++ b/src/main/scala/firrtl/Utils.scala @@ -100,7 +100,7 @@ object Utils extends LazyLogging { } def create_exps(n: String, t: Type): Seq[Expression] = - create_exps(WRef(n, t, ExpKind(), UNKNOWNGENDER)) + create_exps(WRef(n, t, ExpKind, UNKNOWNGENDER)) def create_exps(e: Expression): Seq[Expression] = e match { case (e: Mux) => val e1s = create_exps(e.tval) @@ -325,7 +325,7 @@ object Utils extends LazyLogging { case e: WSubField => kind(e.exp) case e: WSubIndex => kind(e.exp) case e: WSubAccess => kind(e.exp) - case e => ExpKind() + case e => ExpKind } def gender(e: Expression): Gender = e match { case e: WRef => e.gender diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala index 9ff48446..9c63360c 100644 --- a/src/main/scala/firrtl/WIR.scala +++ b/src/main/scala/firrtl/WIR.scala @@ -34,14 +34,14 @@ import WrappedExpression._ import WrappedWidth._ trait Kind -case class WireKind() extends Kind -case class PoisonKind() extends Kind -case class RegKind() extends Kind -case class InstanceKind() extends Kind -case class PortKind() extends Kind -case class NodeKind() extends Kind -case class MemKind(ports: Seq[String]) extends Kind -case class ExpKind() extends Kind +case object WireKind extends Kind +case object PoisonKind extends Kind +case object RegKind extends Kind +case object InstanceKind extends Kind +case object PortKind extends Kind +case object NodeKind extends Kind +case object MemKind extends Kind +case object ExpKind extends Kind trait Gender case object MALE extends Gender diff --git a/src/main/scala/firrtl/passes/CheckInitialization.scala b/src/main/scala/firrtl/passes/CheckInitialization.scala index 69629bf0..f90ee277 100644 --- a/src/main/scala/firrtl/passes/CheckInitialization.scala +++ b/src/main/scala/firrtl/passes/CheckInitialization.scala @@ -92,7 +92,7 @@ object CheckInitialization extends Pass { case node: DefNode => val (hasVoid, voidDeps) = hasVoidExpr(node.value) if (hasVoid) { - val nodeRef = WRef(node.name, node.value.tpe, NodeKind(), MALE) + val nodeRef = WRef(node.name, node.value.tpe, NodeKind, MALE) voidExprs(nodeRef) = VoidExpr(node, voidDeps) } node diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala index c300f7c7..3ee97d08 100644 --- a/src/main/scala/firrtl/passes/Checks.scala +++ b/src/main/scala/firrtl/passes/Checks.scala @@ -469,7 +469,7 @@ object CheckGenders extends Pass { case (MALE, FEMALE) => errors append new WrongGender(info, mname, e.serialize, desired, gender) case (FEMALE, MALE) => kind(e) match { - case _: PortKind | _: InstanceKind if !flip_q(e.tpe) => // OK! + case PortKind | InstanceKind if !flip_q(e.tpe) => // OK! case _ => errors append new WrongGender(info, mname, e.serialize, desired, gender) } diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala index 5a7a7bac..6bd4bffd 100644 --- a/src/main/scala/firrtl/passes/ExpandWhens.scala +++ b/src/main/scala/firrtl/passes/ExpandWhens.scala @@ -53,7 +53,7 @@ object ExpandWhens extends Pass { // ========== Expand When Utilz ========== private def getFemaleRefs(n: String, t: Type, g: Gender): Seq[Expression] = { def getGender(t: Type, i: Int, g: Gender): Gender = times(g, get_flip(t, i, Default)) - val exps = create_exps(WRef(n, t, ExpKind(), g)) + val exps = create_exps(WRef(n, t, ExpKind, g)) (exps.zipWithIndex foldLeft Seq[Expression]()){ case (expsx, (exp, j)) => getGender(t, j, g) match { case (BIGENDER | FEMALE) => expsx :+ exp @@ -140,12 +140,12 @@ object ExpandWhens extends Pass { res match { case _: ValidIf | _: Mux | _: DoPrim => nodes get res match { case Some(name) => - netlist(lvalue) = WRef(name, res.tpe, NodeKind(), MALE) + netlist(lvalue) = WRef(name, res.tpe, NodeKind, MALE) EmptyStmt case None => val name = namespace.newTemp nodes(res) = name - netlist(lvalue) = WRef(name, res.tpe, NodeKind(), MALE) + netlist(lvalue) = WRef(name, res.tpe, NodeKind, MALE) DefNode(s.info, name, res) } case _ => diff --git a/src/main/scala/firrtl/passes/InferReadWrite.scala b/src/main/scala/firrtl/passes/InferReadWrite.scala index 664b3dfc..9fbd6ab3 100644 --- a/src/main/scala/firrtl/passes/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/InferReadWrite.scala @@ -128,7 +128,7 @@ object InferReadWritePass extends Pass { newName = s"rw_$idx" if !allPorts(newName) } yield newName).head - val rw_exp = WSubField(WRef(mem.name, ut, NodeKind(), ug), rw, ut, ug) + val rw_exp = WSubField(WRef(mem.name, ut, MemKind, ug), rw, ut, ug) readwriters += rw readers += r writers += w @@ -142,7 +142,7 @@ object InferReadWritePass extends Pass { repl(s"${mem.name}.$w.data") = WSubField(rw_exp, "wdata", mem.dataType, FEMALE) repl(s"${mem.name}.$w.mask") = WSubField(rw_exp, "wmask", ut, FEMALE) stmts += Connect(NoInfo, WSubField(rw_exp, "clk", ClockType, FEMALE), - WRef("clk", ClockType, NodeKind(), MALE)) + WRef("clk", ClockType, NodeKind, MALE)) stmts += Connect(NoInfo, WSubField(rw_exp, "en", bt, FEMALE), DoPrim(Or, List(connects(s"${mem.name}.$r.en"), connects(s"${mem.name}.$w.en")), Nil, bt)) stmts += Connect(NoInfo, WSubField(rw_exp, "addr", ut, FEMALE), diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala index 43c0ef1e..12dfb497 100644 --- a/src/main/scala/firrtl/passes/Inline.scala +++ b/src/main/scala/firrtl/passes/Inline.scala @@ -106,7 +106,7 @@ class InlineInstances (transID: TransID) extends Transform { if (inlinedInstances.contains(ref)) { val newName = ref + inlineDelim + field set(ComponentName(ref, ModuleName(m.name, cname)), Seq.empty) - WRef(newName, tpe, WireKind(), gen) + WRef(newName, tpe, WireKind, gen) } else e } diff --git a/src/main/scala/firrtl/passes/LowerTypes.scala b/src/main/scala/firrtl/passes/LowerTypes.scala index b3969bea..967b4a1c 100644 --- a/src/main/scala/firrtl/passes/LowerTypes.scala +++ b/src/main/scala/firrtl/passes/LowerTypes.scala @@ -120,11 +120,11 @@ object LowerTypes extends Pass { info: Info, mname: String)(e: Expression): Expression = e match { case e: WRef => e case (_: WSubField | _: WSubIndex) => kind(e) match { - case k: InstanceKind => + case InstanceKind => val (root, tail) = splitRef(e) val name = loweredName(tail) WSubField(root, name, e.tpe, gender(e)) - case k: MemKind => + case MemKind => val exps = lowerTypesMemExp(memDataTypeMap, info, mname)(e) exps.size match { case 1 => exps.head @@ -163,7 +163,7 @@ object LowerTypes extends Pass { case s: WDefInstance => s.tpe match { case t: BundleType => val fieldsx = t.fields flatMap (f => - create_exps(WRef(f.name, f.tpe, ExpKind(), times(f.flip, MALE))) map ( + create_exps(WRef(f.name, f.tpe, ExpKind, times(f.flip, MALE))) map ( // Flip because inst genders are reversed from Module type e => Field(loweredName(e), swap(to_flip(gender(e))), e.tpe))) WDefInstance(s.info, s.name, s.module, BundleType(fieldsx)) @@ -188,12 +188,12 @@ object LowerTypes extends Pass { val exps = create_exps(s.value) map lowerTypesExp(memDataTypeMap, info, mname) Block(names zip exps map { case (n, e) => DefNode(info, loweredName(n), e) }) case s: IsInvalid => kind(s.expr) match { - case _: MemKind => + case MemKind => Block(lowerTypesMemExp(memDataTypeMap, info, mname)(s.expr) map (IsInvalid(info, _))) case _ => s map lowerTypesExp(memDataTypeMap, info, mname) } case s: Connect => kind(s.loc) match { - case k: MemKind => + case MemKind => val exp = lowerTypesExp(memDataTypeMap, info, mname)(s.expr) val locs = lowerTypesMemExp(memDataTypeMap, info, mname)(s.loc) Block(locs map (Connect(info, _, exp))) @@ -207,7 +207,7 @@ object LowerTypes extends Pass { val memDataTypeMap = new MemDataTypeMap // Lower Ports val portsx = m.ports flatMap { p => - val exps = create_exps(WRef(p.name, p.tpe, PortKind(), to_gender(p.direction))) + val exps = create_exps(WRef(p.name, p.tpe, PortKind, to_gender(p.direction))) exps map (e => Port(p.info, loweredName(e), to_dir(gender(e)), e.tpe)) } m match { diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala index 57a7120b..21884661 100644 --- a/src/main/scala/firrtl/passes/MemUtils.scala +++ b/src/main/scala/firrtl/passes/MemUtils.scala @@ -229,9 +229,8 @@ object MemPortUtils { (mem.readwriters map (Field(_, Flip, rwType)))) } - def kind(s: DefMemory) = MemKind(s.readers ++ s.writers ++ s.readwriters) def memPortField(s: DefMemory, p: String, f: String) = { - val mem = WRef(s.name, memType(s), kind(s), UNKNOWNGENDER) + val mem = WRef(s.name, memType(s), MemKind, UNKNOWNGENDER) val t1 = field_type(mem.tpe, p) val t2 = field_type(t1, f) WSubField(WSubField(mem, p, t1, UNKNOWNGENDER), f, t2, UNKNOWNGENDER) diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala index 965ae339..9057c60d 100644 --- a/src/main/scala/firrtl/passes/Passes.scala +++ b/src/main/scala/firrtl/passes/Passes.scala @@ -59,8 +59,8 @@ class Errors { object ToWorkingIR extends Pass { def name = "Working IR" - def toExp(e:Expression) : Expression = e map (toExp) match { - case e: Reference => WRef(e.name, e.tpe, NodeKind(), UNKNOWNGENDER) + def toExp(e: Expression): Expression = e map (toExp) match { + case e: Reference => WRef(e.name, e.tpe, NodeKind, UNKNOWNGENDER) case e: SubField => WSubField(e.expr, e.name, e.tpe, UNKNOWNGENDER) case e: SubIndex => WSubIndex(e.expr, e.value, e.tpe, UNKNOWNGENDER) case e: SubAccess => WSubAccess(e.expr, e.index, e.tpe, UNKNOWNGENDER) diff --git a/src/main/scala/firrtl/passes/Resolves.scala b/src/main/scala/firrtl/passes/Resolves.scala index 3100f0c3..616e30f3 100644 --- a/src/main/scala/firrtl/passes/Resolves.scala +++ b/src/main/scala/firrtl/passes/Resolves.scala @@ -36,16 +36,16 @@ object ResolveKinds extends Pass { type KindMap = collection.mutable.LinkedHashMap[String, Kind] def find_port(kinds: KindMap)(p: Port): Port = { - kinds(p.name) = PortKind() ; p + kinds(p.name) = PortKind ; p } def find_stmt(kinds: KindMap)(s: Statement):Statement = { s match { - case s: DefWire => kinds(s.name) = WireKind() - case s: DefNode => kinds(s.name) = NodeKind() - case s: DefRegister => kinds(s.name) = RegKind() - case s: WDefInstance => kinds(s.name) = InstanceKind() - case s: DefMemory => kinds(s.name) = MemKind(s.readers ++ s.writers ++ s.readwriters) + case s: DefWire => kinds(s.name) = WireKind + case s: DefNode => kinds(s.name) = NodeKind + case s: DefRegister => kinds(s.name) = RegKind + case s: WDefInstance => kinds(s.name) = InstanceKind + case s: DefMemory => kinds(s.name) = MemKind case s => } s map find_stmt(kinds) diff --git a/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala b/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala index 81684d90..0098fa5f 100644 --- a/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala +++ b/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala @@ -12,7 +12,7 @@ import firrtl.Utils._ object MemTransformUtils { - def createRef(n: String) = WRef(n, UnknownType, ExpKind(), UNKNOWNGENDER) + def createRef(n: String) = WRef(n, UnknownType, ExpKind, UNKNOWNGENDER) def createSubField(exp: Expression, n: String) = WSubField(exp, n, UnknownType, UNKNOWNGENDER) def connectFields(lref: Expression, lname: String, rref: Expression, rname: String) = Connect(NoInfo, createSubField(lref, lname), createSubField(rref, rname)) -- cgit v1.2.3 From a8d7e31e5cbe6c387930f8d4ef48fda19e59f465 Mon Sep 17 00:00:00 2001 From: Donggyu Kim Date: Thu, 8 Sep 2016 21:49:43 -0700 Subject: cache IntWidths to avoid redudant object creations --- src/main/scala/firrtl/ir/IR.scala | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/src/main/scala/firrtl/ir/IR.scala b/src/main/scala/firrtl/ir/IR.scala index cdbf2fd7..87072eec 100644 --- a/src/main/scala/firrtl/ir/IR.scala +++ b/src/main/scala/firrtl/ir/IR.scala @@ -300,8 +300,39 @@ abstract class Width extends FirrtlNode { } } /** Positive Integer Bit Width of a [[GroundType]] */ -case class IntWidth(width: BigInt) extends Width { +object IntWidth { + private val maxCached = 1024 + private val cache = new Array[IntWidth](maxCached + 1) + def apply(width: BigInt): IntWidth = { + if (0 <= width && width <= maxCached) { + val i = width.toInt + var w = cache(i) + if (w eq null) { + w = new IntWidth(width) + cache(i) = w + } + w + } else new IntWidth(width) + } + // For pattern matching + def unapply(w: IntWidth): Option[BigInt] = Some(w.width) +} +class IntWidth(val width: BigInt) extends Width with Product { def serialize: String = s"<$width>" + override def equals(that: Any) = that match { + case w: IntWidth => width == w.width + case _ => false + } + override def hashCode = width.toInt + override def productPrefix = "IntWidth" + override def toString = s"$productPrefix($width)" + def copy(width: BigInt = width) = IntWidth(width) + def canEqual(that: Any) = that.isInstanceOf[Width] + def productArity = 1 + def productElement(int: Int) = int match { + case 0 => width + case _ => throw new IndexOutOfBoundsException + } } case object UnknownWidth extends Width { def serialize: String = "" -- cgit v1.2.3 From b6a12c77223f50be57a682fb4be198ed8ffc3511 Mon Sep 17 00:00:00 2001 From: Donggyu Kim Date: Thu, 8 Sep 2016 22:16:48 -0700 Subject: use case object for WVoid, WInvalid --- src/main/scala/firrtl/Utils.scala | 2 +- src/main/scala/firrtl/WIR.scala | 8 ++++---- src/main/scala/firrtl/passes/CheckInitialization.scala | 2 +- src/main/scala/firrtl/passes/ExpandWhens.scala | 14 +++++++------- 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala index be4700e3..bc1ca704 100644 --- a/src/main/scala/firrtl/Utils.scala +++ b/src/main/scala/firrtl/Utils.scala @@ -337,7 +337,7 @@ object Utils extends LazyLogging { case e: SIntLiteral => MALE case e: Mux => MALE case e: ValidIf => MALE - case e: WInvalid => MALE + case WInvalid => MALE case e => println(e); error("Shouldn't be here") } def get_gender(s: Statement): Gender = s match { diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala index 9c63360c..06b5be48 100644 --- a/src/main/scala/firrtl/WIR.scala +++ b/src/main/scala/firrtl/WIR.scala @@ -73,14 +73,14 @@ case class WSubAccess(exp: Expression, index: Expression, tpe: Type, gender: Gen def mapType(f: Type => Type): Expression = this.copy(tpe = f(tpe)) def mapWidth(f: Width => Width): Expression = this } -case class WVoid() extends Expression { +case object WVoid extends Expression { def tpe = UnknownType def serialize: String = "VOID" def mapExpr(f: Expression => Expression): Expression = this def mapType(f: Type => Type): Expression = this def mapWidth(f: Width => Width): Expression = this } -case class WInvalid() extends Expression { +case object WInvalid extends Expression { def tpe = UnknownType def serialize: String = "INVALID" def mapExpr(f: Expression => Expression): Expression = this @@ -126,8 +126,8 @@ class WrappedExpression (val e1: Expression) { case (e1: WSubField, e2: WSubField) => (e1.name equals e2.name) && weq(e1.exp,e2.exp) case (e1: WSubIndex, e2: WSubIndex) => (e1.value == e2.value) && weq(e1.exp,e2.exp) case (e1: WSubAccess, e2: WSubAccess) => weq(e1.index,e2.index) && weq(e1.exp,e2.exp) - case (e1: WVoid, e2: WVoid) => true - case (e1: WInvalid, e2: WInvalid) => true + case (WVoid, WVoid) => true + case (WInvalid, WInvalid) => true case (e1: DoPrim, e2: DoPrim) => e1.op == e2.op && ((e1.consts zip e2.consts) forall {case (x, y) => x == y}) && ((e1.args zip e2.args) forall {case (x, y) => weq(x, y)}) diff --git a/src/main/scala/firrtl/passes/CheckInitialization.scala b/src/main/scala/firrtl/passes/CheckInitialization.scala index f90ee277..7d7f2f32 100644 --- a/src/main/scala/firrtl/passes/CheckInitialization.scala +++ b/src/main/scala/firrtl/passes/CheckInitialization.scala @@ -69,7 +69,7 @@ object CheckInitialization extends Pass { var void = false val voidDeps = collection.mutable.ArrayBuffer[Expression]() def hasVoid(e: Expression): Expression = e match { - case e: WVoid => + case WVoid => void = true e case (_: WRef | _: WSubField) => diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala index 6bd4bffd..deea3c0e 100644 --- a/src/main/scala/firrtl/passes/ExpandWhens.scala +++ b/src/main/scala/firrtl/passes/ExpandWhens.scala @@ -63,7 +63,7 @@ object ExpandWhens extends Pass { } private def expandNetlist(netlist: Netlist) = netlist map { - case (k, WInvalid()) => IsInvalid(NoInfo, k.e1) + case (k, WInvalid) => IsInvalid(NoInfo, k.e1) case (k, v) => Connect(NoInfo, k.e1, v) } // Searches nested scopes of defaults for lvalue @@ -97,7 +97,7 @@ object ExpandWhens extends Pass { p: Expression) (s: Statement): Statement = s match { case w: DefWire => - netlist ++= (getFemaleRefs(w.name, w.tpe, BIGENDER) map (ref => we(ref) -> WVoid())) + netlist ++= (getFemaleRefs(w.name, w.tpe, BIGENDER) map (ref => we(ref) -> WVoid)) w case r: DefRegister => netlist ++= (getFemaleRefs(r.name, r.tpe, BIGENDER) map (ref => we(ref) -> ref)) @@ -106,7 +106,7 @@ object ExpandWhens extends Pass { netlist(c.loc) = c.expr EmptyStmt case c: IsInvalid => - netlist(c.expr) = WInvalid() + netlist(c.expr) = WInvalid EmptyStmt case s: Conditionally => val conseqNetlist = new Netlist @@ -127,9 +127,9 @@ object ExpandWhens extends Pass { val trueValue = conseqNetlist getOrElse (lvalue, defaultValue) val falseValue = altNetlist getOrElse (lvalue, defaultValue) (trueValue, falseValue) match { - case (WInvalid(), WInvalid()) => WInvalid() - case (WInvalid(), fv) => ValidIf(NOT(s.pred), fv, fv.tpe) - case (tv, WInvalid()) => ValidIf(s.pred, tv, tv.tpe) + case (WInvalid, WInvalid) => WInvalid + case (WInvalid, fv) => ValidIf(NOT(s.pred), fv, fv.tpe) + case (tv, WInvalid) => ValidIf(s.pred, tv, tv.tpe) case (tv, fv) => Mux(s.pred, tv, fv, mux_type_and_widths(tv, fv)) } case None => @@ -165,7 +165,7 @@ object ExpandWhens extends Pass { val netlist = new Netlist // Add ports to netlist netlist ++= (m.ports flatMap { case Port(_, name, dir, tpe) => - getFemaleRefs(name, tpe, to_gender(dir)) map (ref => we(ref) -> WVoid()) + getFemaleRefs(name, tpe, to_gender(dir)) map (ref => we(ref) -> WVoid) }) (netlist, simlist, expandWhens(netlist, Seq(netlist), one)(m.body)) } -- cgit v1.2.3 From 1f90624762c419ab8e2ac51f9ddbca58fff07815 Mon Sep 17 00:00:00 2001 From: Donggyu Kim Date: Thu, 8 Sep 2016 22:17:02 -0700 Subject: remove VIndent --- src/main/scala/firrtl/Emitter.scala | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 85955088..26b1f3d9 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -53,7 +53,6 @@ object FIRRTLEmitter extends Emitter { def run(c: Circuit, w: Writer) = w.write(c.serialize) } -case class VIndent() case class VRandom(width: BigInt) extends Expression { def tpe = UIntType(IntWidth(width)) def nWords = (width + 31) / 32 @@ -127,7 +126,6 @@ class VerilogEmitter extends Emitter { case (i: Int) => w write i.toString case (i: Long) => w write i.toString case (i: BigInt) => w write i.toString - case (t: VIndent) => w write " " case (s: Seq[Any]) => s foreach (emit(_, top + 1)) if (top == 0) w write "\n" -- cgit v1.2.3 From 41c78f9854124986e812fd7c7363d404fdb64b0b Mon Sep 17 00:00:00 2001 From: Donggyu Kim Date: Thu, 8 Sep 2016 22:53:40 -0700 Subject: use BoolType for UIntType(IntWidth(1)) --- src/main/scala/firrtl/passes/ExpandWhens.scala | 4 ++-- src/main/scala/firrtl/passes/MemUtils.scala | 4 ++-- src/main/scala/firrtl/passes/Passes.scala | 4 ++-- src/main/scala/firrtl/passes/RemoveAccesses.scala | 2 +- src/main/scala/firrtl/passes/RemoveCHIRRTL.scala | 2 +- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala index deea3c0e..4cc0bdb9 100644 --- a/src/main/scala/firrtl/passes/ExpandWhens.scala +++ b/src/main/scala/firrtl/passes/ExpandWhens.scala @@ -80,9 +80,9 @@ object ExpandWhens extends Pass { } private def AND(e1: Expression, e2: Expression) = - DoPrim(And, Seq(e1, e2), Nil, UIntType(IntWidth(1))) + DoPrim(And, Seq(e1, e2), Nil, BoolType) private def NOT(e: Expression) = - DoPrim(Eq, Seq(e, zero), Nil, UIntType(IntWidth(1))) + DoPrim(Eq, Seq(e, zero), Nil, BoolType) // ------------ Pass ------------------- def run(c: Circuit): Circuit = { diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala index 21884661..505ad0da 100644 --- a/src/main/scala/firrtl/passes/MemUtils.scala +++ b/src/main/scala/firrtl/passes/MemUtils.scala @@ -193,7 +193,7 @@ object MemPortUtils { def rwPortToFlattenBundle(mem: DefMemory) = BundleType( defaultPortSeq(mem) ++ Seq( - Field("wmode", Default, UIntType(IntWidth(1))), + Field("wmode", Default, BoolType), Field("wdata", Default, flattenType(mem.dataType)), Field("rdata", Flip, flattenType(mem.dataType)) ) ++ (if (!containsInfo(mem.info, "maskGran")) Nil @@ -220,7 +220,7 @@ object MemPortUtils { Field("mask", Default, createMask(mem.dataType)))) val rwType = BundleType(defaultPortSeq(mem) ++ Seq( Field("rdata", Flip, mem.dataType), - Field("wmode", Default, UIntType(IntWidth(1))), + Field("wmode", Default, BoolType), Field("wdata", Default, mem.dataType), Field("wmask", Default, createMask(mem.dataType)))) BundleType( diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala index 9057c60d..7f53fac8 100644 --- a/src/main/scala/firrtl/passes/Passes.scala +++ b/src/main/scala/firrtl/passes/Passes.scala @@ -200,9 +200,9 @@ object Legalize extends Pass { lazy val msb = width - 1 if (amount >= width) { e.tpe match { - case UIntType(_) => UIntLiteral(0, IntWidth(1)) + case UIntType(_) => zero case SIntType(_) => - val bits = DoPrim(Bits, e.args, Seq(msb, msb), UIntType(IntWidth(1))) + val bits = DoPrim(Bits, e.args, Seq(msb, msb), BoolType) DoPrim(AsSInt, Seq(bits), Seq.empty, SIntType(IntWidth(1))) case t => error(s"Unsupported type ${t} for Primop Shift Right") } diff --git a/src/main/scala/firrtl/passes/RemoveAccesses.scala b/src/main/scala/firrtl/passes/RemoveAccesses.scala index 08f08eac..933c3543 100644 --- a/src/main/scala/firrtl/passes/RemoveAccesses.scala +++ b/src/main/scala/firrtl/passes/RemoveAccesses.scala @@ -15,7 +15,7 @@ object RemoveAccesses extends Pass { def name = "Remove Accesses" private def AND(e1: Expression, e2: Expression) = - DoPrim(And, Seq(e1, e2), Nil, UIntType(IntWidth(1))) + DoPrim(And, Seq(e1, e2), Nil, BoolType) private def EQV(e1: Expression, e2: Expression): Expression = DoPrim(Eq, Seq(e1, e2), Nil, e1.tpe) diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala index ca860ab6..b71c0dc3 100644 --- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala +++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala @@ -174,7 +174,7 @@ object RemoveCHIRRTL extends Pass { case Some(p) => g match { case FEMALE => has_write_mport = true - if (p.rdwrite) has_readwrite_mport = Some(SubField(p.exp, "wmode", UIntType(IntWidth(1)))) + if (p.rdwrite) has_readwrite_mport = Some(SubField(p.exp, "wmode", BoolType)) SubField(p.exp, p.female, tpe) case MALE => SubField(p.exp, p.male, tpe) -- cgit v1.2.3