From aa5eb968b837a4c35c5361b5f567411766c52184 Mon Sep 17 00:00:00 2001 From: azidar Date: Wed, 22 Apr 2015 10:19:12 -0700 Subject: added new stanza with correct parser --- src/lib/stanza.zip | Bin 3758011 -> 3695332 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/src/lib/stanza.zip b/src/lib/stanza.zip index fb9ac7d7..5fd5ff6d 100644 Binary files a/src/lib/stanza.zip and b/src/lib/stanza.zip differ -- cgit v1.2.3 From 3862865b8c70dd21e1a436dd79cfd165bebe5f43 Mon Sep 17 00:00:00 2001 From: azidar Date: Thu, 23 Apr 2015 15:27:43 -0700 Subject: Added new parser. Fixed all Tests. Added on-reset to parser, but don't correctly handle it in compiler. --- TODO | 5 +- src/main/stanza/firrtl-ir.stanza | 3 + src/main/stanza/ir-parser.stanza | 503 ++++++++++++--------- src/main/stanza/ir-utils.stanza | 9 +- src/main/stanza/passes.stanza | 2 +- test/passes/expand-accessors/accessor-mem.fir | 10 +- test/passes/expand-accessors/accessor-vec.fir | 22 +- test/passes/expand-connect-indexed/bundle-vecs.fir | 14 +- test/passes/expand-whens/one-when.fir | 14 +- test/passes/expand-whens/partial-init.fir | 4 +- test/passes/expand-whens/two-when.fir | 14 +- test/passes/infer-types/bundle.fir | 11 +- test/passes/infer-types/gcd.fir | 28 +- test/passes/infer-types/primops.fir | 10 +- test/passes/infer-widths/gcd.fir | 18 +- test/passes/infer-widths/simple.fir | 6 +- test/passes/inline/gcd.fir | 18 +- test/passes/jacktest/SIntOps.fir | 32 +- test/passes/jacktest/UIntOps.fir | 30 +- test/passes/jacktest/gcd.fir | 16 +- test/passes/jacktest/gcd2.fir | 16 +- test/passes/jacktest/risc.fir | 50 +- test/passes/jacktest/testlower.fir | 22 +- test/passes/jacktest/vecshift.fir | 28 +- test/passes/lower-to-ground/accessor.fir | 20 +- test/passes/lower-to-ground/bundle-vecs.fir | 18 +- test/passes/lower-to-ground/bundle.fir | 4 +- test/passes/lower-to-ground/nested-vec.fir | 22 +- test/passes/lower-to-ground/register.fir | 6 +- test/passes/make-explicit-reset/mix-reset.fir | 26 +- test/passes/resolve-genders/accessor.fir | 2 +- test/passes/resolve-genders/bigenders.fir | 6 +- test/passes/resolve-genders/bulk.fir | 4 +- test/passes/resolve-genders/gcd.fir | 18 +- test/passes/resolve-genders/ports.fir | 10 +- test/passes/resolve-genders/subbundle.fir | 4 +- test/passes/resolve-kinds/gcd.fir | 18 +- test/passes/split-exp/gcd.fir | 18 +- test/passes/to-flo/gcd.fir | 18 +- 39 files changed, 580 insertions(+), 499 deletions(-) diff --git a/TODO b/TODO index 818b78c3..c2a8180d 100644 --- a/TODO +++ b/TODO @@ -4,16 +4,13 @@ ======== Current Tasks ======== on-reset -Parser - Error if incorrectly assign stuff, like use = instead of := - Update parser and update tests Make instances always male, flip the bundles on declaration dlsh,drsh move Infer-Widths to before vec expansion? +Add Unit Tests for each pass ======== Update Core ========== Add source locaters -Add Unit Tests for each pass ======== Check Passes ========== Well-formed high firrtl diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza index f14378cc..6a0b193c 100644 --- a/src/main/stanza/firrtl-ir.stanza +++ b/src/main/stanza/firrtl-ir.stanza @@ -192,6 +192,9 @@ public defstruct Conditionally <: Stmt : alt: Stmt public defstruct Begin <: Stmt : ;LOW body: List +public defstruct OnReset <: Stmt : ;LOW + reg: Expression + exp: Expression public defstruct Connect <: Stmt : ;LOW loc: Expression exp: Expression diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza index 1772d773..c5296dc0 100644 --- a/src/main/stanza/ir-parser.stanza +++ b/src/main/stanza/ir-parser.stanza @@ -5,241 +5,320 @@ defpackage firrtl/parser : import stz/parser import stz/lexer -;======= Convenience Functions ==== -defn throw-error (x) : +;======= Convenience Functions ======== +defn first-info? (form) -> FileInfo|False : + match(form) : + (form:Token) : info(form) + (form:List) : search(first-info?, form) + (form) : false + +defn first-info (form:List) : + match(first-info?(form)) : + (i:FileInfo) : i + (f:False) : FileInfo() + +defn FPE (form, x) : throw $ new Exception : defmethod print (o:OutputStream, this) : - print(o, x) + print(o, "[~] FIRRTL Parsing Error: ~" << [first-info(form), x]) + +defn* apply-suffix-ops (x, fs:List) : + if empty?(fs) : x + else : apply-suffix-ops(head(fs)(x), tail(fs)) -defn ut (x) : - unwrap-token(x) +;======== Parser Utilities ============== +defn atom? (x) : unwrap-token(x) not-typeof List -;======== SYNTAX ======================= +defn primop (x:Symbol) : get?(OPERATORS, x, false) +val OPERATORS = HashTable(symbol-hash) +OPERATORS[`add] = ADD-OP +OPERATORS[`add-uu] = ADD-UU-OP +OPERATORS[`add-us] = ADD-US-OP +OPERATORS[`add-su] = ADD-SU-OP +OPERATORS[`add-ss] = ADD-SS-OP +OPERATORS[`sub] = SUB-OP +OPERATORS[`sub-uu] = SUB-UU-OP +OPERATORS[`sub-us] = SUB-US-OP +OPERATORS[`sub-su] = SUB-SU-OP +OPERATORS[`sub-ss] = SUB-SS-OP +OPERATORS[`mul] = MUL-OP +OPERATORS[`mul-uu] = MUL-UU-OP +OPERATORS[`mul-us] = MUL-US-OP +OPERATORS[`mul-su] = MUL-SU-OP +OPERATORS[`mul-ss] = MUL-SS-OP +OPERATORS[`div] = DIV-OP +OPERATORS[`div-uu] = DIV-UU-OP +OPERATORS[`div-us] = DIV-US-OP +OPERATORS[`div-su] = DIV-SU-OP +OPERATORS[`div-ss] = DIV-SS-OP +OPERATORS[`mod] = MOD-OP +OPERATORS[`mod-uu] = MOD-UU-OP +OPERATORS[`mod-us] = MOD-US-OP +OPERATORS[`mod-su] = MOD-SU-OP +OPERATORS[`mod-ss] = MOD-SS-OP +OPERATORS[`quo] = QUO-OP +OPERATORS[`quo-uu] = QUO-UU-OP +OPERATORS[`quo-us] = QUO-US-OP +OPERATORS[`quo-su] = QUO-SU-OP +OPERATORS[`quo-ss] = QUO-SS-OP +OPERATORS[`rem] = REM-OP +OPERATORS[`rem-uu] = REM-UU-OP +OPERATORS[`rem-us] = REM-US-OP +OPERATORS[`rem-su] = REM-SU-OP +OPERATORS[`rem-ss] = REM-SS-OP +OPERATORS[`add-wrap] = ADD-WRAP-OP +OPERATORS[`add-wrap-uu] = ADD-WRAP-UU-OP +OPERATORS[`add-wrap-us] = ADD-WRAP-US-OP +OPERATORS[`add-wrap-su] = ADD-WRAP-SU-OP +OPERATORS[`add-wrap-ss] = ADD-WRAP-SS-OP +OPERATORS[`sub-wrap] = SUB-WRAP-OP +OPERATORS[`sub-wrap-uu] = SUB-WRAP-UU-OP +OPERATORS[`sub-wrap-us] = SUB-WRAP-US-OP +OPERATORS[`sub-wrap-su] = SUB-WRAP-SU-OP +OPERATORS[`sub-wrap-ss] = SUB-WRAP-SS-OP +OPERATORS[`lt] = LESS-OP +OPERATORS[`lt-uu] = LESS-UU-OP +OPERATORS[`lt-us] = LESS-US-OP +OPERATORS[`lt-su] = LESS-SU-OP +OPERATORS[`lt-ss] = LESS-SS-OP +OPERATORS[`leq] = LESS-EQ-OP +OPERATORS[`leq-uu] = LESS-EQ-UU-OP +OPERATORS[`leq-us] = LESS-EQ-US-OP +OPERATORS[`leq-su] = LESS-EQ-SU-OP +OPERATORS[`leq-ss] = LESS-EQ-SS-OP +OPERATORS[`gt] = GREATER-OP +OPERATORS[`gt-uu] = GREATER-UU-OP +OPERATORS[`gt-us] = GREATER-US-OP +OPERATORS[`gt-su] = GREATER-SU-OP +OPERATORS[`gt-ss] = GREATER-SS-OP +OPERATORS[`geq] = GREATER-EQ-OP +OPERATORS[`geq-uu] = GREATER-EQ-UU-OP +OPERATORS[`geq-us] = GREATER-EQ-US-OP +OPERATORS[`geq-su] = GREATER-EQ-SU-OP +OPERATORS[`geq-ss] = GREATER-EQ-SS-OP +OPERATORS[`eq] = EQUAL-OP +OPERATORS[`eq-uu] = EQUAL-UU-OP +OPERATORS[`eq-ss] = EQUAL-SS-OP +OPERATORS[`neq] = NEQUAL-OP +OPERATORS[`neq-uu] = NEQUAL-UU-OP +OPERATORS[`neq-ss] = NEQUAL-SS-OP +OPERATORS[`mux] = MUX-OP +OPERATORS[`mux-uu] = MUX-UU-OP +OPERATORS[`mux-ss] = MUX-SS-OP +OPERATORS[`pad] = PAD-OP +OPERATORS[`pad-u] = PAD-U-OP +OPERATORS[`pad-s] = PAD-S-OP +OPERATORS[`neg] = NEG-OP +OPERATORS[`neg-u] = NEG-U-OP +OPERATORS[`neg-s] = NEG-S-OP +OPERATORS[`as-UInt] = AS-UINT-OP +OPERATORS[`as-UInt-u] = AS-UINT-U-OP +OPERATORS[`as-UInt-s] = AS-UINT-S-OP +OPERATORS[`as-SInt] = AS-SINT-OP +OPERATORS[`as-SInt-u] = AS-SINT-U-OP +OPERATORS[`as-SInt-s] = AS-SINT-S-OP +OPERATORS[`shl] = SHIFT-LEFT-OP +OPERATORS[`shl-u] = SHIFT-LEFT-U-OP +OPERATORS[`shl-s] = SHIFT-LEFT-S-OP +OPERATORS[`shr] = SHIFT-RIGHT-OP +OPERATORS[`shr-u] = SHIFT-RIGHT-U-OP +OPERATORS[`shr-s] = SHIFT-RIGHT-S-OP +OPERATORS[`convert] = CONVERT-OP +OPERATORS[`convert-u] = CONVERT-U-OP +OPERATORS[`convert-s] = CONVERT-S-OP +OPERATORS[`bit-and-reduce] = BIT-AND-REDUCE-OP +OPERATORS[`bit-or-reduce] = BIT-OR-REDUCE-OP +OPERATORS[`bit-xor-reduce] = BIT-XOR-REDUCE-OP +OPERATORS[`bit-and] = BIT-AND-OP +OPERATORS[`bit-or] = BIT-OR-OP +OPERATORS[`bit-xor] = BIT-XOR-OP +OPERATORS[`cat] = CONCAT-OP +OPERATORS[`bit] = BIT-SELECT-OP +OPERATORS[`bits] = BITS-SELECT-OP + +;======== Parser Rules ================== defsyntax firrtl : + ;Useful Atoms + defrule atoms : + ;Unconditionally parse next form as identifier. + id = (?x) when atom?(x) : + match(unwrap-token(x)) : + (x:Symbol) : x + (x) : FPE(form, "Expected an identifier here. Got ~ instead." << [x]) + + ;Parses next form if integer literal + int = (?x) when unwrap-token(x) typeof Int : + unwrap-token(x) + + ;Parses next form if symbol + sym = (?x) when unwrap-token(x) typeof Symbol : + unwrap-token(x) + + ;Error Handling Productions defrule : - symbol = (?x) when ut(x) typeof Symbol : ut(x) - int = (?x) when ut(x) typeof Int : ut(x) - + ;Error if not an identifier + id! = (?x:#id) : x + id! != () : FPE(form, "Expected an identifier here.") + + ;Error if not a colon + :! = (:) : (`:) + :! != () : FPE(form, "Expected a colon here.") + + ;Error if not 'of' keyword + of! = (of) : `of + of! != () : FPE(form, "Expected the 'of' keyword here.") + + ;Error if not a = + =! = (=) : `= + =! != () : FPE(form, "Expected a '=' here.") + + ;Error if not a single integer + int$ = (?i:#int ?rest ...) when empty?(rest) : i + int$ != () : FPE(form, "Expected a single integer literal here.") + + ;Error if not a single width + width$ = (?w:#width ?rest ...) when empty?(rest) : w + width$ != () : FPE(form, "Expected a single width specifier here.") + + ;Error if not a type + type! = (?t:#type) : t + type! != () : FPE(form, "Expected a type here.") + + ;Error if not a vec type + vectype! = (?t:#type!) : + FPE(form, "Expected a vector type here.") when t not-typeof VectorType + t + + ;Error if not an expression + exp! = (?e:#exp) : e + exp! != () : FPE(form, "Expected an expression here.") + + ;Error if not a single expression + exp$ = (?e:#exp ?rest ...) when empty?(rest) : e + exp$ != () : FPE(form, "Expected a single expression here.") + + ;Error if not a stmt + stmt! = (?s:#stmt) : s + stmt! != () : FPE(form, "Expected a statement here.") + + ;Error if not a reference expression + ref! = (?e:#exp!) : + FPE(form, "Expected a reference expression here.") when e not-typeof Ref + e + + ;Main Circuit Production defrule circuit : - circuit = (circuit ?name:#symbol : (?modules:#module ... ?rest ...)) : + circuit = (circuit ?name:#id! #:! (?ms:#module ... ?rest ...)) : if not empty?(rest) : - throw-error("Expected module here: ~" << [rest]) - Circuit(modules, name) + FPE(rest, "Expected a module declaration here.") + Circuit(ms, name) + circuit != (circuit) : + FPE(form, "Invalid syntax for circuit definition.") + ;Main Module Production defrule module : - module = (module ?name:#symbol : (?ports:#port ... ?body:#comm ... ?rest ...)) : + module = (module ?name:#id! #:! (?ps:#port ... ?cs:#stmt ... ?rest ...)) : + if not empty?(rest) : + FPE(rest, "Expected a statement here.") + Module(name, ps, Begin(cs)) + module != (module) : + FPE(form, "Invalid syntax for module definition.") + + defrule port : + port = (input ?name:#id! #:! ?type:#type!) : Port(name, INPUT, type) + port = (output ?name:#id! #:! ?type:#type!) : Port(name, OUTPUT, type) + + ;Main Type Productions + defrule type : + inttype = (UInt) : UIntType(w) + inttype = (UInt) : UIntType(UnknownWidth()) + inttype = (SInt) : SIntType(w) + inttype = (SInt) : SIntType(UnknownWidth()) + + type = (?t:#typeterm ?ops:#typeop ...) : apply-suffix-ops(t, ops) + typeop = ((@get ?size:#int$)) : (fn (t) : VectorType(t, size)) + + typeterm = (?t:#inttype) : t + typeterm = ({?fs:#field ... ?rest ...}) : if not empty?(rest) : - throw-error("Expected command here: ~" << [rest]) - Module(name, ports, Begin(body)) + FPE(rest, "Expected a bundle field declaration here.") + BundleType(fs) defrule field : - field = (?name:#symbol : ?type:#type) : - Field(ut(name), DEFAULT, type) - field = (flip ?name:#symbol : ?type:#type) : - Field(ut(name), REVERSE, type) + field = (flip ?name:#id! #:! ?type:#type!) : Field(name, REVERSE, type) + field = (?name:#id #:! ?type:#type!) : Field(name, DEFAULT, type) - defrule port : - port = (input ?name:#symbol : ?type:#type) : - Port(ut(name), INPUT, type) - port = (output ?name:#symbol : ?type:#type) : - Port(ut(name), OUTPUT, type) + defrule width : + width = (?x:#int) : IntWidth(x) + width = (?) : UnknownWidth() - defrule type : - type = (?type:#type (@get ?size:#int)) : - VectorType(type, ut(size)) - type = (UInt (@do ?width:#int)) : - UIntType(IntWidth(ut(width))) - type = (UInt) : - UIntType(UnknownWidth()) - type = (SInt (@do ?width:#int)) : - SIntType(IntWidth(ut(width))) - type = (SInt) : - SIntType(UnknownWidth()) - type = ({?fields:#field ...}) : - BundleType(fields) - - defrule comm : - comm = (wire ?name:#symbol : ?type:#type) : - DefWire(ut(name), type) - comm = (reg ?name:#symbol : ?type:#type) : - DefRegister(ut(name), type) - comm = (mem ?name:#symbol : ?type:#type) : - DefMemory(ut(name), type) - comm = (inst ?name:#symbol of ?module:#exp) : - DefInstance(ut(name), module) - comm = (node ?name:#symbol = ?exp:#exp) : - DefNode(ut(name), exp) - comm = (accessor ?name:#symbol = ?source:#exp (@get ?index:#exp)) : - DefAccessor(ut(name), source, index) - comm = ((?body:#comm ...)) : - Begin(body) - comm = (?x:#exp := ?y:#exp) : - Connect(x, y) - comm = (?c:skip) : - EmptyStmt() - comm = (?c:#comm/when) : - c + ;Main Statement Productions + defrule statements : + stmt = (wire ?name:#id! #:! ?t:#type!) : DefWire(name, t) + stmt = (reg ?name:#id! #:! ?t:#type!) : DefRegister(name, t) + stmt = (mem ?name:#id! #:! ?t:#vectype!) : DefMemory(name, t) + stmt = (inst ?name:#id! #of! ?m:#ref!) : DefInstance(name, m) + stmt = (node ?name:#id! #=! ?e:#exp!) : DefNode(name, e) + stmt = (accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(name, s, i) + stmt = (?s:#stmt/when) : s + + stmt = (?x:#exp := ?y:#exp!) : Connect(x, y) + stmt = (on-reset ?x:#exp := ?y:#exp!) : Connect(x, y);TODO + + stmt = ((?s:#stmt ?ss:#stmt ... ?rest ...)) : + if not empty?(rest) : + FPE(rest, "Expected a statement here.") + Begin(List(s, ss)) + stmt = (()) : + Begin(List()) - defrule comm/when : - comm/when = (when ?pred:#exp : ?conseq:#comm else : ?alt:#comm) : + defrule stmt/when : + stmt/when = (when ?pred:#exp! #:! ?conseq:#stmt! else ?alt:#stmt/when) : Conditionally(pred, conseq, alt) - comm/when = (when ?pred:#exp : ?conseq:#comm else ?alt:#comm/when) : + stmt/when = (when ?pred:#exp! #:! ?conseq:#stmt! else #:! ?alt:#stmt!) : Conditionally(pred, conseq, alt) - comm/when = (when ?pred:#exp : ?conseq:#comm) : + stmt/when = (when ?pred:#exp! #:! ?conseq:#stmt!) : Conditionally(pred, conseq, EmptyStmt()) + ;Main Expressions defrule exp : - exp = (?x:#exp . ?f:#int) : - Index(x, ut(f), UnknownType()) - exp = (?x:#exp . ?f:#symbol) : - Subfield(x, ut(f), UnknownType()) - exp = (?x:#exp-form) : - x - - val operators = HashTable(symbol-hash) - operators[`add] = ADD-OP - operators[`add-uu] = ADD-UU-OP - operators[`add-us] = ADD-US-OP - operators[`add-su] = ADD-SU-OP - operators[`add-ss] = ADD-SS-OP - operators[`sub] = SUB-OP - operators[`sub-uu] = SUB-UU-OP - operators[`sub-us] = SUB-US-OP - operators[`sub-su] = SUB-SU-OP - operators[`sub-ss] = SUB-SS-OP - operators[`mul] = MUL-OP - operators[`mul-uu] = MUL-UU-OP - operators[`mul-us] = MUL-US-OP - operators[`mul-su] = MUL-SU-OP - operators[`mul-ss] = MUL-SS-OP - operators[`div] = DIV-OP - operators[`div-uu] = DIV-UU-OP - operators[`div-us] = DIV-US-OP - operators[`div-su] = DIV-SU-OP - operators[`div-ss] = DIV-SS-OP - operators[`mod] = MOD-OP - operators[`mod-uu] = MOD-UU-OP - operators[`mod-us] = MOD-US-OP - operators[`mod-su] = MOD-SU-OP - operators[`mod-ss] = MOD-SS-OP - operators[`quo] = QUO-OP - operators[`quo-uu] = QUO-UU-OP - operators[`quo-us] = QUO-US-OP - operators[`quo-su] = QUO-SU-OP - operators[`quo-ss] = QUO-SS-OP - operators[`rem] = REM-OP - operators[`rem-uu] = REM-UU-OP - operators[`rem-us] = REM-US-OP - operators[`rem-su] = REM-SU-OP - operators[`rem-ss] = REM-SS-OP - operators[`add-wrap] = ADD-WRAP-OP - operators[`add-wrap-uu] = ADD-WRAP-UU-OP - operators[`add-wrap-us] = ADD-WRAP-US-OP - operators[`add-wrap-su] = ADD-WRAP-SU-OP - operators[`add-wrap-ss] = ADD-WRAP-SS-OP - operators[`sub-wrap] = SUB-WRAP-OP - operators[`sub-wrap-uu] = SUB-WRAP-UU-OP - operators[`sub-wrap-us] = SUB-WRAP-US-OP - operators[`sub-wrap-su] = SUB-WRAP-SU-OP - operators[`sub-wrap-ss] = SUB-WRAP-SS-OP - operators[`lt] = LESS-OP - operators[`lt-uu] = LESS-UU-OP - operators[`lt-us] = LESS-US-OP - operators[`lt-su] = LESS-SU-OP - operators[`lt-ss] = LESS-SS-OP - operators[`leq] = LESS-EQ-OP - operators[`leq-uu] = LESS-EQ-UU-OP - operators[`leq-us] = LESS-EQ-US-OP - operators[`leq-su] = LESS-EQ-SU-OP - operators[`leq-ss] = LESS-EQ-SS-OP - operators[`gt] = GREATER-OP - operators[`gt-uu] = GREATER-UU-OP - operators[`gt-us] = GREATER-US-OP - operators[`gt-su] = GREATER-SU-OP - operators[`gt-ss] = GREATER-SS-OP - operators[`geq] = GREATER-EQ-OP - operators[`geq-uu] = GREATER-EQ-UU-OP - operators[`geq-us] = GREATER-EQ-US-OP - operators[`geq-su] = GREATER-EQ-SU-OP - operators[`geq-ss] = GREATER-EQ-SS-OP - operators[`eq] = EQUAL-OP - operators[`eq-uu] = EQUAL-UU-OP - operators[`eq-ss] = EQUAL-SS-OP - operators[`neq] = NEQUAL-OP - operators[`neq-uu] = NEQUAL-UU-OP - operators[`neq-ss] = NEQUAL-SS-OP - operators[`mux] = MUX-OP - operators[`mux-uu] = MUX-UU-OP - operators[`mux-ss] = MUX-SS-OP - operators[`pad] = PAD-OP - operators[`pad-u] = PAD-U-OP - operators[`pad-s] = PAD-S-OP - operators[`as-UInt] = AS-UINT-OP - operators[`as-UInt-u] = AS-UINT-U-OP - operators[`as-UInt-s] = AS-UINT-S-OP - operators[`as-SInt] = AS-SINT-OP - operators[`as-SInt-u] = AS-SINT-U-OP - operators[`as-SInt-s] = AS-SINT-S-OP - operators[`shl] = SHIFT-LEFT-OP - operators[`shl-u] = SHIFT-LEFT-U-OP - operators[`shl-s] = SHIFT-LEFT-S-OP - operators[`shr] = SHIFT-RIGHT-OP - operators[`shr-u] = SHIFT-RIGHT-U-OP - operators[`shr-s] = SHIFT-RIGHT-S-OP - operators[`convert] = CONVERT-OP - operators[`convert-u] = CONVERT-U-OP - operators[`convert-s] = CONVERT-S-OP - operators[`neg] = NEG-OP - operators[`neg-u] = NEG-U-OP - operators[`neg-s] = NEG-S-OP - operators[`bit-not] = BIT-NOT-OP - operators[`bit-and] = BIT-AND-OP - operators[`bit-or] = BIT-OR-OP - operators[`bit-xor] = BIT-XOR-OP - operators[`cat] = CONCAT-OP - operators[`bit] = BIT-SELECT-OP - operators[`bits] = BITS-SELECT-OP - operators[`bit-and-reduce] = BIT-AND-REDUCE-OP - operators[`bit-or-reduce] = BIT-OR-REDUCE-OP - operators[`bit-xor-reduce] = BIT-XOR-REDUCE-OP + ;Suffix Operators + exp = (?x:#expterm ?ops:#expop ...) : apply-suffix-ops(x, ops) + expop = ((@get ?f:#int)) : (fn (x) : Index(x, f, UnknownType())) + expop = (. ?f:#id!) : (fn (x) : Subfield(x, f, UnknownType())) + + ;Prefix Operators + expterm = (?t:#inttype(?v:#int$)) : + match(t) : + (t:UIntType) : UIntValue(v, width(t)) + (t:SIntType) : SIntValue(v, width(t)) - defrule width : - width = (?) : - UnknownWidth() - width = (?width:#int) : - IntWidth(ut(width)) - - defrule exp-form : - exp-form = (UInt (@do ?value:#int ?width:#width)) : - UIntValue(ut(value), width) - exp-form = (UInt (@do ?value:#int)) : - UIntValue(ut(value), UnknownWidth()) - exp-form = (SInt (@do ?value:#int ?width:#width)) : - SIntValue(ut(value), width) - exp-form = (SInt (@do ?value:#int)) : - SIntValue(ut(value), UnknownWidth()) - exp-form = (WritePort (@do ?mem:#exp ?index:#exp ?enable:#exp)) : - WritePort(mem, index, UnknownType(), enable) - exp-form = (ReadPort (@do ?mem:#exp ?index:#exp ?enable:#exp)) : - ReadPort(mem, index, UnknownType(), enable) - exp-form = (Register (@do ?value:#exp ?enable:#exp)) : - Register(UnknownType(),value,enable) - exp-form = (Pad (@do ?value:#exp ?width:#width)) : - Pad(value,width,UnknownType()) - exp-form = (?op:#symbol (@do ?es:#exp ... ?ints:#int ...)) : - println("Op-symbol is:~" % [op]) - match(get?(operators, ut(op), false)) : - (op:PrimOp) : - ;println("Op is:~ ~ ~" % [op,op == ADD-OP, op == ADD-UU-OP]) - DoPrim(op, es, map(ut, ints), UnknownType()) - (f:False) : - throw-error $ string-join $ [ - "Invalid operator: " op] - exp-form = (?x:#symbol) : - Ref(ut(x), UnknownType()) + expterm = (WritePort(?m:#exp, ?i:#exp, ?e:#exp)) : WritePort(m, i, UnknownType(), e) + expterm != (WritePort) : FPE(form, "Invalid syntax for WritePort expression.") + + expterm = (ReadPort(?m:#exp, ?i:#exp, ?e:#exp)) : ReadPort(m, i, UnknownType(), e) + expterm != (ReadPort) : FPE(form, "Invalid syntax for ReadPort expression.") + + expterm = (Register(?v:#exp, ?e:#exp)) : Register(UnknownType(), v, e) + expterm != (Register) : FPE(form, "Invalid syntax for Register expression.") + + expterm = (Pad(?e:#exp, ?w:#width$)) : Pad(e,w,UnknownType()) + expterm != (Pad) : FPE(form, "Invalid syntax for Pad expression.") + + expterm = (?op:#sym(?es:#exp ... ?ints:#int ... ?rest ...)) : + if not empty?(rest) : + FPE(rest, "Illegal operands to primitive operator.") + match(primop(op)) : + (p:PrimOp) : DoPrim(p, es, ints, UnknownType()) + (p:False) : FPE(form, "Unrecognized primitive operator '~'." << [op]) + expterm = (?op:#sym) : + Ref(op, UnknownType()) public defn parse-firrtl (forms:List) : with-syntax(firrtl) : match-syntax(forms) : - (?c:#circuit) : - c + (?c:#circuit) : c + (_ ...) : FPE(form, "Invalid firrtl circuit.") + +public defn parse-firrtl-file (filename:String) : + parse-firrtl(lex-file(filename)) diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza index 86fe56d1..283fe9ea 100644 --- a/src/main/stanza/ir-utils.stanza +++ b/src/main/stanza/ir-utils.stanza @@ -140,7 +140,7 @@ defmethod print (o:OutputStream, e:Expression) : match(e) : (e:Ref) : print(o, name(e)) (e:Subfield) : print-all(o, [exp(e) "." name(e)]) - (e:Index) : print-all(o, [exp(e) "." value(e)]) + (e:Index) : print-all(o, [exp(e) "[" value(e) "]"]) (e:UIntValue) : print-all(o, ["UInt(" value(e) ")"]) (e:SIntValue) : print-all(o, ["SInt(" value(e) ")"]) (e:DoPrim) : @@ -179,6 +179,8 @@ defmethod print (o:OutputStream, c:Stmt) : do(print{o,_}, join(body(c), "\n")) (c:Connect) : print-all(o, [loc(c) " := " exp(c)]) + (c:OnReset) : + print-all(o, ["on-reset " reg(c) " := " exp(c)]) (c:EmptyStmt) : print(o, "skip") print-debug(o,c) @@ -190,11 +192,11 @@ defmethod print (o:OutputStream, t:Type) : (t:UIntType) : match(width(t)) : (w:UnknownWidth) : print-all(o, ["UInt"]) - (w) : print-all(o, ["UInt(" width(t) ")"]) + (w) : print-all(o, ["UInt<" width(t) ">"]) (t:SIntType) : match(width(t)) : (w:UnknownWidth) : print-all(o, ["SInt"]) - (w) : print-all(o, ["SInt(" width(t) ")"]) + (w) : print-all(o, ["SInt<" width(t) ">"]) (t:BundleType) : print(o, "{") print-all(o, join(fields(t), ", ")) @@ -258,6 +260,7 @@ defmethod map (f: Expression -> Expression, c:Stmt) -> Stmt : (c:DefInstance) : DefInstance(name(c), f(module(c))) (c:Conditionally) : Conditionally(f(pred(c)), conseq(c), alt(c)) (c:Connect) : Connect(f(loc(c)), f(exp(c))) + (c:OnReset) : OnReset(f(reg(c)),f(exp(c))) (c) : c public defmulti map (f: Stmt -> Stmt, c:?T&Stmt) -> T diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 50d2831a..497f294d 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -228,7 +228,7 @@ defmethod print (o:OutputStream, e:WSubfield) : print-debug(o,e as ?) defmethod print (o:OutputStream, e:WIndex) : - print-all(o,[exp(e) "." value(e)]) + print-all(o,[exp(e) "[" value(e) "]"]) print-debug(o,e as ?) defmethod print (o:OutputStream, s:WDefAccessor) : diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir index 96bf8d54..984b6acd 100644 --- a/test/passes/expand-accessors/accessor-mem.fir +++ b/test/passes/expand-accessors/accessor-mem.fir @@ -3,17 +3,17 @@ ;CHECK: Expand Accessors circuit top : module top : - mem m : UInt(32)[10][10][10] + mem m : UInt<32>[10][10][10] wire i : UInt accessor a = m[i] ;CHECK: accessor a = m[i] - accessor b = a[i] ;CHECK: b := (a.0 a.1 a.2 a.3 a.4 a.5 a.6 a.7 a.8 a.9)[i] - accessor c = b[i] ;CHECK: c := (b.0 b.1 b.2 b.3 b.4 b.5 b.6 b.7 b.8 b.9)[i] + accessor b = a[i] ;CHECK: b := (a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9])[i] + accessor c = b[i] ;CHECK: c := (b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9])[i] wire j : UInt j := c accessor x = m[i] ;CHECK: accessor x = m[i] - accessor y = x[i] ;CHECK: (x.0 x.1 x.2 x.3 x.4 x.5 x.6 x.7 x.8 x.9)[i] := y - accessor z = y[i] ;CHECK: (y.0 y.1 y.2 y.3 y.4 y.5 y.6 y.7 y.8 y.9)[i] := z + accessor y = x[i] ;CHECK: (x[0] x[1] x[2] x[3] x[4] x[5] x[6] x[7] x[8] x[9])[i] := y + accessor z = y[i] ;CHECK: (y[0] y[1] y[2] y[3] y[4] y[5] y[6] y[7] y[8] y[9])[i] := z z := j ; CHECK: Finished Expand Accessors diff --git a/test/passes/expand-accessors/accessor-vec.fir b/test/passes/expand-accessors/accessor-vec.fir index 2c6bbd5f..6d0b5f93 100644 --- a/test/passes/expand-accessors/accessor-vec.fir +++ b/test/passes/expand-accessors/accessor-vec.fir @@ -3,25 +3,25 @@ ;CHECK: Expand Accessors circuit top : module top : - wire m : UInt(32)[10][10][10] + wire m : UInt<32>[10][10][10] wire i : UInt - accessor a = m[i] ;CHECK: a := (m.0 m.1 m.2 m.3 m.4 m.5 m.6 m.7 m.8 m.9)[i] - accessor b = a[i] ;CHECK: b := (a.0 a.1 a.2 a.3 a.4 a.5 a.6 a.7 a.8 a.9)[i] - accessor c = b[i] ;CHECK: c := (b.0 b.1 b.2 b.3 b.4 b.5 b.6 b.7 b.8 b.9)[i] + accessor a = m[i] ;CHECK: a := (m[0] m[1] m[2] m[3] m[4] m[5] m[6] m[7] m[8] m[9])[i] + accessor b = a[i] ;CHECK: b := (a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9])[i] + accessor c = b[i] ;CHECK: c := (b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9])[i] wire j : UInt j := c - accessor x = m[i] ;CHECK: (m.0 m.1 m.2 m.3 m.4 m.5 m.6 m.7 m.8 m.9)[i] := x - accessor y = x[i] ;CHECK: (x.0 x.1 x.2 x.3 x.4 x.5 x.6 x.7 x.8 x.9)[i] := y - accessor z = y[i] ;CHECK: (y.0 y.1 y.2 y.3 y.4 y.5 y.6 y.7 y.8 y.9)[i] := z + accessor x = m[i] ;CHECK: (m[0] m[1] m[2] m[3] m[4] m[5] m[6] m[7] m[8] m[9])[i] := x + accessor y = x[i] ;CHECK: (x[0] x[1] x[2] x[3] x[4] x[5] x[6] x[7] x[8] x[9])[i] := y + accessor z = y[i] ;CHECK: (y[0] y[1] y[2] y[3] y[4] y[5] y[6] y[7] y[8] y[9])[i] := z z := j - wire p : {n : UInt(32)[10]} - accessor q = p.n[i] ;CHECK: (p.n.0 p.n.1 p.n.2 p.n.3 p.n.4 p.n.5 p.n.6 p.n.7 p.n.8 p.n.9)[i] := q + wire p : {n : UInt<32>[10]} + accessor q = p.n[i] ;CHECK: (p.n[0] p.n[1] p.n[2] p.n[3] p.n[4] p.n[5] p.n[6] p.n[7] p.n[8] p.n[9])[i] := q q := j - wire r : {m : UInt(32)}[10] - accessor s = r[i] ;CHECK: s := (r.0 r.1 r.2 r.3 r.4 r.5 r.6 r.7 r.8 r.9)[i] + wire r : {m : UInt<32>}[10] + accessor s = r[i] ;CHECK: s := (r[0] r[1] r[2] r[3] r[4] r[5] r[6] r[7] r[8] r[9])[i] j := s.m ; CHECK: Finished Expand Accessors diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir index 4e6f3456..35b45b6c 100644 --- a/test/passes/expand-connect-indexed/bundle-vecs.fir +++ b/test/passes/expand-connect-indexed/bundle-vecs.fir @@ -6,15 +6,15 @@ circuit top : wire i : UInt wire j : UInt - wire a : { x : UInt(32), flip y : UInt(32) }[2] - ; CHECK: wire a$0$x : UInt(32) - ; CHECK: wire a$0$y : UInt(32) - ; CHECK: wire a$1$x : UInt(32) - ; CHECK: wire a$1$y : UInt(32) + wire a : { x : UInt<32>, flip y : UInt<32> }[2] + ; CHECK: wire a$0$x : UInt<32> + ; CHECK: wire a$0$y : UInt<32> + ; CHECK: wire a$1$x : UInt<32> + ; CHECK: wire a$1$y : UInt<32> accessor b = a[i] - ; CHECK: wire b$x : UInt(32) - ; CHECK: wire b$y : UInt(32) + ; CHECK: wire b$x : UInt<32> + ; CHECK: wire b$y : UInt<32> ; CHECK: b$x := a$0$x ; CHECK: when eq-uu(i, UInt(1)) : ; CHECK: b$x := a$1$x diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir index 45ae938b..de513641 100644 --- a/test/passes/expand-whens/one-when.fir +++ b/test/passes/expand-whens/one-when.fir @@ -3,15 +3,15 @@ ; CHECK: Expand Whens circuit top : module top : - mem m : UInt(1)[2] - wire i : UInt(1) - wire p : UInt(1) - wire j : UInt(1) - reg r : UInt(1) + mem m : UInt<1>[2] + wire i : UInt<1> + wire p : UInt<1> + wire j : UInt<1> + reg r : UInt<1> p := j when p : - r.init := i + on-reset r := i accessor a = m[i] i := a accessor b = m[i] @@ -26,7 +26,7 @@ circuit top : p := i when e : p := p - r.init := p + on-reset r := p r := p diff --git a/test/passes/expand-whens/partial-init.fir b/test/passes/expand-whens/partial-init.fir index 653dfb2d..e5788c11 100644 --- a/test/passes/expand-whens/partial-init.fir +++ b/test/passes/expand-whens/partial-init.fir @@ -3,7 +3,7 @@ ; CHECK: Expand Whens circuit top : module top : - reg r : UInt(1)[10] - r.init.3 := UInt(0) + reg r : UInt<1>[10] + on-reset r[3] := UInt(0) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir index c2814038..d3adf5f2 100644 --- a/test/passes/expand-whens/two-when.fir +++ b/test/passes/expand-whens/two-when.fir @@ -3,13 +3,13 @@ ; CHECK: Expand Whens circuit top : module top : - mem m :{ x : UInt(1), y : UInt(1) }[2] - wire i : UInt(1) - wire p : UInt(1) - wire q : { x : UInt(1), y : UInt(1) } + mem m :{ x : UInt<1>, y : UInt<1> }[2] + wire i : UInt<1> + wire p : UInt<1> + wire q : { x : UInt<1>, y : UInt<1> } when p : - wire p2 : UInt(1) - reg r5 : UInt(1) + wire p2 : UInt<1> + reg r5 : UInt<1> when p2 : accessor a = m[i] q := a @@ -21,7 +21,7 @@ circuit top : accessor d = m[i] d := q else : - wire p3 : UInt(1) + wire p3 : UInt<1> when p3 : accessor w = m[i] q := w diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir index c3d4896a..cde9be6d 100644 --- a/test/passes/infer-types/bundle.fir +++ b/test/passes/infer-types/bundle.fir @@ -4,10 +4,9 @@ circuit top : module subtracter : wire z : { x : UInt, flip y: SInt} - node x = z.x ;CHECK: node x = z@, flip y : SInt@}>.x@ - node y = z.y ;CHECK: node y = z@, flip y : SInt@}>.y@ - - wire a : UInt(3)[10] ;CHECK: wire a : UInt(3)[10]@@> - node b = a.2 ;CHECK: node b = a@>.2@ - accessor c = a[UInt(3)] ;CHECK: accessor c = a@>[UInt(3)] + node x = z.x ;CHECK: node x = z@, flip y : SInt@}>.x@ + node y = z.y ;CHECK: node y = z@, flip y : SInt@}>.y@ + wire a : UInt<3>[10] ;CHECK: wire a : UInt<3>[10]@@[10]@> + node b = a[2] ;CHECK: node b = a@[10]@>[2]@ + accessor c = a[UInt(3)] ;CHECK: accessor c = a@[10]@>[UInt(3)] ; CHECK: Finished Infer Types diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir index 300101ad..0b6b19fa 100644 --- a/test/passes/infer-types/gcd.fir +++ b/test/passes/infer-types/gcd.fir @@ -9,27 +9,27 @@ circuit top : z := sub-wrap(x, y) ;CHECK: z@ := sub-wrap-uu(x@, y@)@ module gcd : - input a : UInt(16) - input b : UInt(16) - input e : UInt(1) - output z : UInt(16) - output v : UInt(1) + input a : UInt<16> + input b : UInt<16> + input e : UInt<1> + output z : UInt<16> + output v : UInt<1> reg x : UInt reg y : UInt ; CHECK: reg x : UInt - x.init := UInt(0) - y.init := UInt(42) + on-reset x := UInt(0) + on-reset y := UInt(42) when gt(x, y) : ;CHECK: when gt-uu(x@, y@)@ : inst s of subtracter - ;CHECK: inst s of subtracter@, y : UInt@, flip z : UInt@, reset : UInt(1)@}> + ;CHECK: inst s of subtracter@, y : UInt@, flip z : UInt@, reset : UInt<1>@}> s.x := x s.y := y x := s.z - ;CHECK: s@, y : UInt@, flip z : UInt@, reset : UInt(1)@}>.reset@ := reset@ - ;CHECK: s@, y : UInt@, flip z : UInt@, reset : UInt(1)@}>.x@ := x@ - ;CHECK: s@, y : UInt@, flip z : UInt@, reset : UInt(1)@}>.y@ := y@ - ;CHECK: x@ := s@, y : UInt@, flip z : UInt@, reset : UInt(1)@}>.z@ + ;CHECK: s@, y : UInt@, flip z : UInt@, reset : UInt<1>@}>.reset@ := reset@ + ;CHECK: s@, y : UInt@, flip z : UInt@, reset : UInt<1>@}>.x@ := x@ + ;CHECK: s@, y : UInt@, flip z : UInt@, reset : UInt<1>@}>.y@ := y@ + ;CHECK: x@ := s@, y : UInt@, flip z : UInt@, reset : UInt<1>@}>.z@ else : inst s2 of subtracter s2.x := x @@ -42,8 +42,8 @@ circuit top : ;CHECK: v@ := eq-uu(v@, UInt(0))@ z := x module top : - input a : UInt(16) - input b : UInt(16) + input a : UInt<16> + input b : UInt<16> output z : UInt inst i of gcd i.a := a diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir index 35634a6f..a17d8f67 100644 --- a/test/passes/infer-types/primops.fir +++ b/test/passes/infer-types/primops.fir @@ -3,11 +3,11 @@ ;CHECK: Infer Types circuit top : module top : - wire a : UInt(16) - wire b : UInt(8) - wire c : SInt(16) - wire d : SInt(8) - wire e : UInt(1) + wire a : UInt<16> + wire b : UInt<8> + wire c : SInt<16> + wire d : SInt<8> + wire e : UInt<1> node vadd = add(a, c) ;CHECK: node vadd = add-us(a@, c@)@ node wadd-uu = add-uu(a, b) ;CHECK: node wadd-uu = add-uu(a@, b@)@ diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir index 864852fb..0e9b5fed 100644 --- a/test/passes/infer-widths/gcd.fir +++ b/test/passes/infer-widths/gcd.fir @@ -8,15 +8,15 @@ circuit top : output q : UInt q := sub-wrap-uu(x, y) module gcd : - input a : UInt(16) - input b : UInt(16) - input e : UInt(1) - output z : UInt(16) - output v : UInt(1) + input a : UInt<16> + input b : UInt<16> + input e : UInt<1> + output z : UInt<16> + output v : UInt<1> reg x : UInt reg y : UInt - x.init := UInt(0) - y.init := UInt(42) + on-reset x := UInt(0) + on-reset y := UInt(42) when gt-uu(x, y) : inst s of subtracter s.x := x @@ -33,8 +33,8 @@ circuit top : v := eq-uu(v, UInt(0)) z := x module top : - input a : UInt(16) - input b : UInt(16) + input a : UInt<16> + input b : UInt<16> output z : UInt inst i of gcd i.a := a diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir index 50eb5452..0d4dc981 100644 --- a/test/passes/infer-widths/simple.fir +++ b/test/passes/infer-widths/simple.fir @@ -3,12 +3,12 @@ ;CHECK: Infer Widths circuit top : module top : - wire e : UInt(30) + wire e : UInt<30> reg y : UInt y := e - wire a : UInt(20) - wire b : UInt(10) + wire a : UInt<20> + wire b : UInt<10> wire c : UInt wire z : UInt diff --git a/test/passes/inline/gcd.fir b/test/passes/inline/gcd.fir index 8cb856f2..68577431 100644 --- a/test/passes/inline/gcd.fir +++ b/test/passes/inline/gcd.fir @@ -8,15 +8,15 @@ circuit top : output q : UInt q := sub-wrap-uu(x, y) module gcd : - input a : UInt(16) - input b : UInt(16) - input e : UInt(1) - output z : UInt(16) - output v : UInt(1) + input a : UInt<16> + input b : UInt<16> + input e : UInt<1> + output z : UInt<16> + output v : UInt<1> reg x : UInt reg y : UInt - x.init := UInt(0) - y.init := UInt(42) + on-reset x := UInt(0) + on-reset y := UInt(42) when gt-uu(x, y) : inst s of subtracter s.x := x @@ -33,8 +33,8 @@ circuit top : v := eq-uu(v, UInt(0)) z := x module top : - input a : UInt(16) - input b : UInt(16) + input a : UInt<16> + input b : UInt<16> output z : UInt inst i of gcd i.a := a diff --git a/test/passes/jacktest/SIntOps.fir b/test/passes/jacktest/SIntOps.fir index 45ea68f2..406a09de 100644 --- a/test/passes/jacktest/SIntOps.fir +++ b/test/passes/jacktest/SIntOps.fir @@ -3,22 +3,22 @@ circuit SIntOps : module SIntOps : - input b : SInt(16) - input a : SInt(16) - output addout : SInt(16) - output subout : SInt(16) - output timesout : SInt(16) - output divout : SInt(16) - output modout : SInt(16) - output lshiftout : SInt(16) - output rshiftout : SInt(16) - output lessout : UInt(1) - output greatout : UInt(1) - output eqout : UInt(1) - output noteqout : UInt(1) - output lesseqout : UInt(1) - output greateqout : UInt(1) - output negout : SInt(16) + input b : SInt<16> + input a : SInt<16> + output addout : SInt<16> + output subout : SInt<16> + output timesout : SInt<16> + output divout : SInt<16> + output modout : SInt<16> + output lshiftout : SInt<16> + output rshiftout : SInt<16> + output lessout : UInt<1> + output greatout : UInt<1> + output eqout : UInt<1> + output noteqout : UInt<1> + output lesseqout : UInt<1> + output greateqout : UInt<1> + output negout : SInt<16> node T_35 = add-wrap(a, b) addout := T_35 diff --git a/test/passes/jacktest/UIntOps.fir b/test/passes/jacktest/UIntOps.fir index bb3e6293..e402f22e 100644 --- a/test/passes/jacktest/UIntOps.fir +++ b/test/passes/jacktest/UIntOps.fir @@ -3,21 +3,21 @@ circuit UIntOps : module UIntOps : - input b : UInt(16) - input a : UInt(16) - output addout : UInt(16) - output subout : UInt(16) - output timesout : UInt(16) - output divout : UInt(16) - output modout : UInt(16) - output lshiftout : UInt(16) - output rshiftout : UInt(16) - output lessout : UInt(1) - output greatout : UInt(1) - output eqout : UInt(1) - output noteqout : UInt(1) - output lesseqout : UInt(1) - output greateqout : UInt(1) + input b : UInt<16> + input a : UInt<16> + output addout : UInt<16> + output subout : UInt<16> + output timesout : UInt<16> + output divout : UInt<16> + output modout : UInt<16> + output lshiftout : UInt<16> + output rshiftout : UInt<16> + output lessout : UInt<1> + output greatout : UInt<1> + output eqout : UInt<1> + output noteqout : UInt<1> + output lesseqout : UInt<1> + output greateqout : UInt<1> node T_31 = add-wrap(a, b) addout := T_31 diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir index 2d97ee8d..4be5bdf9 100644 --- a/test/passes/jacktest/gcd.fir +++ b/test/passes/jacktest/gcd.fir @@ -3,14 +3,14 @@ ;CHECK: To Flo circuit GCD : module GCD : - input b : UInt(16) - input a : UInt(16) - input e : UInt(1) - output z : UInt(16) - output v : UInt(1) + input b : UInt<16> + input a : UInt<16> + input e : UInt<1> + output z : UInt<16> + output v : UInt<1> - reg x : UInt(16) - reg y : UInt(16) + reg x : UInt<16> + reg y : UInt<16> node T_17 = gt(x, y) when T_17 : node T_18 = sub-wrap(x, y) @@ -22,7 +22,7 @@ circuit GCD : x := a y := b z := x - node T_20 = UInt(0, 1) + node T_20 = UInt<1>(0) node T_21 = eq(y, Pad(T_20,?)) v := T_21 diff --git a/test/passes/jacktest/gcd2.fir b/test/passes/jacktest/gcd2.fir index e6700122..e0220ca1 100644 --- a/test/passes/jacktest/gcd2.fir +++ b/test/passes/jacktest/gcd2.fir @@ -2,14 +2,14 @@ ;CHECK: To Flo circuit GCD : module GCD : - input b : UInt(16) - input a : UInt(16) - input e : UInt(1) - output z : UInt(16) - output v : UInt(1) + input b : UInt<16> + input a : UInt<16> + input e : UInt<1> + output z : UInt<16> + output v : UInt<1> - reg x : UInt(16) - reg y : UInt(16) + reg x : UInt<16> + reg y : UInt<16> node T_17 = gt(Pad(x,?), Pad(y,?)) when T_17 : node T_18 = sub-wrap(Pad(x,?), Pad(y,?)) @@ -21,6 +21,6 @@ circuit GCD : x := a y := b z := x - node T_20 = UInt(0, 1) + node T_20 = UInt<1>(0) node T_21 = eq(Pad(y,?), Pad(T_20,?)) v := T_21 diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir index 0a13e5c0..bb1512d5 100644 --- a/test/passes/jacktest/risc.fir +++ b/test/passes/jacktest/risc.fir @@ -3,47 +3,47 @@ circuit Risc : module Risc : - output out : UInt(32) - output valid : UInt(1) - input boot : UInt(1) - input isWr : UInt(1) - input wrAddr : UInt(8) - input wrData : UInt(32) + output out : UInt<32> + output valid : UInt<1> + input boot : UInt<1> + input isWr : UInt<1> + input wrAddr : UInt<8> + input wrData : UInt<32> - mem file : UInt(32)[256] - mem code : UInt(32)[256] - node T_51 = UInt(0, 8) - reg pc : UInt(8) - pc.init := T_51 - node add_op = UInt(0, 1) - node imm_op = UInt(1, 1) + mem file : UInt<32>[256] + mem code : UInt<32>[256] + node T_51 = UInt<8>(0) + reg pc : UInt<8> + on-reset pc := T_51 + node add_op = UInt<1>(0) + node imm_op = UInt<1>(1) accessor inst = code[pc] node op = bits(inst, 31, 24) node rci = bits(inst, 23, 16) node rai = bits(inst, 15, 8) node rbi = bits(inst, 7, 0) - node T_52 = UInt(0, 1) + node T_52 = UInt<1>(0) node T_53 = eq(rai, T_52) - node T_54 = UInt(0, 1) + node T_54 = UInt<1>(0) accessor T_55 = file[rai] node ra = mux(T_53, T_54, T_55) - node T_56 = UInt(0, 1) + node T_56 = UInt<1>(0) node T_57 = eq(rbi, T_56) - node T_58 = UInt(0, 1) + node T_58 = UInt<1>(0) accessor T_59 = file[rbi] node rb = mux(T_57, T_58, T_59) - wire rc : UInt(32) - node T_60 = UInt(0, 1) + wire rc : UInt<32> + node T_60 = UInt<1>(0) valid := T_60 - node T_61 = UInt(0, 1) + node T_61 = UInt<1>(0) out := T_61 - node T_62 = UInt(0, 1) + node T_62 = UInt<1>(0) rc := T_62 when isWr : accessor T_63 = code[wrAddr] T_63 := wrData else : when boot : - node T_64 = UInt(0, 1) + node T_64 = UInt<1>(0) pc := T_64 else : node T_65 = eq(add_op, op) @@ -56,15 +56,15 @@ circuit Risc : node T_69 = bit-or(T_68, rbi) rc := T_69 out := rc - node T_70 = UInt(255, 8) + node T_70 = UInt<8>(255) node T_71 = eq(rci, T_70) when T_71 : - node T_72 = UInt(1, 1) + node T_72 = UInt<1>(1) valid := T_72 else : accessor T_73 = file[rci] T_73 := rc - node T_74 = UInt(1, 1) + node T_74 = UInt<1>(1) node T_75 = add-wrap(pc, T_74) pc := T_75 ; CHECK: Finished Expand Whens diff --git a/test/passes/jacktest/testlower.fir b/test/passes/jacktest/testlower.fir index c338d094..7b096ff3 100644 --- a/test/passes/jacktest/testlower.fir +++ b/test/passes/jacktest/testlower.fir @@ -4,17 +4,17 @@ circuit BundleWire : module BundleWire : - input in : { y : UInt(32), x : UInt(32) } - output outs : { y : UInt(32), x : UInt(32) }[4] + input in : { y : UInt<32>, x : UInt<32> } + output outs : { y : UInt<32>, x : UInt<32> }[4] - wire coords : { y : UInt(32), x : UInt(32) }[4] - coords.0 := in - outs.0 := coords.0 - coords.1 := in - outs.1 := coords.1 - coords.2 := in - outs.2 := coords.2 - coords.3 := in - outs.3 := coords.3 + wire coords : { y : UInt<32>, x : UInt<32> }[4] + coords[0] := in + outs[0] := coords[0] + coords[1] := in + outs[1] := coords[1] + coords[2] := in + outs[2] := coords[2] + coords[3] := in + outs[3] := coords[3] ; CHECK: Finished Expand Whens diff --git a/test/passes/jacktest/vecshift.fir b/test/passes/jacktest/vecshift.fir index 4d2563af..9914ea04 100644 --- a/test/passes/jacktest/vecshift.fir +++ b/test/passes/jacktest/vecshift.fir @@ -4,21 +4,21 @@ circuit VecShiftRegister : module VecShiftRegister : - input load : UInt(1) - output out : UInt(4) - input shift : UInt(1) - input ins : UInt(4)[4] + input load : UInt<1> + output out : UInt<4> + input shift : UInt<1> + input ins : UInt<4>[4] - reg delays : UInt(4)[4] + reg delays : UInt<4>[4] when load : - delays.0 := ins.0 - delays.1 := ins.1 - delays.2 := ins.2 - delays.3 := ins.3 + delays[0] := ins[0] + delays[1] := ins[1] + delays[2] := ins[2] + delays[3] := ins[3] else : when shift : - delays.0 := ins.0 - delays.1 := delays.0 - delays.2 := delays.1 - delays.3 := delays.2 - out := delays.3 + delays[0] := ins[0] + delays[1] := delays[0] + delays[2] := delays[1] + delays[3] := delays[2] + out := delays[3] ; CHECK: Finished Expand Whens diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir index 0ebbb13d..2b73a8e9 100644 --- a/test/passes/lower-to-ground/accessor.fir +++ b/test/passes/lower-to-ground/accessor.fir @@ -3,26 +3,26 @@ ; CHECK: Lower To Ground circuit top : module m : - wire i : UInt(2) - wire j : UInt(32) + wire i : UInt<2> + wire j : UInt<32> - wire a : UInt(32)[4] - ; CHECK: wire a$0 : UInt(32) - ; CHECK: wire a$1 : UInt(32) - ; CHECK: wire a$2 : UInt(32) - ; CHECK: wire a$3 : UInt(32) + wire a : UInt<32>[4] + ; CHECK: wire a$0 : UInt<32> + ; CHECK: wire a$1 : UInt<32> + ; CHECK: wire a$2 : UInt<32> + ; CHECK: wire a$3 : UInt<32> accessor b = a[i] - ; CHECK: wire b : UInt(32) + ; CHECK: wire b : UInt<32> ; CHECK: b := (a$0 a$1 a$2 a$3)[i] j := b accessor c = a[i] - ; CHECK: wire c : UInt(32) + ; CHECK: wire c : UInt<32> ; CHECK: (a$0 a$1 a$2 a$3)[i] := c c := j - mem p : UInt(32)[4] + mem p : UInt<32>[4] accessor t = p[i] ; CHECK: accessor t = p[i] j := t diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir index 77de74db..a4ba1eab 100644 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ b/test/passes/lower-to-ground/bundle-vecs.fir @@ -6,22 +6,22 @@ circuit top : wire i : UInt wire j : UInt - wire a : { x : UInt(32), flip y : UInt(32) }[2] - ; CHECK: wire a$0$x : UInt(32) - ; CHECK: wire a$0$y : UInt(32) - ; CHECK: wire a$1$x : UInt(32) - ; CHECK: wire a$1$y : UInt(32) + wire a : { x : UInt<32>, flip y : UInt<32> }[2] + ; CHECK: wire a$0$x : UInt<32> + ; CHECK: wire a$0$y : UInt<32> + ; CHECK: wire a$1$x : UInt<32> + ; CHECK: wire a$1$y : UInt<32> accessor b = a[i] - ; CHECK: wire b$x : UInt(32) - ; CHECK: wire b$y : UInt(32) + ; CHECK: wire b$x : UInt<32> + ; CHECK: wire b$y : UInt<32> ; CHECK: b$x := (a$0$x a$1$x)[i] ; CHECK: (a$0$y a$1$y)[i] := b$y j := b accessor c = a[i] - ; CHECK: wire c$x : UInt(32) - ; CHECK: wire c$y : UInt(32) + ; CHECK: wire c$x : UInt<32> + ; CHECK: wire c$y : UInt<32> ; CHECK: (a$0$x a$1$x)[i] := c$x ; CHECK: c$y := (a$0$y a$1$y)[i] c := j diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir index 859ddb47..ca676ba5 100644 --- a/test/passes/lower-to-ground/bundle.fir +++ b/test/passes/lower-to-ground/bundle.fir @@ -21,7 +21,7 @@ circuit top : ;CHECK: output a$y : SInt ;CHECK: output b$x : UInt ;CHECK: input b$y : SInt -;CHECK: input reset : UInt(1) +;CHECK: input reset : UInt<1> ;CHECK: module subtracter : ;CHECK: input c$x$0 : UInt ;CHECK: input c$x$1 : UInt @@ -32,7 +32,7 @@ circuit top : ;CHECK: output c$y$x$1 : UInt ;CHECK: output c$y$x$2 : UInt ;CHECK: input c$y$y : SInt -;CHECK: input reset : UInt(1) +;CHECK: input reset : UInt<1> ;CHECK: wire a$x : UInt ;CHECK: wire a$y : SInt ;CHECK: wire b$x : UInt diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir index 0b14c187..1e9c8f9f 100644 --- a/test/passes/lower-to-ground/nested-vec.fir +++ b/test/passes/lower-to-ground/nested-vec.fir @@ -4,24 +4,24 @@ circuit top : module q : wire i : UInt - wire j : { x : UInt(32), flip y : UInt(32) } + wire j : { x : UInt<32>, flip y : UInt<32> } - wire a : { x : UInt(32), flip y : UInt(32) }[2] - ; CHECK: wire a$0$x : UInt(32) - ; CHECK: wire a$0$y : UInt(32) - ; CHECK: wire a$1$x : UInt(32) - ; CHECK: wire a$1$y : UInt(32) + wire a : { x : UInt<32>, flip y : UInt<32> }[2] + ; CHECK: wire a$0$x : UInt<32> + ; CHECK: wire a$0$y : UInt<32> + ; CHECK: wire a$1$x : UInt<32> + ; CHECK: wire a$1$y : UInt<32> accessor b = a[i] - ; CHECK: wire b$x : UInt(32) - ; CHECK: wire b$y : UInt(32) + ; CHECK: wire b$x : UInt<32> + ; CHECK: wire b$y : UInt<32> ; CHECK: b$x := (a$0$x a$1$x)[i] ; CHECK: (a$0$y a$1$y)[i] := b$y j := b - mem m : { x : UInt(32), flip y : UInt(32) }[2] - ; CHECK: mem m$x : UInt(32)[2] - ; CHECK: mem m$y : UInt(32)[2] + mem m : { x : UInt<32>, flip y : UInt<32> }[2] + ; CHECK: mem m$x : UInt<32>[2] + ; CHECK: mem m$y : UInt<32>[2] accessor c = m[i] ; MALE ; CHECK: accessor c$x = m$x[i] diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir index 23ac8ac3..ecc427d9 100644 --- a/test/passes/lower-to-ground/register.fir +++ b/test/passes/lower-to-ground/register.fir @@ -3,13 +3,13 @@ ; CHECK: Lower To Ground circuit top : module top : - input a : UInt(16) - input b : UInt(16) + input a : UInt<16> + input b : UInt<16> output z : UInt reg r1 : { x : UInt, flip y : SInt } wire q : { x : UInt, flip y : SInt } - r1.init := q + on-reset r1 := q ; CHECK: reg r1$x : UInt ; CHECK: reg r1$y : SInt diff --git a/test/passes/make-explicit-reset/mix-reset.fir b/test/passes/make-explicit-reset/mix-reset.fir index 720663c1..a255dc33 100644 --- a/test/passes/make-explicit-reset/mix-reset.fir +++ b/test/passes/make-explicit-reset/mix-reset.fir @@ -3,26 +3,26 @@ ; CHECK: Make Explicit Reset circuit top : module A : - ;CHECK: input reset : UInt(1) - input x : UInt(16) - output y : UInt(16) + ;CHECK: input reset : UInt<1> + input x : UInt<16> + output y : UInt<16> inst b of B ;CHECK: b.reset := reset module B : - input reset : UInt(1) - ;CHECK: input reset : UInt(1) - input x : UInt(16) - output y : UInt(16) + input reset : UInt<1> + ;CHECK: input reset : UInt<1> + input x : UInt<16> + output y : UInt<16> inst c of C ;CHECK: c.reset := reset module C : - ;CHECK: input reset : UInt(1) - input a : UInt(16) - input b : UInt(16) + ;CHECK: input reset : UInt<1> + input a : UInt<16> + input b : UInt<16> module top : - ;CHECK: input reset : UInt(1) - input a : UInt(16) - input b : UInt(16) + ;CHECK: input reset : UInt<1> + input a : UInt<16> + input b : UInt<16> output z : UInt inst a of A ;CHECK: a.reset := reset diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir index 931372cb..8cae8ba4 100644 --- a/test/passes/resolve-genders/accessor.fir +++ b/test/passes/resolve-genders/accessor.fir @@ -3,7 +3,7 @@ ;CHECK: Resolve Genders circuit top : module top : - wire m : UInt(32)[10][10][10] + wire m : UInt<32>[10][10][10] wire i : UInt accessor a = m[i] ;CHECK: accessor a = m@[i@]@ accessor b = a[i] ;CHECK: accessor b = a@[i@]@ diff --git a/test/passes/resolve-genders/bigenders.fir b/test/passes/resolve-genders/bigenders.fir index 48987a9a..56029969 100644 --- a/test/passes/resolve-genders/bigenders.fir +++ b/test/passes/resolve-genders/bigenders.fir @@ -3,9 +3,9 @@ ;CHECK: Resolve Genders circuit top : module M : - input i : UInt(10) - output o : UInt(10) - wire w : {x : UInt(10), flip y : UInt(10)} + input i : UInt<10> + output o : UInt<10> + wire w : {x : UInt<10>, flip y : UInt<10>} w.x := i w.y := i o := w.x diff --git a/test/passes/resolve-genders/bulk.fir b/test/passes/resolve-genders/bulk.fir index 491760b6..9688a71b 100644 --- a/test/passes/resolve-genders/bulk.fir +++ b/test/passes/resolve-genders/bulk.fir @@ -3,9 +3,9 @@ ;CHECK: Resolve Genders circuit top : module source : - output bundle : { data : UInt(16), flip ready : UInt(1) } + output bundle : { data : UInt<16>, flip ready : UInt<1> } module sink : - input bundle : { data : UInt(16), flip ready : UInt(1) } + input bundle : { data : UInt<16>, flip ready : UInt<1> } module top : inst src of source inst snk of sink diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir index 44e0200f..b16c9b66 100644 --- a/test/passes/resolve-genders/gcd.fir +++ b/test/passes/resolve-genders/gcd.fir @@ -9,16 +9,16 @@ circuit top : z := sub-wrap(x, y) ;CHECK: z@ := sub-wrap-uu(x@, y@) module gcd : - input a : UInt(16) - input b : UInt(16) - input e : UInt(1) - output z : UInt(16) - output v : UInt(1) + input a : UInt<16> + input b : UInt<16> + input e : UInt<1> + output z : UInt<16> + output v : UInt<1> reg x : UInt reg y : UInt ; CHECK: reg x : UInt - x.init := UInt(0) - y.init := UInt(42) + on-reset x := UInt(0) + on-reset y := UInt(42) when gt(x, y) : ;CHECK: when gt-uu(x@, y@) : inst s of subtracter @@ -40,8 +40,8 @@ circuit top : v := eq(v, UInt(0)) z := x module top : - input a : UInt(16) - input b : UInt(16) + input a : UInt<16> + input b : UInt<16> output z : UInt inst i of gcd i.a := a diff --git a/test/passes/resolve-genders/ports.fir b/test/passes/resolve-genders/ports.fir index c1708631..3155dbcf 100644 --- a/test/passes/resolve-genders/ports.fir +++ b/test/passes/resolve-genders/ports.fir @@ -3,14 +3,14 @@ ;CHECK: Resolve Genders circuit top : module source : - output data : UInt(16) - input ready : UInt(1) + output data : UInt<16> + input ready : UInt<1> data := UInt(16) module sink : - input data : UInt(16) - output ready : UInt(1) + input data : UInt<16> + output ready : UInt<1> module top: - wire connect : { data : UInt(16), flip ready: UInt(1) } + wire connect : { data : UInt<16>, flip ready: UInt<1> } inst src of source ;CHECK: inst src of source@ inst snk of sink ;CHECK: inst snk of sink@ connect.data := src.data ;CHECK: connect@.data@ := src@.data@ diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir index 77cf13b3..6abc411a 100644 --- a/test/passes/resolve-genders/subbundle.fir +++ b/test/passes/resolve-genders/subbundle.fir @@ -3,8 +3,8 @@ ;CHECK: Lower To Ground circuit top : module M : - wire w : { flip x : UInt(10)} - reg r : { flip x : UInt(10)} + wire w : { flip x : UInt<10>} + reg r : { flip x : UInt<10>} w := r ; CHECK r$x := w$x w.x := r.x ; CHECK w$x := r$x ; CHECK: Finished Lower To Ground diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir index 4ad23a6a..10278fdb 100644 --- a/test/passes/resolve-kinds/gcd.fir +++ b/test/passes/resolve-kinds/gcd.fir @@ -9,15 +9,15 @@ circuit top : z := sub-wrap(x, y) ;CHECK: z@ := sub-wrap(x@, y@) module gcd : - input a : UInt(16) - input b : UInt(16) - input e : UInt(1) - output z : UInt(16) - output v : UInt(1) + input a : UInt<16> + input b : UInt<16> + input e : UInt<1> + output z : UInt<16> + output v : UInt<1> reg x : UInt reg y : UInt - x.init := UInt(0) - y.init := UInt(42) + on-reset x := UInt(0) + on-reset y := UInt(42) when gt(x, y) : inst s of subtracter s.x := x @@ -35,8 +35,8 @@ circuit top : v := eq(v, UInt(0)) z := x module top : - input a : UInt(16) - input b : UInt(16) + input a : UInt<16> + input b : UInt<16> output z : UInt inst i of gcd ;CHECK: inst i of gcd@ diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir index 75efa2f8..71835204 100644 --- a/test/passes/split-exp/gcd.fir +++ b/test/passes/split-exp/gcd.fir @@ -8,15 +8,15 @@ circuit top : output q : UInt q := sub-wrap-uu(x, y) module gcd : - input a : UInt(16) - input b : UInt(16) - input e : UInt(1) - output z : UInt(16) - output v : UInt(1) + input a : UInt<16> + input b : UInt<16> + input e : UInt<1> + output z : UInt<16> + output v : UInt<1> reg x : UInt reg y : UInt - x.init := UInt(0) - y.init := UInt(42) + on-reset x := UInt(0) + on-reset y := UInt(42) when gt-uu(x, y) : inst s of subtracter s.x := x @@ -33,8 +33,8 @@ circuit top : v := eq-uu(v, UInt(0)) z := x module top : - input a : UInt(16) - input b : UInt(16) + input a : UInt<16> + input b : UInt<16> output z : UInt inst i of gcd i.a := a diff --git a/test/passes/to-flo/gcd.fir b/test/passes/to-flo/gcd.fir index 9ea5d7b1..c8f2b268 100644 --- a/test/passes/to-flo/gcd.fir +++ b/test/passes/to-flo/gcd.fir @@ -8,15 +8,15 @@ circuit top : output q : UInt q := sub-wrap-uu(x, y) module gcd : - input a : UInt(16) - input b : UInt(16) - input e : UInt(1) - output z : UInt(16) - output v : UInt(1) + input a : UInt<16> + input b : UInt<16> + input e : UInt<1> + output z : UInt<16> + output v : UInt<1> reg x : UInt reg y : UInt - x.init := UInt(0) - y.init := UInt(42) + on-reset x := UInt(0) + on-reset y := UInt(42) when gt-uu(x, y) : inst s of subtracter s.x := x @@ -33,8 +33,8 @@ circuit top : v := eq-uu(v, UInt(0)) z := x module top : - input a : UInt(16) - input b : UInt(16) + input a : UInt<16> + input b : UInt<16> output z : UInt inst i of gcd i.a := a -- cgit v1.2.3 From 32148a311e06e8028b95da4bd8b1c888b5d8220f Mon Sep 17 00:00:00 2001 From: azidar Date: Thu, 23 Apr 2015 17:53:29 -0700 Subject: Not finished commmit --- TODO | 1 + src/main/stanza/firrtl-ir.stanza | 2 +- src/main/stanza/ir-parser.stanza | 2 +- src/main/stanza/ir-utils.stanza | 4 +-- src/main/stanza/passes.stanza | 45 +++++++++++++++++----------- test/passes/initialize-regs/bundle-init.fir | 21 +++++++++++++ test/passes/initialize-regs/nested-whens.fir | 26 ++++++++++++++++ 7 files changed, 80 insertions(+), 21 deletions(-) create mode 100644 test/passes/initialize-regs/bundle-init.fir create mode 100644 test/passes/initialize-regs/nested-whens.fir diff --git a/TODO b/TODO index c2a8180d..92dee2b7 100644 --- a/TODO +++ b/TODO @@ -24,6 +24,7 @@ Well-formed high firrtl UInt only has positive ints No combinational loops cannot connect to a pad, or a register. only connct to a reference + onreset can only handle a register After adding dynamic assertions, insert bounds check with accessor expansion Well-formed low firrtl All things only assigned to once diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza index 6a0b193c..0e5400b2 100644 --- a/src/main/stanza/firrtl-ir.stanza +++ b/src/main/stanza/firrtl-ir.stanza @@ -193,7 +193,7 @@ public defstruct Conditionally <: Stmt : public defstruct Begin <: Stmt : ;LOW body: List public defstruct OnReset <: Stmt : ;LOW - reg: Expression + loc: Expression exp: Expression public defstruct Connect <: Stmt : ;LOW loc: Expression diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza index c5296dc0..57a10f0a 100644 --- a/src/main/stanza/ir-parser.stanza +++ b/src/main/stanza/ir-parser.stanza @@ -263,7 +263,7 @@ defsyntax firrtl : stmt = (?s:#stmt/when) : s stmt = (?x:#exp := ?y:#exp!) : Connect(x, y) - stmt = (on-reset ?x:#exp := ?y:#exp!) : Connect(x, y);TODO + stmt = (on-reset ?x:#exp := ?y:#exp!) : OnReset(x, y) stmt = ((?s:#stmt ?ss:#stmt ... ?rest ...)) : if not empty?(rest) : diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza index 283fe9ea..507ccf94 100644 --- a/src/main/stanza/ir-utils.stanza +++ b/src/main/stanza/ir-utils.stanza @@ -180,7 +180,7 @@ defmethod print (o:OutputStream, c:Stmt) : (c:Connect) : print-all(o, [loc(c) " := " exp(c)]) (c:OnReset) : - print-all(o, ["on-reset " reg(c) " := " exp(c)]) + print-all(o, ["on-reset " loc(c) " := " exp(c)]) (c:EmptyStmt) : print(o, "skip") print-debug(o,c) @@ -260,7 +260,7 @@ defmethod map (f: Expression -> Expression, c:Stmt) -> Stmt : (c:DefInstance) : DefInstance(name(c), f(module(c))) (c:Conditionally) : Conditionally(f(pred(c)), conseq(c), alt(c)) (c:Connect) : Connect(f(loc(c)), f(exp(c))) - (c:OnReset) : OnReset(f(reg(c)),f(exp(c))) + (c:OnReset) : OnReset(f(loc(c)),f(exp(c))) (c) : c public defmulti map (f: Stmt -> Stmt, c:?T&Stmt) -> T diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 497f294d..495184e5 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -40,18 +40,27 @@ defstruct WRef <: Expression : kind: Kind gender: Gender with: (as-method => true) +defstruct WSubfield <: Expression : + exp: Expression + name: Symbol + type: Type with: (as-method => true) + gender: Gender with: (as-method => true) + defstruct WRegInit <: Expression : reg: Expression name: Symbol type: Type with: (as-method => true) gender: Gender with: (as-method => true) -defstruct WSubfield <: Expression : - exp: Expression - name: Symbol - type: Type with: (as-method => true) - gender: Gender with: (as-method => true) +defmethod map (f: Expression -> Expression, e: WRegInit) : + WRegInit(f(reg(e)), name(e), type(e), gender(e)) +defmethod map (f: Type -> Type, e: WRegInit) : + WRegInit(reg(e), name(e), f(type(e)), gender(e)) +defmethod print (o:OutputStream, e:WRegInit) : + print-all(o,[name(e)]) + print-debug(o,e as ?) + defstruct WIndex <: Expression : exp: Expression value: Int @@ -219,10 +228,6 @@ defmethod print (o:OutputStream, e:WRef) : print(o,name(e)) print-debug(o,e as ?) -defmethod print (o:OutputStream, e:WRegInit) : - print-all(o,[name(e)]) - print-debug(o,e as ?) - defmethod print (o:OutputStream, e:WSubfield) : print-all(o,[exp(e) "." name(e)]) print-debug(o,e as ?) @@ -243,8 +248,6 @@ defmethod print (o:OutputStream, c:ConnectFromIndexed) : print-all(o, [loc(c) " := " exps(c) "[" index(c) "]"]) print-debug(o,c as ?) -defmethod map (f: Expression -> Expression, e: WRegInit) : - WRegInit(f(reg(e)), name(e), type(e), gender(e)) defmethod map (f: Expression -> Expression, e: WSubfield) : WSubfield(f(exp(e)), name(e), type(e), gender(e)) defmethod map (f: Expression -> Expression, e: WIndex) : @@ -259,8 +262,6 @@ defmethod map (f: Expression -> Expression, c:ConnectFromIndexed) : defmethod map (f: Type -> Type, e: WRef) : WRef(name(e), f(type(e)), kind(e), gender(e)) -defmethod map (f: Type -> Type, e: WRegInit) : - WRegInit(reg(e), name(e), f(type(e)), gender(e)) defmethod map (f: Type -> Type, e: WSubfield) : WSubfield(exp(e), name(e), f(type(e)), gender(e)) defmethod map (f: Type -> Type, e: WIndex) : @@ -303,9 +304,7 @@ defn to-working-ir (c:Circuit) : defn to-exp (e:Expression) : match(map(to-exp,e)) : (e:Ref) : WRef(name(e), type(e), NodeKind(), UNKNOWN-GENDER) - (e:Subfield) : - if name(e) == `init : WRegInit(exp(e), to-symbol("~.init" % [name(exp(e) as WRef)]), type(e), UNKNOWN-GENDER) - else : WSubfield(exp(e), name(e), type(e), UNKNOWN-GENDER) + (e:Subfield) : WSubfield(exp(e), name(e), type(e), UNKNOWN-GENDER) (e:Index) : WIndex(exp(e), value(e), type(e), UNKNOWN-GENDER) (e) : e defn to-stmt (s:Stmt) : @@ -480,7 +479,7 @@ defn infer-types (s:Stmt, l:List>) -> [Stmt List>) -> Module : val ptypes = @@ -568,6 +567,8 @@ defn resolve-genders (c:Circuit) : WDefAccessor(name(s),source*,index*,gender*) (s:Connect) : Connect(resolve-expr(loc(s),FEMALE),resolve-expr(exp(s),MALE)) + (s:OnReset) : + OnReset(resolve-expr(loc(s),FEMALE),resolve-expr(exp(s),MALE)) (s:Conditionally) : val pred* = resolve-expr(pred(s),MALE) val conseq* = resolve-stmt(conseq(s)) @@ -725,6 +726,16 @@ defn lower (body:Stmt, table:HashTable>>) DefWire(name(s),type(value(s))), Connect(WRef(name(s),type(value(s)),NodeKind(),FEMALE),value(s))) lower-stmt(s*) + (s:OnReset) : Begin{_} $ + for (l in expand-expr(loc(s)), r in expand-expr(exp(s))) map : + println-debug(s) + val lgender = calc-gender(FEMALE,loc(s)) * value(l) + val rgender = calc-gender(MALE,exp(s)) * value(r) + println-debug(loc(s)) + println-debug(exp(s)) + switch fn ([x,y]) : lgender == x and rgender == y : + [FEMALE,MALE] : OnReset(key(l),key(r)) + [MALE,FEMALE] : OnReset(key(r),key(l)) (s:Connect) : Begin{_} $ for (l in expand-expr(loc(s)), r in expand-expr(exp(s))) map : println-debug(s) diff --git a/test/passes/initialize-regs/bundle-init.fir b/test/passes/initialize-regs/bundle-init.fir new file mode 100644 index 00000000..7e9af8df --- /dev/null +++ b/test/passes/initialize-regs/bundle-init.fir @@ -0,0 +1,21 @@ +; RUN: firrtl -i %s -o %s.flo -x abcdefghij -p c | tee %s.out | FileCheck %s +; CHECK: Done! +circuit top : + module A : + reg r : { x : UInt, flip y : UInt} + wire a : UInt + wire b : UInt + wire w : { x : UInt, flip y : UInt} + + r.x := a + r.y := b + on-reset r := w + +; CHECK: reg r : { x, flip y} +; CHECK: r.x := a +; CHECK: r.y := b +; CHECK: when reset : +; CHECK: r.x := w.x +; CHECK: w.y := r.y + + diff --git a/test/passes/initialize-regs/nested-whens.fir b/test/passes/initialize-regs/nested-whens.fir new file mode 100644 index 00000000..28cbc53d --- /dev/null +++ b/test/passes/initialize-regs/nested-whens.fir @@ -0,0 +1,26 @@ +; RUN: firrtl -i %s -o %s.flo -x abcdefghij -p c | tee %s.out | FileCheck %s +; CHECK: Done! +circuit top : + module A : + wire p : UInt + wire q : UInt + reg r : UInt + wire a : UInt + wire b : UInt + wire x : UInt + wire y : UInt + wire z : UInt + + on-reset r := w + when p + on-reset r := x + r := a + when q + on-reset r := y + r := b + r := z + +; CHECK: r := z +; CHECK: when reset +; CHECK: r := q?b:(p?a:w) + -- cgit v1.2.3 From e9462f11f6cfd68d0ada3b95a7d48621970e520e Mon Sep 17 00:00:00 2001 From: azidar Date: Fri, 24 Apr 2015 14:10:52 -0700 Subject: Inflight --- TODO | 1 + src/main/stanza/passes.stanza | 122 +++++++++++++++++++++++------------------- 2 files changed, 69 insertions(+), 54 deletions(-) diff --git a/TODO b/TODO index 92dee2b7..32f0bf21 100644 --- a/TODO +++ b/TODO @@ -25,6 +25,7 @@ Well-formed high firrtl No combinational loops cannot connect to a pad, or a register. only connct to a reference onreset can only handle a register + all references are declared After adding dynamic assertions, insert bounds check with accessor expansion Well-formed low firrtl All things only assigned to once diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 495184e5..25c18b0b 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -1169,12 +1169,26 @@ defn reduce-or (l:List) -> Expression : ; 1) Build Table, Build Declaration List -defn expand-whens (assign:HashTable, - kinds:HashTable, - stmts:HashTable, - decs:Vector, - enables:HashTable) -> Stmt : +; assign: holds the symbolic value of a wref. +; resets: holds the symbolic value of connections under reset +; stmts: Used to hold the orignal type, as well as the mem/index for Write/ReadPorts +; kinds: Used to know the kind of reference, so we know whether we should error if it isn't initialized. We also know how we should declare the refernce. +; enables:Calculated off of assigns. + +; I think I'm going to restructure this so that not all information is held in the tables, but instead, we walk the graph again, and do stuff on declarations, and delete other stuff +defn expand-whens (body:Stmt, + assign:HashTable, + resets:HashTable) -> Stmt : + + match(map(expad-whens{_,assign,resets},s)) : + (s:DefWire) : Begin $ list{s,_} $ + val ref = WRef(n,type(s),NodeKind,FEMALE) + if has-nul?(assign[n]) : + println("Uninitialized: ~" % [to-string(n)]);TODO actually collect error + EmptyStmt() + else : Connect(ref,to-exp(assign[n])) + (e: for x in assign do : val [n sv] = [key(x) value(x)] match(kinds[n]) : @@ -1259,83 +1273,83 @@ defn get-enables (assign:HashTable, defn build-tables (s:Stmt, assign:HashTable, - kinds:HashTable, - decs:Vector, - stmts:HashTable) -> False : + resets:HashTable, + flattn:HashTable, + ) -> False : match(s) : - (s:DefWire) : - add(decs,s) - kinds[name(s)] = WireKind() - assign[name(s)] = SVNul() - stmts[name(s)] = s - (s:DefNode) : add(decs,s) - (s:DefRegister) : - add(decs,DefWire(name(s),type(s))) - kinds[name(s)] = RegKind() + (s:DefWire) : assign[name(s)] = SVNul() - stmts[name(s)] = s - (s:WDefAccessor) : - add(decs,DefWire(name(s),type(type(source(s)) as VectorType))) + resets[name(s)] = SVNul() + flattn[name(s)] = true + (s:DefRegister|WDefAccessor) : assign[name(s)] = SVNul() - kinds[name(s)] = switch {_ == gender(s)} : - MALE : ReadAccessorKind() - FEMALE : WriteAccessorKind() - stmts[name(s)] = s - (s:DefInstance) : - add(decs,s) + resets[name(s)] = SVNul() + flattn[name(s)] = false + (s:DefInstance) : for f in fields(type(module(s)) as BundleType) do : val n = to-symbol("~.~" % [name(s),name(f)]) ; only on inputs - println-all-debug(["In DefInst adding: " n]) - kinds[n] = InstanceKind() assign[n] = SVNul() - stmts[n] = s - (s:DefMemory) : add(decs,s) + resets[n] = SVNul() + flattn[name(s)] = true + (s:DefMemory|DefNode) : false (s:Conditionally) : - val assign-c = deepcopy(assign) - val assign-a = deepcopy(assign) - build-tables(conseq(s),assign-c,kinds,decs,stmts) - build-tables(alt(s),assign-a,kinds,decs,stmts) - for i in get-unique-keys(list(assign-c,assign-a)) do : - assign[i] = match(get?(assign-c,i,false),get?(assign-a,i,false)) : ;TODO add to syntax highlighting - (c:SymbolicValue,a:SymbolicValue) : SVMux(pred(s),c,a) - (c:SymbolicValue,a:False) : - if kinds[i] typeof WireKind|InstanceKind|NodeKind : c + defn combine (flattn:HashTable, + table-c:HashTable, + table-a:HashTable, + i:Symbol + ) -> SymbolicValue : + match(get?(table-c,i,false),get?(table-a,i,false)) : + (c:SymbolicValue,a:SymbolicValue) : + if c == a : c + else : SVMux(pred(s),c,a) + (c:SymbolicValue,a:False) : + if flattn[i] : c else : SVMux(pred(s),c,SVNul()) - (c:False,a:SymbolicValue) : - if kinds[i] typeof WireKind|InstanceKind|NodeKind : a + (c:False,a:SymbolicValue) : + if flattn[i] : a else : SVMux(pred(s),SVNul(),a) (c:False,a:False) : error("Shouldn't be here") + + val assign-c = deepcopy(assign) + val assign-a = deepcopy(assign) + val resets-c = deepcopy(resets) + val resets-a = deepcopy(resets) + build-tables(conseq(s),assign-c,resets-c,flattn) + build-tables(alt(s),assign-a,resets-a,flattn) + for i in get-unique-keys(list(assign-c,assign-a)) do : + assign[i] = combine(flattn,assign-c,assign-a,i) + resets[i] = combine(flattn,resets-c,resets-a,i) ;println-debug("TABLE-C") ;for x in assign-c do : println-debug(x) ;println-debug("TABLE-A") ;for x in assign-a do : println-debug(x) ;println-debug("TABLE") ;for x in assign do : println-debug(x) - (s:Connect) : + (s:Connect|OnReset) : val key* = match(loc(s)) : (e:WRef) : name(e) (e:WSubfield) : symbol-join([name(exp(e) as ?) `. name(e)]) (e) : error("Shouldn't be here with ~" % [e]) - assign[key*] = SVExp(exp(s)); TODO, need to check all references are declared before this point - (s:Begin) : for s* in body(s) do: build-tables(s*,assign,kinds,decs,stmts) - (s) : false + if c typeof Connect : assign[key*] = SVExp(exp(s)) + if c typeof OnReset : resets[key*] = SVExp(exp(s)) + (s:Begin) : for s* in body(s) do: build-tables(s*,assign,resets) defn expand-whens (m:Module) -> Module : val assign = HashTable(symbol-hash) - val decs = Vector() - val kinds = HashTable(symbol-hash) - val stmts = HashTable(symbol-hash) + val resets = HashTable(symbol-hash) + val flattn = HashTable(symbol-hash) for p in ports(m) do : if direction(p) == OUTPUT : assign[name(p)] = SVNul() - kinds[name(p)] = PortKind() - stmts[name(p)] = DefWire(name(p),type(p)) + resets[name(p)] = SVNul() + flattn[name(p)] = false - build-tables(body(m),assign,kinds,decs,stmts) + build-tables(body(m),assign,resets) for x in assign do : assign[key(x)] = optimize(value(x)) - val enables = get-enables(assign,kinds) - for x in enables do : enables[key(x)] = optimize(value(x)) + for x in resets do : resets[key(x)] = optimize(value(x)) + ;val enables = get-enables(assign,kinds) + ;for x in enables do : enables[key(x)] = optimize(value(x)) ;println-debug("Assigns") ;for x in assign do : println-debug(x) @@ -1346,7 +1360,7 @@ defn expand-whens (m:Module) -> Module : ;println-debug("Enables") ;for x in enables do : println-debug(x) - Module(name(m),ports(m),expand-whens(assign,kinds,stmts,decs,enables)) + Module(name(m),ports(m),expand-whens(body(m),assign,resets)) defn expand-whens (c:Circuit) -> Circuit : Circuit(modules*, main(c)) where : -- cgit v1.2.3 From d455233c76148bb3f3d26734667b1b9a565d0f39 Mon Sep 17 00:00:00 2001 From: azidar Date: Fri, 24 Apr 2015 17:00:55 -0700 Subject: Merged TODO --- TODO | 6 ------ 1 file changed, 6 deletions(-) diff --git a/TODO b/TODO index ee27c94f..47588213 100644 --- a/TODO +++ b/TODO @@ -6,11 +6,8 @@ on-reset Make instances always male, flip the bundles on declaration dlsh,drsh -<<<<<<< HEAD move Infer-Widths to before vec expansion? Add Unit Tests for each pass -======= ->>>>>>> 5a2a495ce88eec9e2e79cfbfe7f5548cede25874 ======== Update Core ========== Add source locaters @@ -27,12 +24,9 @@ Well-formed high firrtl UInt only has positive ints No combinational loops cannot connect to a pad, or a register. only connct to a reference -<<<<<<< HEAD onreset can only handle a register all references are declared -======= expression in pad must be a ground type ->>>>>>> 5a2a495ce88eec9e2e79cfbfe7f5548cede25874 After adding dynamic assertions, insert bounds check with accessor expansion Well-formed low firrtl All things only assigned to once -- cgit v1.2.3 From 5179919db40caddf9205f190a5dc8b33a8995e56 Mon Sep 17 00:00:00 2001 From: azidar Date: Fri, 24 Apr 2015 17:37:00 -0700 Subject: Partial commit --- src/main/stanza/passes.stanza | 81 ++++++++++++++++++++++++++++++++----------- 1 file changed, 61 insertions(+), 20 deletions(-) diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 4057c3b8..88871bce 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -1157,15 +1157,15 @@ defn remove-nul (sv:SymbolicValue) -> SymbolicValue : (c:SVNul,a) : a (c,a) : sv (sv) : sv -defn to-exp (sv:SymbolicValue) -> Expression : +defn to-exp (sv:SymbolicValue) -> Expression|False : match(remove-nul(sv)) : (sv:SVMux) : DoPrim(MUX-UU-OP, - list(pred(sv),to-exp(conseq(sv)),to-exp(alt(sv))), + list(pred(sv),to-exp(conseq(sv)) as Expression,to-exp(alt(sv)) as Expression), list(), UIntType(IntWidth(1))) (sv:SVExp) : exp(sv) - (sv) : error("Shouldn't be here") + (sv:SVNul) : false defn reduce-or (l:List) -> True|False : if length(l) == 0 : false else : head(l) or reduce-or(tail(l)) @@ -1187,19 +1187,62 @@ defn reduce-or (l:List) -> Expression : ; enables:Calculated off of assigns. ; I think I'm going to restructure this so that not all information is held in the tables, but instead, we walk the graph again, and do stuff on declarations, and delete other stuff -defn expand-whens (body:Stmt, - assign:HashTable, - resets:HashTable) -> Stmt : +defn expand-whens (body:Stmt, table:HashTable) -> Stmt : - match(map(expad-whens{_,assign,resets},s)) : + match(map(expand-whens{_,table,resets},s)) : (s:DefWire) : Begin $ list{s,_} $ - val ref = WRef(n,type(s),NodeKind,FEMALE) - if has-nul?(assign[n]) : - println("Uninitialized: ~" % [to-string(n)]);TODO actually collect error + val ref = WRef(name(s),type(s),NodeKind,FEMALE) + if has-nul?(table[n]) : + println("Uninitialized: ~" % [to-string(name(s))]);TODO actually collect error EmptyStmt() - else : Connect(ref,to-exp(assign[n])) - (e: + else : Connect(ref,to-exp(table[name(s)])) + (s:DefRegister) : Begin $ list{s,_} $ + val ref = WRef(name(s),type(s),RegKind,FEMALE) + val e = to-exp(table[name(s)]) + match(e) : + (e:False) : EmptyStmt() + (e:Expression) : Register(type(s),e, to-exp $ get-write-enable(table[name(s)])) + (s:WDefAccessor) : Begin $ + val t = type(type(source(s)) as VectorType) + val n = name(s) + switch {_ == gender(s)} : + MALE : + val ref = WRef(n,t,ReadAccessorKind(),FEMALE) + list(DefWire(n,t), + Connect(ref,ReadPort(source(s),index(s),t,to-exp $ get-read-enable(table,n)))) + FEMALE : + val ref = WRef(n,t,WriteAccessorKind(),FEMALE) + val e = to-exp(table[n]) + val s* = match(e) : + (e:False) : + println("Uninitialized: ~" % [to-string(n)]) ;TODO actually collect error + EmptyStmt() + (e:Expression) : + Connect(ref,e) + list(DefWire(name(s),t), + Connect(WritePort(source(s),index(s),t,to-exp $ get-write-enable(table[n])),ref), + s*) + (s:DefInstance) : Begin $ + for f in fields(type(module(s)) as BundleType) do : + val n = to-symbol("~.~" % [name(s),name(f)]) ; only on inputs + val ref = WRef(n,type(s),PortKind,FEMALE) + if has-nul?(table[n]) : + println("Uninitialized: ~" % [to-string(name(s))]);TODO actually collect error + EmptyStmt() + else : Connect(ref,to-exp(table[name(s)])) + val x = to-symbol(split(to-string(n),'.')[0]) + val f = to-symbol(split(to-string(n),'.')[1]) + val ref = WRef(x,type(module(s)),k,FEMALE) + val sref = WSubfield(ref,f,bundle-field-type(type(module(s)),f),FEMALE) + if has-nul?(assign[n]) : println("Uninitialized: ~" % [to-string(n)]);TODO actually collect error + else : add(decs,Connect(sref,to-exp(assign[n]))) + (s:Connect) : EmptyStmt() + (s:Conditionally) : Begin(list(conseq(s),alt(s))) + (s:OnReset) : EmptyStmt() + (s:Begin) : s + + for x in assign do : val [n sv] = [key(x) value(x)] match(kinds[n]) : @@ -1298,6 +1341,7 @@ defn build-tables (s:Stmt, flattn[name(s)] = false (s:DefInstance) : for f in fields(type(module(s)) as BundleType) do : + if val n = to-symbol("~.~" % [name(s),name(f)]) ; only on inputs assign[n] = SVNul() resets[n] = SVNul() @@ -1364,14 +1408,11 @@ defn expand-whens (m:Module) -> Module : println-debug("Assigns") for x in assign do : println-debug(x) - println-debug("Kinds") - for x in kinds do : println-debug(x) - println-debug("Decs") - for x in decs do : println-debug(x) - println-debug("Enables") - for x in enables do : println-debug(x) - - Module(name(m),ports(m),expand-whens(body(m),assign,resets)) + println-debug("Resets") + for x in resets do : println-debug(x) + + val table = merge-resets(assign,resets) + Module(name(m),ports(m),expand-whens(body(m),table)) defn expand-whens (c:Circuit) -> Circuit : Circuit(modules*, main(c)) where : -- cgit v1.2.3 From 2d2120a05549a5d31072aa792dc96fb7e6e7c629 Mon Sep 17 00:00:00 2001 From: azidar Date: Mon, 27 Apr 2015 11:14:06 -0700 Subject: Added on-reset --- TODO | 1 - src/main/stanza/ir-parser.stanza | 1 + src/main/stanza/ir-utils.stanza | 6 +- src/main/stanza/passes.stanza | 377 ++++++++++++--------------- test/passes/expand-whens/bundle-init.fir | 25 ++ test/passes/expand-whens/nested-whens.fir | 24 ++ test/passes/infer-widths/gcd.fir | 2 +- test/passes/initialize-regs/bundle-init.fir | 21 -- test/passes/initialize-regs/nested-whens.fir | 26 -- test/passes/jacktest/MemorySearch.fir | 50 ++-- test/passes/jacktest/RegisterVecShift.fir | 50 ++-- test/passes/jacktest/Tlb.fir | 12 +- test/passes/lower-to-ground/register.fir | 4 +- 13 files changed, 282 insertions(+), 317 deletions(-) create mode 100644 test/passes/expand-whens/bundle-init.fir create mode 100644 test/passes/expand-whens/nested-whens.fir delete mode 100644 test/passes/initialize-regs/bundle-init.fir delete mode 100644 test/passes/initialize-regs/nested-whens.fir diff --git a/TODO b/TODO index 47588213..fd5685bd 100644 --- a/TODO +++ b/TODO @@ -3,7 +3,6 @@ ================================================ ======== Current Tasks ======== -on-reset Make instances always male, flip the bundles on declaration dlsh,drsh move Infer-Widths to before vec expansion? diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza index 57a10f0a..6e6ba1a2 100644 --- a/src/main/stanza/ir-parser.stanza +++ b/src/main/stanza/ir-parser.stanza @@ -129,6 +129,7 @@ OPERATORS[`convert-s] = CONVERT-S-OP OPERATORS[`bit-and-reduce] = BIT-AND-REDUCE-OP OPERATORS[`bit-or-reduce] = BIT-OR-REDUCE-OP OPERATORS[`bit-xor-reduce] = BIT-XOR-REDUCE-OP +OPERATORS[`bit-not] = BIT-NOT-OP OPERATORS[`bit-and] = BIT-AND-OP OPERATORS[`bit-or] = BIT-OR-OP OPERATORS[`bit-xor] = BIT-XOR-OP diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza index 67dfc89d..1131c1b3 100644 --- a/src/main/stanza/ir-utils.stanza +++ b/src/main/stanza/ir-utils.stanza @@ -129,12 +129,12 @@ defmethod print (o:OutputStream, op:PrimOp) : BIT-AND-OP : "bit-and" BIT-OR-OP : "bit-or" BIT-XOR-OP : "bit-xor" - CONCAT-OP : "cat" - BIT-SELECT-OP : "bit" - BITS-SELECT-OP : "bits" BIT-AND-REDUCE-OP : "bit-and-reduce" BIT-OR-REDUCE-OP : "bit-or-reduce" BIT-XOR-REDUCE-OP : "bit-xor-reduce" + CONCAT-OP : "cat" + BIT-SELECT-OP : "bit" + BITS-SELECT-OP : "bits" defmethod print (o:OutputStream, e:Expression) : match(e) : diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 88871bce..06ad6a97 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -132,7 +132,6 @@ defn times (f1:Flip,f2:Flip) -> Flip : REVERSE : swap(f1) defn to-field (p:Port) -> Field : - Field(name(p),REVERSE,type(p)) if direction(p) == OUTPUT : Field(name(p),REVERSE,type(p)) else if direction(p) == INPUT : Field(name(p),DEFAULT,type(p)) else : error("Shouldn't be here") @@ -929,70 +928,70 @@ defn expand-connect-indexed (c: Circuit) -> Circuit : ; This ensures proper behavior if this pass is run multiple ; times. -defn initialize-registers (c:Circuit) : - defn to-wire-name (y:Symbol) : symbol-join([ y "$init"]) - defn add-when (s:Stmt,h:HashTable) -> Stmt : - var inits = List() - for kv in h do : - val refreg = WRef(key(kv),value(kv),RegKind(),FEMALE) - val refwire = WRef(to-wire-name(key(kv)),value(kv),NodeKind(),MALE) - val connect = Connect(refreg,refwire) - inits = append(inits,list(connect)) - if empty?(inits) : s - else : - val pred = WRef(`reset, UIntType(IntWidth(1)), PortKind(), MALE) - val when-reset = Conditionally(pred,Begin(inits),Begin(List())) - Begin(list(s,when-reset)) - - defn rename (s:Stmt,h:HashTable) -> [Stmt HashTable] : - val t = HashTable(symbol-hash) - defn rename-expr (e:Expression) -> Expression : - match(map(rename-expr,e)) : - (e:WRegInit) : - val new-name = to-wire-name(name(reg(e) as WRef)) - WRef(new-name,type(reg(e)),RegKind(),gender(e)) - (e) : e - defn rename-stmt (s:Stmt) -> Stmt : - match(map(rename-stmt,s)) : - (s:DefRegister) : - if h[name(s)] : - t[name(s)] = type(s) - Begin(list(s,DefWire(to-wire-name(name(s)),type(s)))) - else : s - (s) : map(rename-expr,s) - [rename-stmt(s) t] - - defn init? (y:Symbol,s:Stmt) -> True|False : - var used? = false - defn has? (e:Expression) -> Expression : - match(map(has?,e)) : - (e:WRegInit) : - if name(reg(e) as WRef) == y : used? = true - (e) : map(has?,e) - e - map(has?,s) - used? - - defn using-init (s:Stmt,h:HashTable) -> Stmt : - match(s) : - (s:DefRegister) : h[name(s)] = false - (s) : - for x in h do : - h[key(x)] = value(x) or init?(key(x),s) - map(using-init{_,h},s) - - defn explicit-init-scope (s:Stmt) -> Stmt : - val h = HashTable(symbol-hash) - using-init(s,h) - ;println-debug(h) - val [s* t] = rename(s,h) - add-when(s*,t) - - Circuit(modules*, main(c)) where : - val modules* = - for m in modules(c) map : - Module(name(m), ports(m), body*) where : - val body* = explicit-init-scope(body(m)) +;defn initialize-registers (c:Circuit) : +; defn to-wire-name (y:Symbol) : symbol-join([ y "$init"]) +; defn add-when (s:Stmt,h:HashTable) -> Stmt : +; var inits = List() +; for kv in h do : +; val refreg = WRef(key(kv),value(kv),RegKind(),FEMALE) +; val refwire = WRef(to-wire-name(key(kv)),value(kv),NodeKind(),MALE) +; val connect = Connect(refreg,refwire) +; inits = append(inits,list(connect)) +; if empty?(inits) : s +; else : +; val pred = WRef(`reset, UIntType(IntWidth(1)), PortKind(), MALE) +; val when-reset = Conditionally(pred,Begin(inits),Begin(List())) +; Begin(list(s,when-reset)) +; +; defn rename (s:Stmt,h:HashTable) -> [Stmt HashTable] : +; val t = HashTable(symbol-hash) +; defn rename-expr (e:Expression) -> Expression : +; match(map(rename-expr,e)) : +; (e:WRegInit) : +; val new-name = to-wire-name(name(reg(e) as WRef)) +; WRef(new-name,type(reg(e)),RegKind(),gender(e)) +; (e) : e +; defn rename-stmt (s:Stmt) -> Stmt : +; match(map(rename-stmt,s)) : +; (s:DefRegister) : +; if h[name(s)] : +; t[name(s)] = type(s) +; Begin(list(s,DefWire(to-wire-name(name(s)),type(s)))) +; else : s +; (s) : map(rename-expr,s) +; [rename-stmt(s) t] +; +; defn init? (y:Symbol,s:Stmt) -> True|False : +; var used? = false +; defn has? (e:Expression) -> Expression : +; match(map(has?,e)) : +; (e:WRegInit) : +; if name(reg(e) as WRef) == y : used? = true +; (e) : map(has?,e) +; e +; map(has?,s) +; used? +; +; defn using-init (s:Stmt,h:HashTable) -> Stmt : +; match(s) : +; (s:DefRegister) : h[name(s)] = false +; (s) : +; for x in h do : +; h[key(x)] = value(x) or init?(key(x),s) +; map(using-init{_,h},s) +; +; defn explicit-init-scope (s:Stmt) -> Stmt : +; val h = HashTable(symbol-hash) +; using-init(s,h) +; ;println-debug(h) +; val [s* t] = rename(s,h) +; add-when(s*,t) +; +; Circuit(modules*, main(c)) where : +; val modules* = +; for m in modules(c) map : +; Module(name(m), ports(m), body*) where : +; val body* = explicit-init-scope(body(m)) ;;================ EXPAND WHENS ============================= ; This pass does three things: remove last connect semantics, @@ -1187,108 +1186,69 @@ defn reduce-or (l:List) -> Expression : ; enables:Calculated off of assigns. ; I think I'm going to restructure this so that not all information is held in the tables, but instead, we walk the graph again, and do stuff on declarations, and delete other stuff -defn expand-whens (body:Stmt, table:HashTable) -> Stmt : - - - match(map(expand-whens{_,table,resets},s)) : - (s:DefWire) : Begin $ list{s,_} $ - val ref = WRef(name(s),type(s),NodeKind,FEMALE) - if has-nul?(table[n]) : - println("Uninitialized: ~" % [to-string(name(s))]);TODO actually collect error - EmptyStmt() - else : Connect(ref,to-exp(table[name(s)])) - (s:DefRegister) : Begin $ list{s,_} $ - val ref = WRef(name(s),type(s),RegKind,FEMALE) - val e = to-exp(table[name(s)]) - match(e) : - (e:False) : EmptyStmt() - (e:Expression) : Register(type(s),e, to-exp $ get-write-enable(table[name(s)])) - (s:WDefAccessor) : Begin $ +defn expand-whens (s:Stmt, table:HashTable,decs:Vector,cons:Vector) -> Stmt : + match(map(expand-whens{_,table,decs,cons},s)) : + (s:DefNode|DefMemory) : add(decs,s) + (s:DefWire) : + add(decs,s) + add{cons,_} $ { + val ref = WRef(name(s),type(s),NodeKind(),FEMALE) + if has-nul?(table[name(s)]) : + println("Uninitialized: ~" % [to-string(name(s))]);TODO actually collect error + EmptyStmt() + else : Connect(ref,to-exp(table[name(s)]) as Expression) + }() + (s:DefRegister) : + add(decs,DefWire(name(s),type(s))) + add{cons,_} $ { + val ref = WRef(name(s),type(s),RegKind(),FEMALE) + val e = to-exp(table[name(s)]) + match(e) : + (e:False) : EmptyStmt() + (e:Expression) : Connect(ref,Register(type(s),e, to-exp(optimize $ get-write-enable(table[name(s)])) as Expression)) + }() + (s:WDefAccessor) : val t = type(type(source(s)) as VectorType) val n = name(s) - switch {_ == gender(s)} : - MALE : - val ref = WRef(n,t,ReadAccessorKind(),FEMALE) - list(DefWire(n,t), - Connect(ref,ReadPort(source(s),index(s),t,to-exp $ get-read-enable(table,n)))) - FEMALE : - val ref = WRef(n,t,WriteAccessorKind(),FEMALE) - val e = to-exp(table[n]) - val s* = match(e) : - (e:False) : - println("Uninitialized: ~" % [to-string(n)]) ;TODO actually collect error + add(decs,DefWire(n,t)) + add{cons,_} $ { + switch {_ == gender(s)} : + MALE : + val ref = WRef(n,t,ReadAccessorKind(),FEMALE) + Begin $ list $ Connect(ref,ReadPort(source(s),index(s),t,get-read-enable(n,table))) + FEMALE : + val ref = WRef(n,t,WriteAccessorKind(),FEMALE) + val e = to-exp(table[n]) + val s* = match(e) : + (e:False) : + println("Uninitialized: ~" % [to-string(n)]) ;TODO actually collect error + EmptyStmt() + (e:Expression) : + Connect(ref,e) + val enable = (to-exp $ optimize $ get-write-enable(table[n])) as Expression + val wp = WritePort(source(s),index(s),t,enable as Expression) + Begin $ list(Connect(wp,ref),s*) + }() + (s:DefInstance) : + add(decs,s) + add{cons,_} $ Begin $ + for f in fields(type(module(s)) as BundleType) map : + if flip(f) == DEFAULT : + val n = to-symbol("~.~" % [name(s),name(f)]) ; only on inputs + val x = to-symbol(split(to-string(n),'.')[0]) + val f = to-symbol(split(to-string(n),'.')[1]) + val ref = WRef(x,type(module(s)),InstanceKind(),FEMALE) + val sref = WSubfield(ref,f,bundle-field-type(type(module(s)),f),FEMALE) + if has-nul?(table[n]) : + println("Uninitialized: ~" % [to-string(n)]);TODO actually collect error EmptyStmt() - (e:Expression) : - Connect(ref,e) - list(DefWire(name(s),t), - Connect(WritePort(source(s),index(s),t,to-exp $ get-write-enable(table[n])),ref), - s*) - (s:DefInstance) : Begin $ - for f in fields(type(module(s)) as BundleType) do : - val n = to-symbol("~.~" % [name(s),name(f)]) ; only on inputs - val ref = WRef(n,type(s),PortKind,FEMALE) - if has-nul?(table[n]) : - println("Uninitialized: ~" % [to-string(name(s))]);TODO actually collect error - EmptyStmt() - else : Connect(ref,to-exp(table[name(s)])) - val x = to-symbol(split(to-string(n),'.')[0]) - val f = to-symbol(split(to-string(n),'.')[1]) - val ref = WRef(x,type(module(s)),k,FEMALE) - val sref = WSubfield(ref,f,bundle-field-type(type(module(s)),f),FEMALE) - if has-nul?(assign[n]) : println("Uninitialized: ~" % [to-string(n)]);TODO actually collect error - else : add(decs,Connect(sref,to-exp(assign[n]))) - (s:Connect) : EmptyStmt() - (s:Conditionally) : Begin(list(conseq(s),alt(s))) - (s:OnReset) : EmptyStmt() - (s:Begin) : s - + else : Connect(sref,to-exp(table[n]) as Expression) + else : EmptyStmt() + (s:Connect|Conditionally|OnReset|Begin|EmptyStmt) : false + s - for x in assign do : - val [n sv] = [key(x) value(x)] - match(kinds[n]) : - (k:WriteAccessorKind) : - ;First create WritePort and assign from accessor-turned-wire - val s = stmts[n] as WDefAccessor - val t = type(type(source(s)) as VectorType) - val ref = WRef(n,t,k,MALE) - val wp = WritePort(source(s),index(s),t,to-exp(enables[n])) - add(decs,Connect(wp,ref)) - ;If initialized, assign input to accessor-turned-wire - val sv = remove-nul(assign[n]) - if sv == SVNul : println("Uninitialized: ~" % [to-string(n)]) ;TODO actually collect error - else : add(decs,Connect(ref,to-exp(sv))) - (k:ReadAccessorKind) : - val s = stmts[n] as WDefAccessor - val t = type(type(source(s)) as VectorType) - val ref = WRef(n,t,k,FEMALE) - val rp = ReadPort(source(s),index(s),t,to-exp(enables[n])) - add(decs,Connect(ref,rp)) - (k:RegKind) : - val s = stmts[n] as DefRegister - val ref = WRef(n,type(s),k,FEMALE) - val sv = remove-nul(assign[n]) - val reg = - if sv typeof SVNul : Register(type(s),UIntValue(0,width(type(s) as ?)),zero) - else : Register(type(s),to-exp(sv),to-exp(enables[n])) - add(decs,Connect(ref,reg)) - (k:InstanceKind) : - val s = stmts[n] as DefInstance - val x = to-symbol(split(to-string(n),'.')[0]) - val f = to-symbol(split(to-string(n),'.')[1]) - val ref = WRef(x,type(module(s)),k,FEMALE) - val sref = WSubfield(ref,f,bundle-field-type(type(module(s)),f),FEMALE) - if has-nul?(assign[n]) : println("Uninitialized: ~" % [to-string(n)]);TODO actually collect error - else : add(decs,Connect(sref,to-exp(assign[n]))) - (k) : - val s = stmts[n] as DefWire - val ref = WRef(n,type(s),k,FEMALE) - if has-nul?(assign[n]) : println("Uninitialized: ~" % [to-string(n)]);TODO actually collect error - else : add(decs,Connect(ref,to-exp(assign[n]))) - Begin(to-list(decs)) - -defn get-enables (assign:HashTable, - kinds:HashTable) -> HashTable : - defn get-read-enable (sym:Symbol,sv:SymbolicValue) -> Expression : +defn get-read-enable (sym:Symbol,table:HashTable) -> Expression : + defn get-single-read-enable (sym:Symbol,sv:SymbolicValue) -> Expression : defn active (e:Expression) -> True|False : match(e) : (e:WRef) : name(e) == sym @@ -1300,30 +1260,30 @@ defn get-enables (assign:HashTable, if active(exp(sv)) : one else : zero (sv: SVMux) : - val e0 = get-read-enable(sym,SVExp(pred(sv))) - val e1 = get-read-enable(sym,conseq(sv)) - val e2 = get-read-enable(sym,alt(sv)) + val e0 = get-single-read-enable(sym,SVExp(pred(sv))) + val e1 = get-single-read-enable(sym,conseq(sv)) + val e2 = get-single-read-enable(sym,alt(sv)) if e1 == e2 : OR(e0,e1) else : OR(e0,OR(AND(pred(sv),e1),AND(NOT(pred(sv)),e2))) + DoPrim{BIT-OR-OP,_,list(),UIntType(IntWidth(1))} $ to-list $ + for y in table stream : get-single-read-enable(sym,value(y)) + +defn get-write-enable (sv:SymbolicValue) -> SymbolicValue : + match(map(get-write-enable,sv)) : + (sv: SVExp) : SVExp(one) + (sv: SVNul) : SVExp(zero) + (sv) : sv - defn get-write-enable (sv:SymbolicValue) -> SymbolicValue : - match(map(get-write-enable,sv)) : - (sv: SVExp) : SVExp(one) - (sv: SVNul) : SVExp(zero) - (sv) : sv - - val enables = HashTable(symbol-hash) - for x in assign do : - val sym = key(x) - match(kinds[sym]) : - (k:ReadAccessorKind) : - enables[sym] = SVExp{_} $ reduce-or{_} $ to-list{_} $ - for y in assign stream : - get-read-enable(sym,value(y)) - (k:WriteAccessorKind) : enables[sym] = get-write-enable(value(x)) - (k:RegKind) : enables[sym] = get-write-enable(value(x)) - (k) : k - enables +defn merge-resets (assign:HashTable, resets:HashTable) -> HashTable : + val table = HashTable(symbol-hash) + val reset = WRef(`reset, UnknownType(), PortKind(), MALE) + for i in get-unique-keys(list(assign,resets)) do : + table[i] = match(get?(assign,i,false),get?(resets,i,false)) : + (a:SymbolicValue,r:SymbolicValue) : SVMux(reset,r,a) + (a:SymbolicValue,r:False) : a + (a:False,r:SymbolicValue) : SVMux(reset,r,SVNul()) + (a:False,r:False) : error("Shouldn't be here") + table defn build-tables (s:Stmt, assign:HashTable, @@ -1333,26 +1293,22 @@ defn build-tables (s:Stmt, match(s) : (s:DefWire) : assign[name(s)] = SVNul() - resets[name(s)] = SVNul() flattn[name(s)] = true (s:DefRegister|WDefAccessor) : assign[name(s)] = SVNul() - resets[name(s)] = SVNul() flattn[name(s)] = false - (s:DefInstance) : + (s:DefInstance) : ;TODO only add instance input ports. This probably involves correcting instance genders for f in fields(type(module(s)) as BundleType) do : - if - val n = to-symbol("~.~" % [name(s),name(f)]) ; only on inputs - assign[n] = SVNul() - resets[n] = SVNul() - flattn[name(s)] = true - (s:DefMemory|DefNode) : false + if flip(f) == DEFAULT : + println-all-debug(["Instance: " s " has input " f]) + val n = to-symbol("~.~" % [name(s),name(f)]) ; only on inputs + assign[n] = SVNul() + flattn[n] = true (s:Conditionally) : defn combine (flattn:HashTable, table-c:HashTable, table-a:HashTable, - i:Symbol - ) -> SymbolicValue : + i:Symbol) -> SymbolicValue|False : match(get?(table-c,i,false),get?(table-a,i,false)) : (c:SymbolicValue,a:SymbolicValue) : if c == a : c @@ -1363,7 +1319,7 @@ defn build-tables (s:Stmt, (c:False,a:SymbolicValue) : if flattn[i] : a else : SVMux(pred(s),SVNul(),a) - (c:False,a:False) : error("Shouldn't be here") + (c:False,a:False) : false val assign-c = deepcopy(assign) val assign-a = deepcopy(assign) @@ -1372,8 +1328,11 @@ defn build-tables (s:Stmt, build-tables(conseq(s),assign-c,resets-c,flattn) build-tables(alt(s),assign-a,resets-a,flattn) for i in get-unique-keys(list(assign-c,assign-a)) do : - assign[i] = combine(flattn,assign-c,assign-a,i) - resets[i] = combine(flattn,resets-c,resets-a,i) + assign[i] = combine(flattn,assign-c,assign-a,i) as SymbolicValue + val r = combine(flattn,resets-c,resets-a,i) + match(r) : + (r:SymbolicValue) : resets[i] = r + (r) : false ;println-debug("TABLE-C") ;for x in assign-c do : println-debug(x) ;println-debug("TABLE-A") @@ -1385,9 +1344,10 @@ defn build-tables (s:Stmt, (e:WRef) : name(e) (e:WSubfield) : symbol-join([name(exp(e) as ?) `. name(e)]) (e) : error("Shouldn't be here with ~" % [e]) - if c typeof Connect : assign[key*] = SVExp(exp(s)) - if c typeof OnReset : resets[key*] = SVExp(exp(s)) - (s:Begin) : for s* in body(s) do: build-tables(s*,assign,resets) + if s typeof Connect : assign[key*] = SVExp(exp(s)) + if s typeof OnReset : resets[key*] = SVExp(exp(s)) + (s:Begin) : for s* in body(s) do: build-tables(s*,assign,resets,flattn) + (s:DefMemory|DefNode|EmptyStmt) : false defn expand-whens (m:Module) -> Module : val assign = HashTable(symbol-hash) @@ -1397,22 +1357,26 @@ defn expand-whens (m:Module) -> Module : for p in ports(m) do : if direction(p) == OUTPUT : assign[name(p)] = SVNul() - resets[name(p)] = SVNul() flattn[name(p)] = false - build-tables(body(m),assign,resets) + build-tables(body(m),assign,resets,flattn) for x in assign do : assign[key(x)] = optimize(value(x)) for x in resets do : resets[key(x)] = optimize(value(x)) ;val enables = get-enables(assign,kinds) ;for x in enables do : enables[key(x)] = optimize(value(x)) - println-debug("Assigns") + println-debug("====== Assigns ======") for x in assign do : println-debug(x) - println-debug("Resets") + println-debug("====== Resets ======") for x in resets do : println-debug(x) val table = merge-resets(assign,resets) - Module(name(m),ports(m),expand-whens(body(m),table)) + println-debug("====== Table ======") + for x in table do : println-debug(x) + val decs = Vector() + val cons = Vector() + expand-whens(body(m),table,decs,cons) + Module(name(m),ports(m),Begin(append(to-list(decs),to-list(cons)))) defn expand-whens (c:Circuit) -> Circuit : Circuit(modules*, main(c)) where : @@ -2103,7 +2067,6 @@ public defn run-passes (c: Circuit, p: List,file:String) : if contains(p,'X') or contains(p,'g') : do-stage("Expand Accessors", expand-accessors) if contains(p,'X') or contains(p,'h') : do-stage("Lower To Ground", lower-to-ground) if contains(p,'X') or contains(p,'i') : do-stage("Expand Indexed Connects", expand-connect-indexed) - if contains(p,'X') or contains(p,'j') : do-stage("Initialize Registers", initialize-registers) if contains(p,'X') or contains(p,'k') : do-stage("Expand Whens", expand-whens) if contains(p,'X') or contains(p,'l') : do-stage("Infer Widths", infer-widths) if contains(p,'X') or contains(p,'m') : do-stage("Inline Instances", inline-instances) diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir new file mode 100644 index 00000000..48336c93 --- /dev/null +++ b/test/passes/expand-whens/bundle-init.fir @@ -0,0 +1,25 @@ +; RUN: firrtl -i %s -o %s.flo -x abcdefghijk -p cd | tee %s.out | FileCheck %s +; CHECK: Expand Whens +circuit top : + module A : + reg r : { x : UInt, flip y : UInt} + wire a : UInt + wire b : UInt + wire w : { x : UInt, flip y : UInt} + a := UInt(1) + b := UInt(2) + + w.x := b + w.y := a + r.x := a + r.y := b + on-reset r := w + +; CHECK: r$x := Register(mux-uu(reset, w$x, a), UInt(1)) +; CHECK: r$y := Register(b, UInt(1)) +; CHECK: a := UInt(1) +; CHECK: b := UInt(2) +; CHECK: w$x := b +; CHECK: w$y := mux-uu(reset, r$y, a) + +; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir new file mode 100644 index 00000000..8185dade --- /dev/null +++ b/test/passes/expand-whens/nested-whens.fir @@ -0,0 +1,24 @@ +; RUN: firrtl -i %s -o %s.flo -x abcdefghijk -p c | tee %s.out | FileCheck %s +; CHECK: Expand Whens +circuit top : + module A : + wire p : UInt + wire q : UInt + reg r : UInt + wire a : UInt + wire b : UInt + wire x : UInt + wire y : UInt + wire z : UInt + wire w : UInt + + on-reset r := w + when p : + on-reset r := x + r := a + when q : + on-reset r := y + r := b + r := z +; CHECK: r := Register(mux-uu(reset, mux-uu(q, y, mux-uu(p, x, w)), z), UInt(1)) +; CHECK: Finished Expand Whens diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir index 0e9b5fed..3cd5c542 100644 --- a/test/passes/infer-widths/gcd.fir +++ b/test/passes/infer-widths/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cTd | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cd | tee %s.out | FileCheck %s ;CHECK: Infer Widths circuit top : diff --git a/test/passes/initialize-regs/bundle-init.fir b/test/passes/initialize-regs/bundle-init.fir deleted file mode 100644 index 7e9af8df..00000000 --- a/test/passes/initialize-regs/bundle-init.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefghij -p c | tee %s.out | FileCheck %s -; CHECK: Done! -circuit top : - module A : - reg r : { x : UInt, flip y : UInt} - wire a : UInt - wire b : UInt - wire w : { x : UInt, flip y : UInt} - - r.x := a - r.y := b - on-reset r := w - -; CHECK: reg r : { x, flip y} -; CHECK: r.x := a -; CHECK: r.y := b -; CHECK: when reset : -; CHECK: r.x := w.x -; CHECK: w.y := r.y - - diff --git a/test/passes/initialize-regs/nested-whens.fir b/test/passes/initialize-regs/nested-whens.fir deleted file mode 100644 index 28cbc53d..00000000 --- a/test/passes/initialize-regs/nested-whens.fir +++ /dev/null @@ -1,26 +0,0 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefghij -p c | tee %s.out | FileCheck %s -; CHECK: Done! -circuit top : - module A : - wire p : UInt - wire q : UInt - reg r : UInt - wire a : UInt - wire b : UInt - wire x : UInt - wire y : UInt - wire z : UInt - - on-reset r := w - when p - on-reset r := x - r := a - when q - on-reset r := y - r := b - r := z - -; CHECK: r := z -; CHECK: when reset -; CHECK: r := q?b:(p?a:w) - diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir index 955d44f2..60b62ac7 100644 --- a/test/passes/jacktest/MemorySearch.fir +++ b/test/passes/jacktest/MemorySearch.fir @@ -3,43 +3,43 @@ circuit MemorySearch : module MemorySearch : - input target : UInt(4) - output address : UInt(3) - input en : UInt(1) - output done : UInt(1) + input target : UInt<4> + output address : UInt<3> + input en : UInt<1> + output done : UInt<1> - node T_35 = UInt(0, 3) - reg index : UInt(3) - index.init := T_35 - node T_36 = UInt(0, 1) - node T_37 = UInt(4, 3) - node T_38 = UInt(15, 4) - node T_39 = UInt(14, 4) - node T_40 = UInt(2, 2) - node T_41 = UInt(5, 3) - node T_42 = UInt(13, 4) - wire elts : UInt(1)[7] - elts.0 := Pad(T_36,?) - elts.1 := Pad(T_37,?) - elts.2 := Pad(T_38,?) - elts.3 := Pad(T_39,?) - elts.4 := Pad(T_40,?) - elts.5 := Pad(T_41,?) - elts.6 := Pad(T_42,?) + node T_35 = UInt<3>(0) + reg index : UInt<3> + on-reset index := T_35 + node T_36 = UInt<1>(0) + node T_37 = UInt<3>(4) + node T_38 = UInt<4>(15) + node T_39 = UInt<4>(14) + node T_40 = UInt<2>(2) + node T_41 = UInt<3>(5) + node T_42 = UInt<4>(13) + wire elts : UInt<1>[7] + elts[0] := Pad(T_36,?) + elts[1] := Pad(T_37,?) + elts[2] := Pad(T_38,?) + elts[3] := Pad(T_39,?) + elts[4] := Pad(T_40,?) + elts[5] := Pad(T_41,?) + elts[6] := Pad(T_42,?) accessor elt = elts[index] node T_43 = bit-not(en) node T_44 = eq(Pad(elt,?), Pad(target,?)) - node T_45 = UInt(7, 3) + node T_45 = UInt<3>(7) node T_46 = eq(Pad(index,?), Pad(T_45,?)) node T_47 = bit-or(T_44, T_46) node end = bit-and(T_43, T_47) when en : - node T_48 = UInt(0, 1) + node T_48 = UInt<1>(0) index := Pad(T_48,?) else : node T_49 = bit-not(end) when T_49 : - node T_50 = UInt(1, 1) + node T_50 = UInt<1>(1) node T_51 = add-wrap(Pad(index,?), Pad(T_50,?)) index := Pad(T_51,?) done := Pad(end,?) diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir index 733e2036..832bd279 100644 --- a/test/passes/jacktest/RegisterVecShift.fir +++ b/test/passes/jacktest/RegisterVecShift.fir @@ -3,35 +3,35 @@ circuit RegisterVecShift : module RegisterVecShift : - input load : UInt(1) - output out : UInt(4) - input shift : UInt(1) - input ins : UInt(4)[4] + input load : UInt<1> + output out : UInt<4> + input shift : UInt<1> + input ins : UInt<4>[4] - reg delays : UInt(4)[4] + reg delays : UInt<4>[4] when reset : - node T_38 = UInt(0, 4) - node T_39 = UInt(0, 4) - node T_40 = UInt(0, 4) - node T_41 = UInt(0, 4) - wire T_42 : UInt(4)[4] - T_42.0 := T_38 - T_42.1 := T_39 - T_42.2 := T_40 - T_42.3 := T_41 + node T_38 = UInt<4>(0) + node T_39 = UInt<4>(0) + node T_40 = UInt<4>(0) + node T_41 = UInt<4>(0) + wire T_42 : UInt<4>[4] + T_42[0] := T_38 + T_42[1] := T_39 + T_42[2] := T_40 + T_42[3] := T_41 delays := T_42 - node T_43 = UInt(5, 3) + node T_43 = UInt<3>(5) node T_44 = bit-and(Pad(T_43,?), Pad(load,?)) - node T_45 = UInt(4, 3) + node T_45 = UInt<3>(4) node T_46 = eq(Pad(T_44,?), Pad(T_45,?)) when T_46 : - delays.0 := Pad(ins.0,?) - delays.1 := Pad(ins.1,?) - delays.2 := Pad(ins.2,?) - delays.3 := Pad(ins.3,?) + delays[0] := Pad(ins[0],?) + delays[1] := Pad(ins[1],?) + delays[2] := Pad(ins[2],?) + delays[3] := Pad(ins[3],?) else : when shift : - delays.0 := Pad(ins.0,?) - delays.1 := Pad(delays.0,?) - delays.2 := Pad(delays.1,?) - delays.3 := Pad(delays.2,?) - out := Pad(delays.3,?) + delays[0] := Pad(ins[0],?) + delays[1] := Pad(delays[0],?) + delays[2] := Pad(delays[1],?) + delays[3] := Pad(delays[2],?) + out := Pad(delays[3],?) diff --git a/test/passes/jacktest/Tlb.fir b/test/passes/jacktest/Tlb.fir index 35442ac8..b458ac4a 100644 --- a/test/passes/jacktest/Tlb.fir +++ b/test/passes/jacktest/Tlb.fir @@ -2,13 +2,13 @@ ; CHECK: Done! circuit Tbl : module Tbl : - output o : UInt(16) - input i : UInt(16) - input d : UInt(16) - input we : UInt(1) + output o : UInt<16> + input i : UInt<16> + input d : UInt<16> + input we : UInt<1> - mem m : UInt(10)[256] - node T_12 = UInt(0, 1) + mem m : UInt<10>[256] + node T_12 = UInt<1>(0) o := Pad(T_12,?) when we : accessor T_13 = m[i] diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir index ecc427d9..918710a5 100644 --- a/test/passes/lower-to-ground/register.fir +++ b/test/passes/lower-to-ground/register.fir @@ -15,7 +15,7 @@ ; CHECK: reg r1$y : SInt ; CHECK: wire q$x : UInt ; CHECK: wire q$y : SInt - ; CHECK: r1$x.init := q$x - ; CHECK: q$y := r1$y.init + ; CHECK: on-reset r1$x := q$x + ; CHECK: on-reset q$y := r1$y ; CHECK: Finished Lower To Ground -- cgit v1.2.3 From d6d630e6dbe3e5dd3c335cc8bd65a81d9dcb0f5f Mon Sep 17 00:00:00 2001 From: azidar Date: Mon, 27 Apr 2015 11:20:56 -0700 Subject: Removed WRegInit --- src/main/stanza/passes.stanza | 34 ++-------------------------------- 1 file changed, 2 insertions(+), 32 deletions(-) diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 06ad6a97..dacdce36 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -46,21 +46,6 @@ defstruct WSubfield <: Expression : type: Type with: (as-method => true) gender: Gender with: (as-method => true) -defstruct WRegInit <: Expression : - reg: Expression - name: Symbol - type: Type with: (as-method => true) - gender: Gender with: (as-method => true) - -defmethod map (f: Expression -> Expression, e: WRegInit) : - WRegInit(f(reg(e)), name(e), type(e), gender(e)) -defmethod map (f: Type -> Type, e: WRegInit) : - WRegInit(reg(e), name(e), f(type(e)), gender(e)) - -defmethod print (o:OutputStream, e:WRegInit) : - print-all(o,[name(e)]) - print-debug(o,e as ?) - defstruct WIndex <: Expression : exp: Expression value: Int @@ -190,7 +175,7 @@ defmethod print (o:OutputStream, k:Kind) : (k:WriteAccessorKind) : "wacc" defn hasGender (e:Expression|Stmt|Type|Port|Field) : - e typeof WRef|WSubfield|WIndex|WDefAccessor|WRegInit + e typeof WRef|WSubfield|WIndex|WDefAccessor defn hasWidth (e:Expression|Stmt|Type|Port|Field) : e typeof UIntType|SIntType|UIntValue|SIntValue|Pad @@ -198,7 +183,7 @@ defn hasWidth (e:Expression|Stmt|Type|Port|Field) : defn hasType (e:Expression|Stmt|Type|Port|Field) : e typeof Ref|Subfield|Index|DoPrim|WritePort|ReadPort|WRef|WSubfield |WIndex|DefWire|DefRegister|DefMemory|Register - |VectorType|Port|Field|WRegInit|Pad + |VectorType|Port|Field|Pad defn hasKind (e:Expression|Stmt|Type|Port|Field) : e typeof WRef @@ -448,7 +433,6 @@ defn infer-exp-types (e:Expression, l:List>) -> Expression match(r) : (e:WRef) : WRef(name(e), get-type(name(e),l),kind(e),gender(e)) (e:WSubfield) : WSubfield(exp(e),name(e), bundle-field-type(type(exp(e)),name(e)),gender(e)) - (e:WRegInit) : WRegInit(reg(e),name(e),get-type(name(reg(e) as WRef),l),gender(e)) (e:WIndex) : WIndex(exp(e),value(e), get-vector-subtype(type(exp(e))),gender(e)) (e:DoPrim) : lower-and-type-primop(e) ;DoPrim(op(e),args(e),consts(e),get-primop-rettype(e)) @@ -582,11 +566,6 @@ defn resolve-genders (c:Circuit) : WRef{name(e),type(e),kind(e),_} $ if gender == BI-GENDER : desired else : gender - (e:WRegInit) : - val gender = get-gender(name(reg(e) as WRef),desired) - WRegInit{reg(e),name(e),type(e),_} $ - if gender == BI-GENDER : desired - else : gender (e:WSubfield) : val field-flip = bundle-field-flip(name(e),type(exp(e))) val exp* = resolve-expr(exp(e),field-flip * desired) @@ -705,7 +684,6 @@ defn lower (body:Stmt, table:HashTable>>) defn calc-gender (g:Gender, e:Expression) -> Gender : match(e) : (e:WRef) : gender(e) - (e:WRegInit) : gender(e) (e:WSubfield) : if is-instance(exp(e)) : gender(e) else : calc-gender(bundle-field-flip(name(e),type(exp(e))) * g,exp(e)) @@ -789,7 +767,6 @@ defn lower (body:Stmt, table:HashTable>>) defn expand-expr (e:Expression) -> List> : match(e) : (e:WRef) : table[name(e)] - (e:WRegInit) : table[name(e)] (e:WSubfield) : val exps = expand-expr(exp(e)) val begin = index-of-elem(type(exp(e)) as BundleType,name(e)) @@ -837,12 +814,7 @@ defn lower-module (m:Module,table:HashTable f table[name(s)] = regs - table[init-sym] = init-regs (s:DefInstance) : val r = WRef(name(s),type(module(s)),InstanceKind(),FEMALE) val ports = table[name(module(s) as WRef)] @@ -1028,7 +1000,6 @@ defmethod equal? (e1:Expression,e2:Expression) -> True|False : else : false (e1:WRef,e2:WRef) : name(e1) == name(e2) ;(e1:DoPrim,e2:DoPrim) : TODO - (e1:WRegInit,e2:WRegInit) : reg(e1) == reg(e2) and name(e1) == name(e2) (e1:WSubfield,e2:WSubfield) : name(e1) == name(e2) (e1:Pad,e2:Pad) : width(e1) == width(e2) and value(e1) == value(e2) (e1:DoPrim,e2:DoPrim) : @@ -1820,7 +1791,6 @@ defn to-real-ir (c:Circuit) : match(map(to-exp,e)) : (e:WRef) : Ref(name(e), type(e)) (e:WSubfield) : Subfield(exp(e),name(e),type(e)) - (e:WRegInit) : error("Shouldn't be here") (e:WIndex) : error("Shouldn't be here") (e) : e defn to-stmt (s:Stmt) : -- cgit v1.2.3