From ed20e7c6c77543756e1ebc7bc1e6ae7d10911f0a Mon Sep 17 00:00:00 2001 From: azidar Date: Sat, 16 Jan 2016 12:42:15 -0800 Subject: Added notes for Richard to work on --- src/main/scala/firrtl/IR.scala | 15 ++++++++------- src/main/scala/firrtl/Utils.scala | 4 ++++ 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/src/main/scala/firrtl/IR.scala b/src/main/scala/firrtl/IR.scala index 3dbf3dae..e7356abc 100644 --- a/src/main/scala/firrtl/IR.scala +++ b/src/main/scala/firrtl/IR.scala @@ -68,9 +68,10 @@ case class UIntValue(value: BigInt, width: Width) extends Exp case class SIntValue(value: BigInt, width: Width) extends Exp case class Ref(name: String, tpe: Type) extends Exp case class Subfield(exp: Exp, name: String, tpe: Type) extends Exp -case class Index(exp: Exp, value: BigInt, tpe: Type) extends Exp +case class Index(exp: Exp, value: BigInt, tpe: Type) extends Exp //SubIndex, add SubAccess case class DoPrimop(op: Primop, args: Seq[Exp], consts: Seq[BigInt], tpe: Type) extends Exp +// THIS GOES BYE BYE trait AccessorDir extends AST case object Infer extends AccessorDir case object Read extends AccessorDir @@ -79,19 +80,19 @@ case object RdWr extends AccessorDir trait Stmt extends AST case class DefWire(info: Info, name: String, tpe: Type) extends Stmt -case class DefReg(info: Info, name: String, tpe: Type, clock: Exp, reset: Exp) extends Stmt -case class DefMemory(info: Info, name: String, seq: Boolean, tpe: Type, clock: Exp) extends Stmt +case class DefReg(info: Info, name: String, tpe: Type, clock: Exp, reset: Exp) extends Stmt //Added init value +case class DefMemory(info: Info, name: String, seq: Boolean, tpe: Type, clock: Exp) extends Stmt //very different case class DefInst(info: Info, name: String, module: Exp) extends Stmt case class DefNode(info: Info, name: String, value: Exp) extends Stmt case class DefPoison(info: Info, name: String, tpe: Type) extends Stmt -case class DefAccessor(info: Info, name: String, dir: AccessorDir, source: Exp, index: Exp) extends Stmt -case class OnReset(info: Info, lhs: Exp, rhs: Exp) extends Stmt +case class DefAccessor(info: Info, name: String, dir: AccessorDir, source: Exp, index: Exp) extends Stmt //BYE BYE +case class OnReset(info: Info, lhs: Exp, rhs: Exp) extends Stmt //BYE BYE case class Connect(info: Info, lhs: Exp, rhs: Exp) extends Stmt case class BulkConnect(info: Info, lhs: Exp, rhs: Exp) extends Stmt case class When(info: Info, pred: Exp, conseq: Stmt, alt: Stmt) extends Stmt -case class Assert(info: Info, pred: Exp) extends Stmt +case class Assert(info: Info, pred: Exp) extends Stmt //Now Stop, with clk and enable and int, add Print case class Block(stmts: Seq[Stmt]) extends Stmt -case object EmptyStmt extends Stmt +case object EmptyStmt extends Stmt //Now Empty trait Width extends AST case class IntWidth(width: BigInt) extends Width diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala index d767f027..fc2efba8 100644 --- a/src/main/scala/firrtl/Utils.scala +++ b/src/main/scala/firrtl/Utils.scala @@ -5,6 +5,10 @@ * - Find way to have generic map function instead of mapE and mapS under Stmt implicits */ +/* TODO Richard + * - add new IR nodes to all Util functions + */ + package firrtl import scala.collection.mutable.StringBuilder -- cgit v1.2.3 From 4dc5995cae85ccbcb11d0648143bb8d26a16f135 Mon Sep 17 00:00:00 2001 From: azidar Date: Sat, 16 Jan 2016 12:42:15 -0800 Subject: Added notes for Richard to work on --- src/main/scala/firrtl/IR.scala | 15 ++++++++------- src/main/scala/firrtl/Utils.scala | 4 ++++ 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/src/main/scala/firrtl/IR.scala b/src/main/scala/firrtl/IR.scala index 3dbf3dae..e7356abc 100644 --- a/src/main/scala/firrtl/IR.scala +++ b/src/main/scala/firrtl/IR.scala @@ -68,9 +68,10 @@ case class UIntValue(value: BigInt, width: Width) extends Exp case class SIntValue(value: BigInt, width: Width) extends Exp case class Ref(name: String, tpe: Type) extends Exp case class Subfield(exp: Exp, name: String, tpe: Type) extends Exp -case class Index(exp: Exp, value: BigInt, tpe: Type) extends Exp +case class Index(exp: Exp, value: BigInt, tpe: Type) extends Exp //SubIndex, add SubAccess case class DoPrimop(op: Primop, args: Seq[Exp], consts: Seq[BigInt], tpe: Type) extends Exp +// THIS GOES BYE BYE trait AccessorDir extends AST case object Infer extends AccessorDir case object Read extends AccessorDir @@ -79,19 +80,19 @@ case object RdWr extends AccessorDir trait Stmt extends AST case class DefWire(info: Info, name: String, tpe: Type) extends Stmt -case class DefReg(info: Info, name: String, tpe: Type, clock: Exp, reset: Exp) extends Stmt -case class DefMemory(info: Info, name: String, seq: Boolean, tpe: Type, clock: Exp) extends Stmt +case class DefReg(info: Info, name: String, tpe: Type, clock: Exp, reset: Exp) extends Stmt //Added init value +case class DefMemory(info: Info, name: String, seq: Boolean, tpe: Type, clock: Exp) extends Stmt //very different case class DefInst(info: Info, name: String, module: Exp) extends Stmt case class DefNode(info: Info, name: String, value: Exp) extends Stmt case class DefPoison(info: Info, name: String, tpe: Type) extends Stmt -case class DefAccessor(info: Info, name: String, dir: AccessorDir, source: Exp, index: Exp) extends Stmt -case class OnReset(info: Info, lhs: Exp, rhs: Exp) extends Stmt +case class DefAccessor(info: Info, name: String, dir: AccessorDir, source: Exp, index: Exp) extends Stmt //BYE BYE +case class OnReset(info: Info, lhs: Exp, rhs: Exp) extends Stmt //BYE BYE case class Connect(info: Info, lhs: Exp, rhs: Exp) extends Stmt case class BulkConnect(info: Info, lhs: Exp, rhs: Exp) extends Stmt case class When(info: Info, pred: Exp, conseq: Stmt, alt: Stmt) extends Stmt -case class Assert(info: Info, pred: Exp) extends Stmt +case class Assert(info: Info, pred: Exp) extends Stmt //Now Stop, with clk and enable and int, add Print case class Block(stmts: Seq[Stmt]) extends Stmt -case object EmptyStmt extends Stmt +case object EmptyStmt extends Stmt //Now Empty trait Width extends AST case class IntWidth(width: BigInt) extends Width diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala index d767f027..fc2efba8 100644 --- a/src/main/scala/firrtl/Utils.scala +++ b/src/main/scala/firrtl/Utils.scala @@ -5,6 +5,10 @@ * - Find way to have generic map function instead of mapE and mapS under Stmt implicits */ +/* TODO Richard + * - add new IR nodes to all Util functions + */ + package firrtl import scala.collection.mutable.StringBuilder -- cgit v1.2.3 From f8d2ac8452e562590ad080265815cb9f3ea26bfc Mon Sep 17 00:00:00 2001 From: ducky Date: Sat, 16 Jan 2016 14:09:31 -0800 Subject: Update README with better Linux and Scala instructions --- README.md | 70 ++++++++++++++++++++++++++++++++++++--------------------------- 1 file changed, 40 insertions(+), 30 deletions(-) diff --git a/README.md b/README.md index 98a7868f..01648fa9 100644 --- a/README.md +++ b/README.md @@ -3,50 +3,60 @@ This repository contains the compiler for .fir files. It is currently being developed in stanza, with the end-goal to translate into scala for ease of other people to use. - This decision was made for multiple reasons: - 1. Previous development had already been done in stanza - 2. Most of the passes are relatively language independent - 3. Stanza is easier to develop in than scala bc less-strict type system - 4. As a favor, its useful to develop in stanza to give Patrick some language tips :) - The hardest part to port will likely be the parser, but we hope to use an existing scala-based general-purpose parser for the port. + This decision was made for multiple reasons: + 1. Previous development had already been done in stanza + 2. Most of the passes are relatively language independent + 3. Stanza is easier to develop in than scala bc less-strict type system + 4. As a favor, its useful to develop in stanza to give Patrick some language tips :) + The hardest part to port will likely be the parser, but we hope to use an existing scala-based general-purpose parser for the port. #### Installation Instructions *Disclaimer*: This project is going through development stages so there is no guarantee anything works. -##### For Linux: - 1. Clone the repository: +##### For Linux: + 1. Clone the repository: `git clone https://github.com/ucb-bar/firrtl` - 1. Install lit (you need to have pip installed first): + 1. Install lit (you need to have pip installed first): `pip install lit` - 1. Build firrtl: + 1. Inflate stanza (this will fail before it builds firrtl): `make build` + 1. Remove first empty line in `utils/bin/stanza`, so the first line now becomes `#!/bin/bash`. + 1. Actually build firrtl: + `make build` + 1. Run `make set-linux`, which links the FileCheck binary to the Linux version. + The original binary is compiled for Mac and will not work. + * **Note**: This compiled binary may not run on all platforms. You may need to build + Clang/LLVM from source to extract the compiled FileCheck utility. 1. Add `firrtl/utils/bin` to your `PATH`, so that the compiled firrtl will be available anywhere. This also makes FileCheck available for the tests. - 1. Rename `FileCheck_linux` in `firrtl/utils/bin` to `FileCheck`. The original - `FileCheck` is a compiled Mac version and will not run on Linux. - *Note: This compiled binary may not run on all platforms. You may need to build - Clang/LLVM from source to extract the compiled FileCheck utility.* - 1. Run tests: + 1. Run tests: `make check` - 1. Build and test: + * **Note**: Stanza eats a 🐣🐣🐣🐣ton of memory and running many instances + simultaneously (as the build script does) may stall your system due to + excessive paging. Setting a memory limit seems to make everything behave + better: `ulimit -v 3096000` + 1. Build and test: `make` -##### For Mac: - 1. Clone the repository: +##### For Mac: + 1. Clone the repository: `git clone https://github.com/ucb-bar/firrtl` - 1. Install lit (you need to have pip installed first): + 1. Install lit (you need to have pip installed first): `pip install lit` - 1. Build firrtl: - `make build` - 1. Run tests: + 1. Build firrtl: + `make build` + 1. Run tests: `make check` - 1. Build and test: + 1. Build and test: `make` -#### Scala implementation -The Scala FIRRTL implementation relies upon sbt 0.13.6. It uses sbt-assembly to create a fat JAR. -Using a bash script and a symbolic link it can be used with the same command-line arguments as the stanza implementation. -Example use: - `make build-scala` - `make set-scala` # Creates symbolic link, make set-stanza reverts to stanza implementation - `./utils/bin/firrtl -i -o -X ` +#### Scala implementation +The Scala FIRRTL implementation relies upon sbt 0.13.6. It uses sbt-assembly to create a fat JAR. +Using a bash script and a symbolic link it can be used with the same command-line arguments as the stanza implementation. +Example use: + 1. Build the fat JAR using the makefile: `make build-scala`, or using sbt: `sbt assembly` + * For development, you can have sbt automatically monitor for changes and recompile: `sbt ~assembly` + 1. Link firrtl to the Scala version: `make set-scala` (can be reverted with `make set-stanza`) + 1. Scala firrtl can be invoked in the same way as Stanza firrtl: + `./utils/bin/firrtl -i -o -X ` + * As a result, the test make targets should use Scala firrtl and work properly -- cgit v1.2.3 From 017c6547d38b88a2b3121b88f61dfe50cd3fa266 Mon Sep 17 00:00:00 2001 From: ducky Date: Sat, 16 Jan 2016 14:11:04 -0800 Subject: Default platform-agnostic, ignore platform-specific FileCheck --- .gitignore | 1 + README.md | 6 +++--- utils/bin/FileCheck | Bin 1017048 -> 0 bytes 3 files changed, 4 insertions(+), 3 deletions(-) delete mode 100755 utils/bin/FileCheck diff --git a/.gitignore b/.gitignore index 6a02ef4a..899e81f0 100644 --- a/.gitignore +++ b/.gitignore @@ -26,6 +26,7 @@ utils/bin/firrtl utils/bin/stanza utils/bin/firrtl-scala utils/bin/firrtl-stanza +utils/bin/FileCheck spec/spec.aux spec/spec.log spec/spec.toc diff --git a/README.md b/README.md index 01648fa9..cb1ef726 100644 --- a/README.md +++ b/README.md @@ -24,7 +24,6 @@ 1. Actually build firrtl: `make build` 1. Run `make set-linux`, which links the FileCheck binary to the Linux version. - The original binary is compiled for Mac and will not work. * **Note**: This compiled binary may not run on all platforms. You may need to build Clang/LLVM from source to extract the compiled FileCheck utility. 1. Add `firrtl/utils/bin` to your `PATH`, so that the compiled firrtl will be @@ -45,6 +44,7 @@ `pip install lit` 1. Build firrtl: `make build` + 1. Run `make set-osx`, which links the FileCheck binary to the Mac version. 1. Run tests: `make check` 1. Build and test: @@ -57,6 +57,6 @@ Example use: 1. Build the fat JAR using the makefile: `make build-scala`, or using sbt: `sbt assembly` * For development, you can have sbt automatically monitor for changes and recompile: `sbt ~assembly` 1. Link firrtl to the Scala version: `make set-scala` (can be reverted with `make set-stanza`) - 1. Scala firrtl can be invoked in the same way as Stanza firrtl: + 1. Scala firrtl can be invoked in the same way as Stanza firrtl (and the test + make targets should continue to work): `./utils/bin/firrtl -i -o -X ` - * As a result, the test make targets should use Scala firrtl and work properly diff --git a/utils/bin/FileCheck b/utils/bin/FileCheck deleted file mode 100755 index 2ab52bb6..00000000 Binary files a/utils/bin/FileCheck and /dev/null differ -- cgit v1.2.3 From a9d181e351f1c13c009f75cef3106f25ea435d1a Mon Sep 17 00:00:00 2001 From: ducky Date: Sat, 16 Jan 2016 16:08:25 -0800 Subject: Refactor passes system --- src/main/scala/firrtl/Driver.scala | 175 +++++++++++++++++++------------------ 1 file changed, 91 insertions(+), 84 deletions(-) diff --git a/src/main/scala/firrtl/Driver.scala b/src/main/scala/firrtl/Driver.scala index 4b3b2967..82eb3962 100644 --- a/src/main/scala/firrtl/Driver.scala +++ b/src/main/scala/firrtl/Driver.scala @@ -8,6 +8,51 @@ import Utils._ import DebugUtils._ import Passes._ + +trait DriverPass { + def run(input: String, output: String)(implicit logger: Logger) : Unit +} +case class StanzaPass(val passes : Seq[String]) extends DriverPass { + def run(input : String, output : String)(implicit logger : Logger) : Unit = { + val cmd = Seq("firrtl-stanza", "-i", input, "-o", output, "-b", "firrtl") ++ passes.flatMap(x=>Seq("-x", x)) + println(cmd.mkString(" ")) + val ret = cmd.!! + println(ret) + } +} +case class ScalaPass(val func : Circuit => Circuit) extends DriverPass { + def run(input : String, output : String)(implicit logger : Logger) : Unit = { + var ast = Parser.parse(input, Source.fromFile(input).getLines) + val newast = func(ast) + println("Writing to " + output) + val writer = new PrintWriter(new File(output)) + writer.write(newast.serialize()) + writer.close() + } +} +object StanzaPass { + def apply(pass: String): StanzaPass = StanzaPass(Seq(pass)) +} + +object DriverPasses { + private def aggregateStanzaPasses(passes: Seq[DriverPass]): Seq[DriverPass] = { + if (passes.isEmpty) return Seq() + val span = passes.span(x => x match { + case p : StanzaPass => true + case _ => false + }) + if (span._1.isEmpty) { + Seq(span._2.head) ++ aggregateStanzaPasses(span._2.tail) + } else { + Seq(StanzaPass(span._1.flatMap(x=>x.asInstanceOf[StanzaPass].passes))) ++ aggregateStanzaPasses(span._2) + } + } + + def optimize(passes: Seq[DriverPass]): Seq[DriverPass] = { + aggregateStanzaPasses(passes) + } +} + object Driver { private val usage = """ @@ -28,6 +73,49 @@ object Driver path + name + count + ext } + val defaultPasses = DriverPasses.optimize(Seq( + StanzaPass("to-firrtl"), + + StanzaPass("high-form-check"), + +// ScalaPass(renameall(Map( +// "c"->"ccc", +// "z"->"zzz", +// "top"->"its_a_top_module" +// ))), + // StanzaPass("temp-elim"), // performance pass + StanzaPass("to-working-ir"), + + StanzaPass("resolve-kinds"), + StanzaPass("infer-types"), + StanzaPass("check-types"), + StanzaPass("resolve-genders"), + StanzaPass("check-genders"), + StanzaPass("infer-widths"), + StanzaPass("width-check"), + + StanzaPass("check-kinds"), + + StanzaPass("expand-accessors"), + StanzaPass("lower-to-ground"), + StanzaPass("inline-indexers"), + StanzaPass("infer-types"), + //ScalaPass(inferTypes), + StanzaPass("check-genders"), + StanzaPass("expand-whens"), + + StanzaPass("real-ir"), + + StanzaPass("pad-widths"), + StanzaPass("const-prop"), + StanzaPass("split-expressions"), + StanzaPass("width-check"), + StanzaPass("high-form-check"), + StanzaPass("low-form-check"), + StanzaPass("check-init")//, + //ScalaPass(renamec) + )) + // Parse input file and print to output private def firrtl(input: String, output: String)(implicit logger: Logger) { @@ -49,91 +137,10 @@ object Driver executePassesWithLogger(ast, passes) } - trait Pass - case class StanzaPass(val name : String) extends Pass - case class AggregatedStanzaPass(val passes : Seq[StanzaPass]) extends Pass - case class ScalaPass(val func : Circuit => Circuit) extends Pass - - def aggregateStanzaPasses(l : Seq[Pass]) : Seq[Pass] = { - if (l.isEmpty) return Seq() - val span = l.span(x => x match { - case p : StanzaPass => true - case _ => false - }) - if (span._1.isEmpty) { - val tail = if(span._2.length > 1) - aggregateStanzaPasses(span._2.tail) - else - Seq() - Seq(span._2.head) ++ tail - } else { - Seq(AggregatedStanzaPass(span._1.asInstanceOf[Seq[StanzaPass]])) ++ aggregateStanzaPasses(span._2) - } - } - - def run(pass : Pass, input : String, output : String)(implicit logger : Logger) : Unit = pass match { - case p : StanzaPass => - val cmd = Seq("firrtl-stanza", "-i", input, "-o", output, "-b", "firrtl", "-x", p.name) - println(cmd.mkString(" ")) - val ret = cmd.!! - println(ret) - case p : AggregatedStanzaPass => - val cmd = Seq("firrtl-stanza", "-i", input, "-o", output, "-b", "firrtl") ++ p.passes.flatMap(x=>Seq("-x", x.name)) - println(cmd.mkString(" ")) - val ret = cmd.!! - println(ret) - case p : ScalaPass => - var ast = Parser.parse(input, Source.fromFile(input).getLines) - val newast = p.func(ast) - println("Writing to " + output) - val writer = new PrintWriter(new File(output)) - writer.write(newast.serialize()) - writer.close() - case _ => logger.warn("Pass " + pass + " cannot be run") - } - - private def verilog(input: String, output: String)(implicit logger: Logger) - { - - val passes = aggregateStanzaPasses(Seq( - StanzaPass("rem-spec-chars"), - StanzaPass("high-form-check"), - ScalaPass(renameall(Map( - "c"->"ccc", - "z"->"zzz", - "top"->"its_a_top_module" - ))), - StanzaPass("temp-elim"), - StanzaPass("to-working-ir"), - StanzaPass("resolve-kinds"), - StanzaPass("infer-types"), - StanzaPass("resolve-genders"), - StanzaPass("check-genders"), - StanzaPass("check-kinds"), - StanzaPass("check-types"), - StanzaPass("expand-accessors"), - StanzaPass("lower-to-ground"), - StanzaPass("inline-indexers"), - StanzaPass("infer-types"), - //ScalaPass(inferTypes), - StanzaPass("check-genders"), - StanzaPass("expand-whens"), - StanzaPass("infer-widths"), - StanzaPass("real-ir"), - StanzaPass("width-check"), - StanzaPass("pad-widths"), - StanzaPass("const-prop"), - StanzaPass("split-expressions"), - StanzaPass("width-check"), - StanzaPass("high-form-check"), - StanzaPass("low-form-check"), - StanzaPass("check-init")//, - //ScalaPass(renamec) - )) - - val outfile = passes.foldLeft( input ) ( (infile, pass) => { + private def verilog(input: String, output: String)(implicit logger: Logger) { + val outfile = defaultPasses.foldLeft( input ) ( (infile, pass) => { val outfile = genTempFilename(output) - run(pass, infile, outfile) + pass.run(infile, outfile) outfile }) -- cgit v1.2.3 From 5869b8e201390b534b06b8960ab32351e51602c0 Mon Sep 17 00:00:00 2001 From: ducky Date: Sat, 16 Jan 2016 16:31:16 -0800 Subject: Import a logging library so we don't reinvent the wheel and have implicits flying around everywhere --- build.sbt | 2 ++ src/main/resources/logback.xml | 10 ++++++ src/main/scala/firrtl/DebugUtils.scala | 62 ++-------------------------------- src/main/scala/firrtl/Driver.scala | 55 ++++++++++++++---------------- src/main/scala/firrtl/Passes.scala | 45 ++++++++++++------------ src/main/scala/firrtl/Primops.scala | 10 +++--- 6 files changed, 69 insertions(+), 115 deletions(-) create mode 100644 src/main/resources/logback.xml diff --git a/build.sbt b/build.sbt index c758923f..59b06bf3 100644 --- a/build.sbt +++ b/build.sbt @@ -9,6 +9,8 @@ version := "0.1-SNAPSHOT" scalaVersion := "2.11.4" libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value +libraryDependencies += "com.typesafe.scala-logging" %% "scala-logging" % "3.1.0" +libraryDependencies += "ch.qos.logback" % "logback-classic" % "1.1.2" // Assembly diff --git a/src/main/resources/logback.xml b/src/main/resources/logback.xml new file mode 100644 index 00000000..a6bab96e --- /dev/null +++ b/src/main/resources/logback.xml @@ -0,0 +1,10 @@ + + + + [%-4level] %msg%n + + + + + + diff --git a/src/main/scala/firrtl/DebugUtils.scala b/src/main/scala/firrtl/DebugUtils.scala index e802d935..5d58fba6 100644 --- a/src/main/scala/firrtl/DebugUtils.scala +++ b/src/main/scala/firrtl/DebugUtils.scala @@ -2,7 +2,6 @@ package firrtl -import java.io.PrintWriter import Utils._ private object DebugUtils { @@ -63,67 +62,10 @@ private object DebugUtils { a.ports.foreach(_.preOrderTraversal(f)) a.stmt.preOrderTraversal(f) } - case a: Circuit => a.modules.foreach(_.preOrderTraversal(f)) + case a: Circuit => a.modules.foreach(_.preOrderTraversal(f)) //case _ => throw new Exception(s"Unsupported FIRRTL node ${ast.getClass.getSimpleName}!") - case _ => + case _ => } } } - - - /** Private class for recording and organizing debug information */ - class Logger private ( - writer: PrintWriter, - printMode: Symbol, - printVars: List[Symbol]){ - - // Legal printModes: 'none, 'error, 'warn, 'info, 'debug, 'trace - require(List('none, 'error, 'warn, 'info, 'debug, 'trace) contains printMode) - val errorEnable = List('error, 'warn, 'info, 'debug, 'trace) contains printMode - val warnEnable = List('warn, 'info, 'debug, 'trace) contains printMode - val infoEnable = List('info, 'debug, 'trace) contains printMode - val debugEnable = List('debug, 'trace) contains printMode - val traceEnable = List('trace) contains printMode - val circuitEnable = printVars contains 'circuit - val debugFlags = printVars.map(_ -> true).toMap.withDefaultValue(false) - - def println(message: => String){ - writer.println(message) - } - def error(message: => String){ - if (errorEnable) writer.println(message.split("\n").map("[error] " + _).mkString("\n")) - } - def warn(message: => String){ - if (warnEnable) writer.println(message.split("\n").map("[warn] " + _).mkString("\n")) - } - def info(message: => String){ - if (infoEnable) writer.println(message.split("\n").map("[info] " + _).mkString("\n")) - } - def debug(message: => String){ - if (debugEnable) writer.println(message.split("\n").map("[debug] " + _).mkString("\n")) - } - def trace(message: => String){ - if (traceEnable) writer.println(message.split("\n").map("[trace] " + _).mkString("\n")) - } - def printlnDebug(circuit: Circuit){ - if (circuitEnable) this.println(circuit.serialize(debugFlags)) - } - // Used if not autoflushing - def flush() = writer.flush() - - } - /** Factory object for logger - * - * Logger records and organizes debug information - */ - object Logger - { - def apply(writer: PrintWriter): Logger = - new Logger(writer, 'warn, List()) - def apply(writer: PrintWriter, printMode: Symbol): Logger = - new Logger(writer, printMode, List()) - def apply(writer: PrintWriter, printMode: Symbol, printVars: List[Symbol]): Logger = - new Logger(writer, printMode, printVars) - def apply(): Logger = new Logger(null, 'none, List()) - } } diff --git a/src/main/scala/firrtl/Driver.scala b/src/main/scala/firrtl/Driver.scala index 82eb3962..700ee936 100644 --- a/src/main/scala/firrtl/Driver.scala +++ b/src/main/scala/firrtl/Driver.scala @@ -1,30 +1,33 @@ package firrtl import java.io._ -import scala.sys.process._ import java.nio.file.{Paths, Files} + import scala.io.Source +import scala.sys.process._ + +import com.typesafe.scalalogging.LazyLogging + import Utils._ import DebugUtils._ import Passes._ - trait DriverPass { - def run(input: String, output: String)(implicit logger: Logger) : Unit + def run(input: String, output: String) : Unit } -case class StanzaPass(val passes : Seq[String]) extends DriverPass { - def run(input : String, output : String)(implicit logger : Logger) : Unit = { +case class StanzaPass(val passes : Seq[String]) extends DriverPass with LazyLogging { + def run(input : String, output : String): Unit = { val cmd = Seq("firrtl-stanza", "-i", input, "-o", output, "-b", "firrtl") ++ passes.flatMap(x=>Seq("-x", x)) - println(cmd.mkString(" ")) + logger.info(cmd.mkString(" ")) val ret = cmd.!! - println(ret) + logger.info(ret) } } -case class ScalaPass(val func : Circuit => Circuit) extends DriverPass { - def run(input : String, output : String)(implicit logger : Logger) : Unit = { +case class ScalaPass(val func : Circuit => Circuit) extends DriverPass with LazyLogging { + def run(input : String, output : String): Unit = { var ast = Parser.parse(input, Source.fromFile(input).getLines) val newast = func(ast) - println("Writing to " + output) + logger.info("Writing to " + output) val writer = new PrintWriter(new File(output)) writer.write(newast.serialize()) writer.close() @@ -53,8 +56,7 @@ object DriverPasses { } } -object Driver -{ +object Driver extends LazyLogging { private val usage = """ Usage: java -cp utils/bin/firrtl.jar firrtl.Driver [options] -i -o """ @@ -117,40 +119,34 @@ object Driver )) // Parse input file and print to output - private def firrtl(input: String, output: String)(implicit logger: Logger) + private def firrtl(input: String, output: String) { val ast = Parser.parse(input, Source.fromFile(input).getLines) val writer = new PrintWriter(new File(output)) writer.write(ast.serialize()) writer.close() - logger.printlnDebug(ast) + logger.debug(ast.toString) } - // Should we just remove logger? - private def executePassesWithLogger(ast: Circuit, passes: Seq[Circuit => Circuit])(implicit logger: Logger): Circuit = { + def executePasses(ast: Circuit, passes: Seq[Circuit => Circuit]): Circuit = { if (passes.isEmpty) ast else executePasses(passes.head(ast), passes.tail) } - def executePasses(ast: Circuit, passes: Seq[Circuit => Circuit]): Circuit = { - implicit val logger = Logger() // No logging - executePassesWithLogger(ast, passes) - } - - private def verilog(input: String, output: String)(implicit logger: Logger) { + private def verilog(input: String, output: String) { val outfile = defaultPasses.foldLeft( input ) ( (infile, pass) => { val outfile = genTempFilename(output) pass.run(infile, outfile) outfile }) - println(outfile) + logger.info(outfile) // finally, convert to verilog at the end val cmd = Seq("firrtl-stanza", "-i", outfile, "-o", output, "-X", "verilog") - println(cmd.mkString(" ")) + logger.info(cmd.mkString(" ")) val ret = cmd.!! - println(ret) + logger.info(ret) } def main(args: Array[String]) @@ -220,13 +216,14 @@ object Driver case s: String => nextPrintVar(List(), s.toList) case false => List() } - implicit val logger = options('log) match { + + /*implicit val logger = options('log) match { case s: String => Logger(new PrintWriter(new FileOutputStream(s)), debugMode, printVars) case false => Logger(new PrintWriter(System.err, true), debugMode, printVars) - } + }*/ // -p "printVars" options only print for debugMode > 'debug, warn if -p enabled and debugMode < 'debug - if( !logger.debugEnable && !printVars.isEmpty ) + if (!printVars.isEmpty) logger.warn("-p options will not print unless debugMode (-d) is debug or trace") options('compiler) match { @@ -236,7 +233,7 @@ object Driver } } - def time[R](str: String)(block: => R)(implicit logger: Logger): R = { + def time[R](str: String)(block: => R): R = { val t0 = System.currentTimeMillis() val result = block // call-by-name val t1 = System.currentTimeMillis() diff --git a/src/main/scala/firrtl/Passes.scala b/src/main/scala/firrtl/Passes.scala index 5aa74630..9469b6cb 100644 --- a/src/main/scala/firrtl/Passes.scala +++ b/src/main/scala/firrtl/Passes.scala @@ -1,11 +1,13 @@ package firrtl +import com.typesafe.scalalogging.LazyLogging + import Utils._ import DebugUtils._ import Primops._ -object Passes { +object Passes extends LazyLogging { // TODO Perhaps we should get rid of Logger since this map would be nice ////private val defaultLogger = Logger() @@ -13,7 +15,6 @@ object Passes { // "infer-types" -> inferTypes //) def nameToPass(name: String): Circuit => Circuit = { - implicit val logger = Logger() // throw logging away //mapNameToPass.getOrElse(name, throw new Exception("No Standard FIRRTL Pass of name " + name)) name match { case "infer-types" => inferTypes @@ -22,8 +23,8 @@ object Passes { } } - private def toField(p: Port)(implicit logger: Logger): Field = { - logger.trace(s"toField called on port ${p.serialize}") + private def toField(p: Port): Field = { + logger.debug(s"toField called on port ${p.serialize}") p.dir match { case Input => Field(p.name, Reverse, p.tpe) case Output => Field(p.name, Default, p.tpe) @@ -55,8 +56,8 @@ object Passes { } private def getVectorSubtype(t: Type): Type = t.getType // Added for clarity // TODO Add genders - private def inferExpTypes(typeMap: TypeMap)(exp: Exp)(implicit logger: Logger): Exp = { - logger.trace(s"inferTypes called on ${exp.getClass.getSimpleName}") + private def inferExpTypes(typeMap: TypeMap)(exp: Exp): Exp = { + logger.debug(s"inferTypes called on ${exp.getClass.getSimpleName}") exp.map(inferExpTypes(typeMap)) match { case e: UIntValue => e case e: SIntValue => e @@ -67,8 +68,8 @@ object Passes { case e: Exp => e } } - private def inferTypes(typeMap: TypeMap, stmt: Stmt)(implicit logger: Logger): (Stmt, TypeMap) = { - logger.trace(s"inferTypes called on ${stmt.getClass.getSimpleName} ") + private def inferTypes(typeMap: TypeMap, stmt: Stmt): (Stmt, TypeMap) = { + logger.debug(s"inferTypes called on ${stmt.getClass.getSimpleName} ") stmt.map(inferExpTypes(typeMap)) match { case b: Block => { var tMap = typeMap @@ -95,15 +96,15 @@ object Passes { case s: Stmt => (s, typeMap) } } - private def inferTypes(typeMap: TypeMap, m: Module)(implicit logger: Logger): Module = { - logger.trace(s"inferTypes called on module ${m.name}") + private def inferTypes(typeMap: TypeMap, m: Module): Module = { + logger.debug(s"inferTypes called on module ${m.name}") val pTypeMap = m.ports.map( p => p.name -> p.tpe ).toMap Module(m.info, m.name, m.ports, inferTypes(typeMap ++ pTypeMap, m.stmt)._1) } - def inferTypes(c: Circuit)(implicit logger: Logger): Circuit = { - logger.trace(s"inferTypes called on circuit ${c.name}") + def inferTypes(c: Circuit): Circuit = { + logger.debug(s"inferTypes called on circuit ${c.name}") // initialize typeMap with each module of circuit mapped to their bundled IO (ports converted to fields) val typeMap = c.modules.map(m => m.name -> BundleType(m.ports.map(toField(_)))).toMap @@ -115,8 +116,8 @@ object Passes { def renameall(s : String)(implicit map : Map[String,String]) : String = map getOrElse (s, s) - def renameall(e : Exp)(implicit logger : Logger, map : Map[String,String]) : Exp = { - logger.trace(s"renameall called on expression ${e.toString}") + def renameall(e : Exp)(implicit map : Map[String,String]) : Exp = { + logger.debug(s"renameall called on expression ${e.toString}") e match { case p : Ref => Ref(renameall(p.name), p.tpe) @@ -131,8 +132,8 @@ object Passes { } } - def renameall(s : Stmt)(implicit logger : Logger, map : Map[String,String]) : Stmt = { - logger.trace(s"renameall called on statement ${s.toString}") + def renameall(s : Stmt)(implicit map : Map[String,String]) : Stmt = { + logger.debug(s"renameall called on statement ${s.toString}") s match { case p : DefWire => @@ -165,20 +166,20 @@ object Passes { } } - def renameall(p : Port)(implicit logger : Logger, map : Map[String,String]) : Port = { - logger.trace(s"renameall called on port ${p.name}") + def renameall(p : Port)(implicit map : Map[String,String]) : Port = { + logger.debug(s"renameall called on port ${p.name}") Port(p.info, renameall(p.name), p.dir, p.tpe) } - def renameall(m : Module)(implicit logger : Logger, map : Map[String,String]) : Module = { - logger.trace(s"renameall called on module ${m.name}") + def renameall(m : Module)(implicit map : Map[String,String]) : Module = { + logger.debug(s"renameall called on module ${m.name}") Module(m.info, renameall(m.name), m.ports.map(renameall(_)), renameall(m.stmt)) } - def renameall(map : Map[String,String])(implicit logger : Logger) : Circuit => Circuit = { + def renameall(map : Map[String,String]) : Circuit => Circuit = { c => { implicit val imap = map - logger.trace(s"renameall called on circuit ${c.name} with %{renameto}") + logger.debug(s"renameall called on circuit ${c.name} with %{renameto}") Circuit(c.info, renameall(c.name), c.modules.map(renameall(_))) } } diff --git a/src/main/scala/firrtl/Primops.scala b/src/main/scala/firrtl/Primops.scala index 1840b190..59a6c1ff 100644 --- a/src/main/scala/firrtl/Primops.scala +++ b/src/main/scala/firrtl/Primops.scala @@ -1,10 +1,12 @@ package firrtl +import com.typesafe.scalalogging.LazyLogging + import Utils._ import DebugUtils._ -object Primops { +object Primops extends LazyLogging { private val mapPrimop2String = Map[Primop, String]( Add -> "add", @@ -53,7 +55,7 @@ object Primops { } // Borrowed from Stanza implementation - def lowerAndTypePrimop(e: DoPrimop)(implicit logger: Logger): DoPrimop = { + def lowerAndTypePrimop(e: DoPrimop): DoPrimop = { def uAnd(op1: Exp, op2: Exp): Type = { (op1.getType, op2.getType) match { case (t1: UIntType, t2: UIntType) => UIntType(UnknownWidth) @@ -69,7 +71,7 @@ object Primops { case _ => UnknownType } } - + logger.debug(s"lowerAndTypePrimop on ${e.op.getClass.getSimpleName}") val tpe = e.op match { case Add => uAnd(e.args(0), e.args(1)) @@ -109,7 +111,7 @@ object Primops { case Cat => UIntType(UnknownWidth) case Bit => UIntType(UnknownWidth) case Bits => UIntType(UnknownWidth) - case _ => ??? + case _ => ??? } DoPrimop(e.op, e.args, e.consts, tpe) } -- cgit v1.2.3 From 11a7318275a4da11ef64c302e958b27a04e42a25 Mon Sep 17 00:00:00 2001 From: ducky Date: Sat, 16 Jan 2016 16:32:16 -0800 Subject: Ignore eclipse .project --- .gitignore | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.gitignore b/.gitignore index 899e81f0..2c59432c 100644 --- a/.gitignore +++ b/.gitignore @@ -26,6 +26,7 @@ utils/bin/firrtl utils/bin/stanza utils/bin/firrtl-scala utils/bin/firrtl-stanza +utils/bin/firrtl.jar utils/bin/FileCheck spec/spec.aux spec/spec.log @@ -34,6 +35,8 @@ spec/spec.out spec/spec.synctex.gz notes/*.docx +.project + # sbt specific .cache .history -- cgit v1.2.3 From 1f3b2b10e1fd63f28ba2e2f3fbfb885f5476a253 Mon Sep 17 00:00:00 2001 From: ducky Date: Sat, 16 Jan 2016 16:39:42 -0800 Subject: Clean up old logging remnants --- src/main/scala/firrtl/Driver.scala | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/main/scala/firrtl/Driver.scala b/src/main/scala/firrtl/Driver.scala index 700ee936..7cbd63d4 100644 --- a/src/main/scala/firrtl/Driver.scala +++ b/src/main/scala/firrtl/Driver.scala @@ -217,14 +217,8 @@ object Driver extends LazyLogging { case false => List() } - /*implicit val logger = options('log) match { - case s: String => Logger(new PrintWriter(new FileOutputStream(s)), debugMode, printVars) - case false => Logger(new PrintWriter(System.err, true), debugMode, printVars) - }*/ - - // -p "printVars" options only print for debugMode > 'debug, warn if -p enabled and debugMode < 'debug - if (!printVars.isEmpty) - logger.warn("-p options will not print unless debugMode (-d) is debug or trace") + if (!logger.underlying.isDebugEnabled && !printVars.isEmpty ) + logger.warn("-p options will only print at DEBUG log level") options('compiler) match { case "verilog" => verilog(input, output) -- cgit v1.2.3 From cbe579b3f6676638dbc078e606be90ca895977bc Mon Sep 17 00:00:00 2001 From: ducky Date: Sat, 16 Jan 2016 16:44:01 -0800 Subject: Add warning that -p unused --- src/main/scala/firrtl/Driver.scala | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/src/main/scala/firrtl/Driver.scala b/src/main/scala/firrtl/Driver.scala index 7cbd63d4..34a69110 100644 --- a/src/main/scala/firrtl/Driver.scala +++ b/src/main/scala/firrtl/Driver.scala @@ -170,7 +170,7 @@ object Driver extends LazyLogging { case 'T' :: tail => nextPrintVar(syms ++ List('twidths), tail) case 'g' :: tail => nextPrintVar(syms ++ List('genders), tail) case 'c' :: tail => nextPrintVar(syms ++ List('circuit), tail) - case 'd' :: tail => nextPrintVar(syms ++ List('debug), tail) // Currently ignored + case 'd' :: tail => nextPrintVar(syms ++ List('debug), tail) case 'i' :: tail => nextPrintVar(syms ++ List('info), tail) case char :: tail => throw new Exception("Unknown print option " + char) } @@ -180,10 +180,6 @@ object Driver extends LazyLogging { case Nil => map case "-X" :: value :: tail => nextOption(map ++ Map('compiler -> value), tail) - case "-d" :: value :: tail => - nextOption(map ++ Map('debugMode -> value), tail) - case "-l" :: value :: tail => - nextOption(map ++ Map('log -> value), tail) case "-p" :: value :: tail => nextOption(map ++ Map('printVars -> value), tail) case "-i" :: value :: tail => @@ -211,14 +207,17 @@ object Driver extends LazyLogging { case s: String => s case false => throw new Exception("No output file provided!" + usage) } - val debugMode = decodeDebugMode(options('debugMode)) val printVars = options('printVars) match { case s: String => nextPrintVar(List(), s.toList) case false => List() } - if (!logger.underlying.isDebugEnabled && !printVars.isEmpty ) - logger.warn("-p options will only print at DEBUG log level") + if (!printVars.isEmpty) { + logger.warn("-p options currently ignored") + if (!logger.underlying.isDebugEnabled) { + logger.warn("-p options will only print at DEBUG log level, logging configuration can be edited in src/main/resources/logback.xml") + } + } options('compiler) match { case "verilog" => verilog(input, output) -- cgit v1.2.3