From 7992c5f7725bcbf00c1130c50719711b19dc9818 Mon Sep 17 00:00:00 2001 From: azidar Date: Wed, 29 Apr 2015 15:41:57 -0700 Subject: Fixed bug in lowering of subfields. Fixed ModuleVec.fir to be correct --- src/main/stanza/passes.stanza | 33 +++++++++++++++------------------ test/chisel3/ModuleVec.fir | 24 ++++++++++++------------ 2 files changed, 27 insertions(+), 30 deletions(-) diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 0b586080..453a8181 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -712,12 +712,17 @@ defn expand-expr (e:Expression) -> List : for x in generate-entry(name(f),type(f)) map : EF(WSubfield(i,name(x),type(x),gender(e)),flip(x)) else : - val b = exp(e) - val exps = for x in generate-entry(name(b as WRef),type(b)) map : - EF(WRef(name(x),type(x),NodeKind(),gender(e)),DEFAULT) - val begin = index-of-elem(type(b) as BundleType,name(e)) + val exps = expand-expr(exp(e)) + val begin = index-of-elem(type(exp(e)) as BundleType,name(e)) val len = num-elems(type(e)) - headn(tailn(exps,begin),len) + val ret = headn(tailn(exps,begin),len) + for r in ret map : EF(exp(r),DEFAULT) + ;val b = exp(e) + ;val exps = for x in generate-entry(name(b as WRef),type(b)) map : + ;EF(WRef(name(x),type(x),NodeKind(),gender(e)),DEFAULT) + ;val begin = index-of-elem(type(b) as BundleType,name(e)) + ;val len = num-elems(type(e)) + ;headn(tailn(exps,begin),len) (e:WIndex) : val exps = expand-expr(exp(e)) val len = num-elems(type(e)) @@ -740,6 +745,11 @@ defn size (s:DefMemory) -> Int : size(type(s)) defn size (s:WDefAccessor) -> Int : size(type(source(s)) as VectorType) defn kind (e:WSubfield) -> Kind : kind(exp(e) as WRef|WSubfield|WIndex) defn kind (e:WIndex) -> Kind : kind(exp(e) as WRef|WSubfield|WIndex) +defn base-name (e:Expression) -> Symbol : + match(e) : + (e:WRef) : name(e) + (e:WSubfield) : base-name(exp(e)) + (e:WIndex) : base-name(exp(e)) defn set-gender (e:Expression,g:Gender,f:Flip) -> Expression : match(e) : @@ -749,18 +759,6 @@ defn set-gender (e:Expression,g:Gender,f:Flip) -> Expression : defn lower (body:Stmt) -> Stmt : defn lower-stmt (s:Stmt) -> Stmt : - defn calc-gender (g:Gender, e:Expression) -> Gender : - match(e) : - (e:WRef) : gender(e) - (e:WSubfield) : - println-all-debug(["Calc gender. " g " with " e]) - println-all-debug(["Exp: " exp(e)]) - val flip = bundle-field-flip(name(e),type(exp(e))) - println-all-debug(["Flip: " flip]) - calc-gender(flip * g,exp(e)) - (e:WIndex) : gender(e) - (e) : g - println(s) match(s) : (s:DefWire) : Begin $ @@ -1974,5 +1972,4 @@ public defn run-passes (c: Circuit, p: List,file:String) : if contains(p,'X') or contains(p,'n') : do-stage("Split Expressions", split-exp) if contains(p,'X') or contains(p,'o') : do-stage("Real IR", to-real-ir) if contains(p,'X') or contains(p,'F') : do-stage("To Flo", emit-flo{file,_}) - println("Done!") diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir index 7379024b..a4617267 100644 --- a/test/chisel3/ModuleVec.fir +++ b/test/chisel3/ModuleVec.fir @@ -6,25 +6,25 @@ circuit ModuleVec : output out : UInt<32> node T_33 = UInt<1>(1) - node T_34 = add(in, T_33) - out := T_34 + node T_34 = add-wrap(Pad(in,?), Pad(T_33,?)) + out := Pad(T_34,?) module PlusOne_25 : input in : UInt<32> output out : UInt<32> node T_35 = UInt<1>(1) - node T_36 = add(in, T_35) - out := T_36 + node T_36 = add-wrap(Pad(in,?), Pad(T_35,?)) + out := Pad(T_36,?) module ModuleVec : - output ins : UInt<32>[2] + input ins : UInt<32>[2] output outs : UInt<32>[2] inst T_37 of PlusOne inst T_38 of PlusOne_25 - wire pluses : {flip in : UInt<32>, out : UInt<32>}[2] - pluses[0] := T_37 - pluses[1] := T_38 - pluses.s.in := ins.s - outs[0] := pluses.s.out - pluses.s.in := ins[1] - outs[1] := pluses[1].out + wire pluses : { in : UInt<32>, flip out : UInt<32>}[2] + pluses[0] := Pad(T_37,?) + pluses[1] := Pad(T_38,?) + pluses[0].in := Pad(ins[0],?) + outs[0] := Pad(pluses[0].out,?) + pluses[1].in := Pad(ins[1],?) + outs[1] := Pad(pluses[1].out,?) -- cgit v1.2.3 From 7c0d0af5b91fcdc2a0cf9619b76be5529968487d Mon Sep 17 00:00:00 2001 From: azidar Date: Wed, 29 Apr 2015 16:16:33 -0700 Subject: Made temp name generation counter, as well as the name, based off the eventual named assignment. Should be very clear what caused the generation of the temp, and the numbering is based off of that cause, not a global counter --- TODO | 3 +-- src/main/stanza/passes.stanza | 27 ++++++++++++++++++++------- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/TODO b/TODO index f4a25827..f7863055 100644 --- a/TODO +++ b/TODO @@ -3,8 +3,8 @@ ================================================ ======== Current Tasks ======== -<> Update spec +<> Add Unit Tests for each pass ======== Update Core ========== @@ -58,7 +58,6 @@ Patrick: <> subword accesses verilog style guide -naming for split nodes annotation system zero-width wires expanding mems (consider changing defmem to be size, and element type) diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 453a8181..39795a62 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -141,6 +141,18 @@ defmethod print (o:OutputStream, g:Gender) : defmethod type (exp:UIntValue) -> Type : UIntType(width(exp)) defmethod type (exp:SIntValue) -> Type : SIntType(width(exp)) +;============== GENSYM STUFF ====================== + +val sym-hash = HashTable(symbol-hash) +defn firrtl-gensym (s:Symbol) -> Symbol : + val cur = get?(sym-hash,s,0) + val nxt = cur + 1 + sym-hash[s] = nxt + symbol-join([s cur]) + +defn firrtl-gensym () -> Symbol : + firrtl-gensym(`gen) + ;============== DEBUG STUFF ============================= public var PRINT-TYPES : True|False = false public var PRINT-KINDS : True|False = false @@ -251,7 +263,7 @@ defmethod map (f: Type -> Type, e: WSubfield) : defmethod map (f: Type -> Type, e: WIndex) : WIndex(exp(e), value(e), f(type(e)), gender(e)) -;================= Temparary Variable Elimination ======================== +;================= Temporary Variable Elimination ======================== ; Returns a new Circuit where temporary variables are removed and returns ; the resulting nested expression @@ -1538,14 +1550,14 @@ defn gen-constraints (m:Module, h:HashTable, v:Vector) -> Mod (e:UIntValue) : match(width(e)) : (w:UnknownWidth) : - val w* = VarWidth(gensym(`w)) + val w* = VarWidth(firrtl-gensym(`w)) add(v,WGeq(w*,IntWidth(ceil-log2(value(e))))) UIntValue(value(e),w*) (w) : e (e:SIntValue) : match(width(e)) : (w:UnknownWidth) : - val w* = VarWidth(gensym(`w)) + val w* = VarWidth(firrtl-gensym(`w)) add(v,WGeq(w*,IntWidth(1 + ceil-log2(abs(value(e)))))) SIntValue(value(e),w*) (w) : e @@ -1590,7 +1602,7 @@ defn replace-var-widths (c:Circuit,h:HashTable) -> Circuit : defn remove-unknowns-w (w:Width) -> Width : match(w) : - (w:UnknownWidth) : VarWidth(gensym(`w)) + (w:UnknownWidth) : VarWidth(firrtl-gensym(`w)) (w) : w defn remove-unknowns (t:Type) -> Type : mapr(remove-unknowns-w,t) @@ -1700,8 +1712,9 @@ defn split-exp (c:Circuit) : match(map(split-exp-e{_,v,n},e)): (e:Subfield|DoPrim|Pad|ReadPort|Register|WritePort) : val n* = - if n typeof False : gensym(`T) - else : to-symbol $ string-join $ [n as Symbol gensym(`#)] + if n typeof False : firrtl-gensym(`T) + else : firrtl-gensym(symbol-join([n as Symbol `#])) + ;to-symbol $ string-join $ [n as Symbol firrtl-gensym(`#)] add(v,DefNode(n*,e)) WRef(n*,type(e),NodeKind(),UNKNOWN-GENDER) (e) : e @@ -1914,7 +1927,7 @@ defn emit-s (s:Stmt, v:List, top:Symbol) : (s:DefNode) : if value(s) typeof WritePort : val e = value(s) as WritePort - val n = gensym(`F) + val n = firrtl-gensym(`F) emit-all([top "::" n " = wr'" prim-width(type(e)) " " enable(e) " " mem(e) " " index(e) " " name(s) "\n"], top) else : emit-all([top "::" name(s) " = " maybe-mov(value(s)) value(s) "\n"], top) -- cgit v1.2.3 From 0608bfbe363780132c0baf1e7098013ab4352f34 Mon Sep 17 00:00:00 2001 From: azidar Date: Wed, 29 Apr 2015 19:23:03 -0700 Subject: Fixed bug where a node's width was not equal to its value's --- src/main/stanza/passes.stanza | 7 +++- test/passes/jacktest/risc.fir | 80 ++++++++++++++++++------------------------- 2 files changed, 39 insertions(+), 48 deletions(-) diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 39795a62..5d2abb81 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -1520,7 +1520,12 @@ defn gen-constraints (m:Module, h:HashTable, v:Vector) -> Mod (s:DefWire) : DefWire(name(s),h[name(s)]) (s:DefInstance) : DefInstance(name(s),gen-constraints(module(s))) (s:DefMemory) : DefMemory(name(s),h[name(s)] as VectorType) - (s:DefNode) : DefNode(name(s),gen-constraints(value(s))) + (s:DefNode) : + val l = h[name(s)] + val r = gen-constraints(value(s)) + add(v,WGeq(width!(l),width!(type(r)))) + add(v,WGeq(width!(type(r)),width!(l))) + DefNode(name(s),r) (s:Connect) : val l = gen-constraints(loc(s)) val e = gen-constraints(exp(s)) diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir index bb1512d5..a73d57c4 100644 --- a/test/passes/jacktest/risc.fir +++ b/test/passes/jacktest/risc.fir @@ -1,5 +1,5 @@ ; RUN: firrtl -i %s -o %s.flo -x X -p cTwd | tee %s.out | FileCheck %s -; CHECK: Expand Whens +; CHECK: Done! circuit Risc : module Risc : @@ -12,59 +12,45 @@ circuit Risc : mem file : UInt<32>[256] mem code : UInt<32>[256] - node T_51 = UInt<8>(0) reg pc : UInt<8> - on-reset pc := T_51 - node add_op = UInt<1>(0) - node imm_op = UInt<1>(1) + on-reset pc := Pad(UInt<8>(0),?) accessor inst = code[pc] node op = bits(inst, 31, 24) node rci = bits(inst, 23, 16) node rai = bits(inst, 15, 8) node rbi = bits(inst, 7, 0) - node T_52 = UInt<1>(0) - node T_53 = eq(rai, T_52) - node T_54 = UInt<1>(0) - accessor T_55 = file[rai] - node ra = mux(T_53, T_54, T_55) - node T_56 = UInt<1>(0) - node T_57 = eq(rbi, T_56) - node T_58 = UInt<1>(0) - accessor T_59 = file[rbi] - node rb = mux(T_57, T_58, T_59) + node T_51 = eq(Pad(rai,?), Pad(UInt<1>(0),?)) + accessor T_52 = file[rai] + node ra = mux(Pad(T_51,?), Pad(UInt<1>(0),?), Pad(T_52,?)) + node T_53 = eq(Pad(rbi,?), Pad(UInt<1>(0),?)) + accessor T_54 = file[rbi] + node rb = mux(Pad(T_53,?), Pad(UInt<1>(0),?), Pad(T_54,?)) wire rc : UInt<32> - node T_60 = UInt<1>(0) - valid := T_60 - node T_61 = UInt<1>(0) - out := T_61 - node T_62 = UInt<1>(0) - rc := T_62 + node T_55 = UInt<1>(0) + valid := Pad(T_55,?) + out := Pad(UInt<1>(0),?) + rc := Pad(UInt<1>(0),?) when isWr : - accessor T_63 = code[wrAddr] - T_63 := wrData - else : when boot : - node T_64 = UInt<1>(0) - pc := T_64 + accessor T_56 = code[wrAddr] + T_56 := Pad(wrData,?) + else : when boot : pc := Pad(UInt<1>(0),?) else : - node T_65 = eq(add_op, op) - when T_65 : - node T_66 = add-wrap(ra, rb) - rc := T_66 - node T_67 = eq(imm_op, op) - when T_67 : - node T_68 = shl(rai, 8) - node T_69 = bit-or(T_68, rbi) - rc := T_69 - out := rc - node T_70 = UInt<8>(255) - node T_71 = eq(rci, T_70) - when T_71 : - node T_72 = UInt<1>(1) - valid := T_72 + node T_57 = eq(Pad(UInt<1>(0),?), Pad(op,?)) + when T_57 : + node T_58 = add-wrap(Pad(ra,?), Pad(rb,?)) + rc := Pad(T_58,?) + node T_59 = eq(Pad(UInt<1>(1),?), Pad(op,?)) + when T_59 : + node T_60 = shl(rai, 8) + node T_61 = bit-or(Pad(T_60,?), Pad(rbi,?)) + rc := Pad(T_61,?) + out := Pad(rc,?) + node T_62 = eq(Pad(rci,?), Pad(UInt<8>(255),?)) + when T_62 : + node T_63 = UInt<1>(1) + valid := Pad(T_63,?) else : - accessor T_73 = file[rci] - T_73 := rc - node T_74 = UInt<1>(1) - node T_75 = add-wrap(pc, T_74) - pc := T_75 -; CHECK: Finished Expand Whens + accessor T_64 = file[rci] + T_64 := Pad(rc,?) + node T_65 = add-wrap(Pad(pc,?), Pad(UInt<1>(1),?)) + pc := Pad(T_65,?) -- cgit v1.2.3