From 00e736fb1dffd7fa1cd9986dbfb3dcdb4b273fbc Mon Sep 17 00:00:00 2001
From: Schuyler Eldridge
Date: Wed, 12 Feb 2020 16:52:35 -0500
Subject: Add test of RenameMap self-renaming

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
---
 src/test/scala/firrtlTests/RenameMapSpec.scala | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/test/scala/firrtlTests/RenameMapSpec.scala b/src/test/scala/firrtlTests/RenameMapSpec.scala
index 2da10b7f..bbe0255f 100644
--- a/src/test/scala/firrtlTests/RenameMapSpec.scala
+++ b/src/test/scala/firrtlTests/RenameMapSpec.scala
@@ -752,4 +752,18 @@ class RenameMapSpec extends FirrtlFlatSpec {
       Some(Seq(bar2))
     }
   }
+
+  it should "record a self-rename" in {
+    val top = CircuitTarget("Top").module("Top")
+    val foo = top.instOf("foo", "Mod")
+    val bar = top.instOf("bar", "Mod")
+
+    val r = RenameMap()
+
+    r.record(foo, bar)
+    r.record(foo, foo)
+
+    r.get(foo) should not be (empty)
+    r.get(foo).get should contain allOf (foo, bar)
+  }
 }
-- 
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