From efdefde2a5fa13de8faa8c141f852391909225df Mon Sep 17 00:00:00 2001
From: Carlos Eduardo
Date: Tue, 9 Mar 2021 15:49:37 -0300
Subject: Create annotation to allow inline readmem in Verilog (#2107)

This PR adds a new annotation allowing inline loading for memory files
in Verilog code.---
 .gitignore | 1 +
 1 file changed, 1 insertion(+)

(limited to '.gitignore')

diff --git a/.gitignore b/.gitignore
index 8b3d51a6..dd2f998b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -66,3 +66,4 @@ project/metals.sbt
 
 *~
 *#*#
+.vscode
-- 
cgit v1.2.3