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2016-01-28Fixed bug where subaccess indexes were being classified as female,azidar
mucking up the chirrtl->firrtl transform. #56.
2016-01-28Changed rmode to wmodeazidar
2016-01-28Use IsInvalid instead of Poisons in chirrtl -> firrtl transformazidar
2016-01-28Added tests for previous commitazidar
2016-01-28Added addw to working ir as an optimized verilog emissionazidar
2016-01-28Fixed bug and updated test for changing mod to remazidar
2016-01-28Updated all tests to passazidar
2016-01-28Changed register syntax for optional reset and init valuesazidar
2016-01-27Reworked readwriter typesazidar
2016-01-27Fixed additional tests and inferring rdwr ports in chirrtljackkoenig
2016-01-25Fixed bug where poisons were not being declaredazidar
2016-01-25Added verilog rename passazidar
2016-01-25Added isinvalid and validifazidar
2016-01-25Fixed support for muxes and nodes with passive aggregate typesazidar
2016-01-25Fixed one more testazidar
2016-01-25Changed tests to pass with change to postfix of generated nameazidar
2016-01-24Fixed tests that broke from changing verilog backend and removing mask from ↵azidar
write mport declaration
2016-01-24Added muxing on passive aggregate typesazidar
2016-01-24Added DefMemory to CInfer Typesazidar
2016-01-23Fixed bug where the write mask wasn't being generated correctlyazidar
2016-01-23Added inference to mportsazidar
2016-01-23Added prefix checker, now compliant with firrtl specazidar
2016-01-23Changed chirrtl to not require known mask valuesazidar
2016-01-17Fixed error where memory of size 1 would create an index of size 0. This can ↵azidar
be fixed in the future with a pass that removes these memories
2016-01-17Added check for uint on access index typeazidar
2016-01-17BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed testsazidar
2016-01-16Added a bunch of tests and added firrtl-stanza and firrtl-scala to .gitignoreazidar
2016-01-16Fixed all tests so they either pass are marked as expected failuresazidar
2016-01-16Updated passes so they test new-memazidar
2016-01-16Fixed a testazidar
2016-01-16Fixed Vector performance testsazidar
2016-01-16Finished first cut at new firrtl - time for testing! Chirrtl requires masks ↵azidar
to be specified with write and rdwr mports
2016-01-16Fixed a bunch of tests, and minor bugsazidar
2016-01-16Added src and test filesazidar
2016-01-16WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit ↵azidar
roadblock in assigning clocked ports
2016-01-16WIP getting through testsazidar
2016-01-16Finished supporting nested accesses. Required some nuianced thinking. Pass ↵azidar
all feature tests. Deleted CondRead because it tested a problem we don't have any more
2016-01-16WIP, hit semantic bug in WSubAccessazidar
2016-01-16New memory works with verilog. Slowly changing tests and fixing bugs.azidar
Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
2016-01-16WIP. Compiles and almost done with verilog backend. Need to think about ↵azidar
emitting ports (and the assignments to them)
2016-01-16WIPazidar
2016-01-16WIP need to correctly output readwrite portsazidar
2016-01-16Added performance testsazidar
2016-01-16Fixed inline-indexers bug where genders weren't properly calculated inazidar
Lower Types pass. #53
2016-01-16Finished adding clocks to Stop and Printazidar
2015-11-02Deleted extranous passes.stanza comments, updated standard passes. Added ↵jackkoenig
support for -b <backend> flag without any other specified passes in stanza, updated parser tests to work with stanza implementation.
2015-10-19Merge pull request #47 from jackkoenig/masterAdam Izraelevitz
Updated Scala FIRRTL with Testing and Infer-Types Pass
2015-10-14Modified getType to return Type rather than Option[Type] which makes more ↵Jack
sense for some applications, also fixed up printing to better match stanza implementation
2015-10-14Moved Logger to new private object DebugUtils, changed UInt/SInt value ↵Jack
printing to match stanza implementation
2015-10-12Added support for no width to mean unknown, and print nothing instead of <?> ↵Jack
for unknown width. Also added test to check this
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