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Change of FIRRTL semantics!
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Fix init accessor
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Assignments to a register are no longer affected by enclosing when
statements:
when p :
reg r : UInt,clk,reset
r := a
will lower to:
reg r : UInt,clk,reset
r := a
instead of:
reg r : UInt,clk,reset
when p : r := a
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StandardVerilogCompiler
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particular directory structure.
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catching of initialization of accessors. Missing use case of accessing an accessor. Still need to update tests to pass
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enable with muxing the index with poison bits
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conditional assignment
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now be small examples, categorized by either passes, errors, or features.
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Updated tests to match. #29.
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extract, not >>
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an optimization that eliminated some when statements.
Added test case.
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invalid <> assignments.
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indexed. Fixed various broken tests.
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tests. Made more tests pass
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width error
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