| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-06-03 | Fixed verilog backend bugs. Passes ALU. Fails Datapath | azidar | |
| 2015-06-02 | Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ↵ | azidar | |
| low-firrtl syntax. Generates verilog that compiles, but is not correct | |||
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. ↵ | azidar | |
| Added Long support so UInt(LARGENUMBER) works | |||
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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