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2015-05-27Added sequential memories. mem no longer exists, must declare either cmem or ...azidar
2015-05-27Added external modules. Switched lower firrtl back to wire r; r := Register, ...azidar
2015-05-26Added <>. Added additional checks for primops. Added new chisel3 files.azidar
2015-05-20Added Pad pass to flo.stanza, which pads widths to make := and primops strict...azidar
2015-05-19Updated testsazidar
2015-05-18First pass at a Verilog Backend. Not tested, but compiles and generates reaso...azidar
2015-05-18Big API Change. Pad is no longer supported. Widths of primops can be flexible...azidar
2015-05-15Updated firrtl for its passes to be a bit more modular, and to enable pluggin...azidar
2015-05-13Added source indicators from FIRRTL files. Pass in -p i to get them printed. ...azidar
2015-05-13Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bugazidar
2015-05-02Now when expanding ConnectFrom/ToIndex, create a node for the index so it isn...azidar
2015-05-01Bug fix. ExpWidth was improperly evaluated during simplify (not subtracting one)azidar
2015-04-30Fixed assignment to outputs not getting emitted from Expand When passazidar
2015-04-29Fixed bug where a node's width was not equal to its value'sazidar
2015-04-29Added dshl and dshrazidar
2015-04-28Instances are now male. Reworked lowering pass to be sane. chisel3/ModuleVec....azidar
2015-04-27Added on-resetazidar
2015-04-24Merge branch 'master' of github.com:ucb-bar/firrtl into parserazidar
2015-04-24Fixed width inference bug where later constraints on the output width were no...azidar
2015-04-24Fixed performance bug in expand-when where equality between the consequence a...azidar
2015-04-23Fixed bug in lowering where the arguments to DoPrim and Pad weren't loweredazidar
2015-04-23Not finished commmitazidar
2015-04-23Added new parser. Fixed all Tests. Added on-reset to parser, but don't correc...azidar
2015-04-23Fixed Pad inference bugazidar
2015-04-22Switched to stricter primop width constraints. Implemented Pad. Added some mi...azidar
2015-04-21Reordered resolve-kinds and make-explicit-reset to fix bug where reset, if re...azidar
2015-04-20Fixed tests to use new execution arguments. Added and fixed chisel3 bugsazidar
2015-04-17Removed excessive debug print statements, added default call to firrtl to gen...azidar
2015-04-17Added temp elimination passazidar
2015-04-17Fixed bug in primop lowering during type inference. Added reduce instructions...azidar
2015-04-16Merged with new stanzaazidar
2015-04-15Finished flo backend. Restructured todo listazidar
2015-04-14Finished Split Expressionsazidar
2015-04-14Finished inlining passazidar
2015-04-13Stanza bugazidar
2015-04-10Almost finished width inference, takes too long/infinite loop for gcdazidar
2015-04-10Updated StanzaPatrick Li
2015-04-09Added more 'fake' tests. infer-widths now collects constraintsazidar
2015-04-08Added test to show correctness of gender inference and loweringazidar
2015-04-08Fixed bug in lowering that incorrectly determined genders when subfieldedazidar
2015-04-08Finished expand whens. started infer widths. added pdf for people to viewazidar
2015-03-27Corrected register init by adding initialization of registers pass after lowe...azidar
2015-03-25Finished expand-whens. Removed letrec also, a while agoazidar
2015-03-25Correctly do when expansion, minus enables and outputting lowered formazidar
2015-03-23Finished first two parts of expand-whens pass. Fixed inits by adding WRegInit...azidar
2015-03-18Finished expand accessors and lower to groundazidar
2015-03-12Switched bundles from gender to flipazidar
2015-03-11Finished expand accessors pass. Fixed bug in resolve-gender. Added tests, all...azidar
2015-03-10Finished resolve gendersazidar
2015-03-05Finished part of infer gender, tests not committedazidar