sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2016-01-16	WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl...	azidar
2016-01-16	WIP. Compiles and almost done with verilog backend. Need to think about emitt...	azidar
2016-01-16	WIP	azidar
2016-01-16	WIP need to correctly output readwrite ports	azidar
2015-08-28	Moved check type and check kind after check gender	azidar
2015-08-19	Fixed width inference bug where constraints were propagating backwards.	azidar
2015-08-17	Added tests for shl and mem. Fixed bug in verilog output of mem size.	azidar
2015-07-31	Updated tests to pipe from stderr to stdout	azidar
2015-07-14	Added tests for clocks. Added remove scope and special chars passes. Added te...	azidar
2015-06-12	Major revisions to spec. Bumped to v0.1.2	azidar
2015-05-18	First pass at a Verilog Backend. Not tested, but compiles and generates reaso...	azidar