| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-01-16 | WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit ↵ | azidar | |
| roadblock in assigning clocked ports | |||
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar | |
| Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables | |||
| 2015-09-30 | Fixed naming bug where __1 was matching. Caused lots o issues. | azidar | |
| 2015-08-25 | Fixed bug in split expression that leaked connect statements out of a ↵ | azidar | |
| conditional assignment | |||
 |
index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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