| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-01-16 | WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit ↵ | azidar | |
| roadblock in assigning clocked ports | |||
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar | |
| Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables | |||
| 2015-08-25 | Fixed bug in split expression that leaked connect statements out of a ↵ | azidar | |
| conditional assignment | |||
| 2015-08-03 | Changed name mangling to use _ as a delin. Fixed bug in checking for | azidar | |
| invalid <> assignments. | |||
