| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-07-14 | Pass most tests. The ones that do not pass are not expected to, yet | azidar |
| 2015-05-18 | First pass at a Verilog Backend. Not tested, but compiles and generates reaso... | azidar |
| 2015-05-18 | Big API Change. Pad is no longer supported. Widths of primops can be flexible... | azidar |
| 2015-04-28 | Instances are now male. Reworked lowering pass to be sane. chisel3/ModuleVec.... | azidar |
| 2015-04-23 | Added new parser. Fixed all Tests. Added on-reset to parser, but don't correc... | azidar |
| 2015-04-20 | Fixed tests to use new execution arguments. Added and fixed chisel3 bugs | azidar |
| 2015-03-10 | Finished resolve genders | azidar |
 |
index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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