sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2015-05-27	Added sequential memories. mem no longer exists, must declare either cmem or ...	azidar
2015-05-27	Added external modules. Switched lower firrtl back to wire r; r := Register, ...	azidar
2015-05-26	Added <>. Added additional checks for primops. Added new chisel3 files.	azidar
2015-05-19	Updated tests	azidar
2015-05-15	Updated firrtl for its passes to be a bit more modular, and to enable pluggin...	azidar
2015-05-13	Added source indicators from FIRRTL files. Pass in -p i to get them printed. ...	azidar
2015-04-30	Fixed assignment to outputs not getting emitted from Expand When pass	azidar
2015-04-29	Fixed bug where a node's width was not equal to its value's	azidar
2015-04-27	Added on-reset	azidar
2015-04-24	Merge branch 'master' of github.com:ucb-bar/firrtl into parser	azidar
2015-04-24	Fixed width inference bug where later constraints on the output width were no...	azidar
2015-04-24	Fixed performance bug in expand-when where equality between the consequence a...	azidar
2015-04-23	Fixed bug in lowering where the arguments to DoPrim and Pad weren't lowered	azidar
2015-04-23	Added new parser. Fixed all Tests. Added on-reset to parser, but don't correc...	azidar
2015-04-23	Fixed Pad inference bug	azidar
2015-04-22	Switched to stricter primop width constraints. Implemented Pad. Added some mi...	azidar
2015-04-20	Fixed tests to use new execution arguments. Added and fixed chisel3 bugs	azidar
2015-04-17	Removed excessive debug print statements, added default call to firrtl to gen...	azidar
2015-04-17	Added temp elimination pass	azidar
2015-04-17	Fixed bug in primop lowering during type inference. Added reduce instructions...	azidar
2015-04-09	Added more 'fake' tests. infer-widths now collects constraints	azidar
2015-04-08	Fixed bug in lowering that incorrectly determined genders when subfielded	azidar
2015-04-08	Finished expand whens. started infer widths. added pdf for people to view	azidar