sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-01-16	Fixed a bunch of tests, and minor bugs	azidar

2016-01-16	New memory works with verilog. Slowly changing tests and fixing bugs.	azidar
	Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
2015-08-24	Changed all tests to use verilog backend.	azidar

2015-07-31	Updated tests to pipe from stderr to stdout	azidar

2015-07-14	Added tests for clocks. Added remove scope and special chars passes. Added ↵	azidar
	tests. Made more tests pass
2015-05-19	Updated tests	azidar

2015-05-15	Updated firrtl for its passes to be a bit more modular, and to enable ↵	azidar
	plugging in other backends. Also updated a lot of tests, but not all of them because its annoying.
2015-04-23	Added new parser. Fixed all Tests. Added on-reset to parser, but don't ↵	azidar
	correctly handle it in compiler.
2015-04-22	Switched to stricter primop width constraints. Implemented Pad. Added some ↵	azidar
	missing primops
2015-04-20	Fixed tests to use new execution arguments. Added and fixed chisel3 bugs	azidar

2015-04-17	Removed excessive debug print statements, added default call to firrtl to ↵	azidar
	generate flo