sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-01-24	Fixed tests that broke from changing verilog backend and removing mask from ↵	azidar
	write mport declaration
2016-01-16	Finished first cut at new firrtl - time for testing! Chirrtl requires masks ↵	azidar
	to be specified with write and rdwr mports
2016-01-16	Fixed a bunch of tests, and minor bugs	azidar

2016-01-16	New memory works with verilog. Slowly changing tests and fixing bugs.	azidar
	Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
2015-08-24	Changed all tests to use verilog backend.	azidar

2015-07-31	Updated tests to pipe from stderr to stdout	azidar

2015-07-14	Added tests for clocks. Added remove scope and special chars passes. Added ↵	azidar
	tests. Made more tests pass
2015-07-14	Pass most tests. The ones that do not pass are not expected to, yet	azidar

2015-05-27	Added sequential memories. mem no longer exists, must declare either cmem or ↵	azidar
	smem. Added firrtl-gensym utility to generate a hashmap of names
2015-05-19	Updated tests	azidar