| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-08-17 | Change RW port names (#236) | Angie Wang | |
| * Updated FIRRTL spec + related code for readwrite ports. (write) data -> wdata & mask -> wmask for clarity * Also removed simple.fir that snuck into master branch. | |||
| 2016-05-24 | Add integration test for single-ported memory | jackkoenig | |
| 2016-03-15 | Revamp string literal handling | jackkoenig | |
| 2016-03-10 | Add support for right shift by amount larger than argument width | jackkoenig | |
| 2016-03-03 | Add some integration tests: successful compilation and execution | jackkoenig | |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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