| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-06-27 | Emitting reg update mux tree, only walk netlist for wires and nodes | Jack Koenig | |
| Fixes bug where the Verilog emitter could pull the next value for a register that feeds a second register, removing the first register from the second register's update. | |||
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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