| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-07-14 | Added tests for clocks. Added remove scope and special chars passes. Added ↵ | azidar | |
| tests. Made more tests pass | |||
| 2015-07-14 | Added clock support | azidar | |
| 2015-07-14 | Pass most tests. The ones that do not pass are not expected to, yet | azidar | |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. ↵ | azidar | |
| Added Long support so UInt(LARGENUMBER) works | |||
| 2015-05-27 | Added sequential memories. mem no longer exists, must declare either cmem or ↵ | azidar | |
| smem. Added firrtl-gensym utility to generate a hashmap of names | |||
| 2015-05-27 | Added external modules. Switched lower firrtl back to wire r; r := Register, ↵ | azidar | |
| instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed | |||
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar | |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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