sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2015-08-24	Changed all tests to use verilog backend.	azidar

2015-08-20	Added tests, cleaned up repo	azidar

2015-08-20	Added Poison node. Includes tests. #26.	azidar

2015-08-17	Removed leading zeros from UInt constants	azidar

2015-08-03	Changed name mangling to use _ as a delin. Fixed bug in checking for	azidar
	invalid <> assignments.
2015-07-31	Added errors for bulk connects where field names match but types/flips don't	azidar

2015-07-31	Updated tests to pipe from stderr to stdout	azidar

2015-07-30	Updated error and feature tests. Fixed bug in detecting incorrect genders	azidar

2015-07-30	Updated lots of tests so they pass. Found one bug in expand whens	azidar

2015-07-14	Added tests for clocks. Added remove scope and special chars passes. Added ↵	azidar
	tests. Made more tests pass
2015-07-14	Added clock support	azidar

2015-07-14	Pass most tests. The ones that do not pass are not expected to, yet	azidar

2015-06-02	Added sequential/combinational memories. Started debugging verilog backend. ↵	azidar
	Added Long support so UInt(LARGENUMBER) works
2015-05-27	Added sequential memories. mem no longer exists, must declare either cmem or ↵	azidar
	smem. Added firrtl-gensym utility to generate a hashmap of names
2015-05-27	Added external modules. Switched lower firrtl back to wire r; r := Register, ↵	azidar
	instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed
2015-05-26	Added <>. Added additional checks for primops. Added new chisel3 files.	azidar