sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-01-24	Added muxing on passive aggregate types	azidar

2016-01-16	Fixed a bunch of tests, and minor bugs	azidar

2016-01-16	WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit ↵	azidar
	roadblock in assigning clocked ports
2016-01-16	Finished supporting nested accesses. Required some nuianced thinking. Pass ↵	azidar
	all feature tests. Deleted CondRead because it tested a problem we don't have any more
2016-01-16	New memory works with verilog. Slowly changing tests and fixing bugs.	azidar
	Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
2015-08-24	Changed all tests to use verilog backend.	azidar

2015-08-20	Added tests, cleaned up repo	azidar