| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-08-24 | Changed all tests to use verilog backend. | azidar |
| 2015-07-31 | Added errors for bulk connects where field names match but types/flips don't | azidar |
| 2015-07-31 | Updated tests to pipe from stderr to stdout | azidar |
| 2015-07-14 | Pass most tests. The ones that do not pass are not expected to, yet | azidar |
| 2015-05-27 | Added sequential memories. mem no longer exists, must declare either cmem or ... | azidar |
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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