| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-02-09 | Changed stanza output of UInt/SInt to include widths. Made tests match accord... | azidar |
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar |
| 2015-08-17 | Removed leading zeros from UInt constants | azidar |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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