| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-10-01 | Updated tests for previous change that removed RemoveScope test from the ↵ | azidar | |
| StandardVerilogCompiler | |||
| 2015-08-24 | Changed all tests to use verilog backend. | azidar | |
| 2015-07-30 | Updated error and feature tests. Fixed bug in detecting incorrect genders | azidar | |
| 2015-05-20 | Added Pad pass to flo.stanza, which pads widths to make := and primops ↵ | azidar | |
| strict. Have not tested this | |||
| 2015-05-05 | Added a bunch of tests. In the middle of implementing check kinds and check ↵ | azidar | |
| types. Does not compile | |||
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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