| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-08-24 | Changed all tests to use verilog backend. | azidar | |
| 2015-05-20 | Added Pad pass to flo.stanza, which pads widths to make := and primops ↵ | azidar | |
| strict. Have not tested this | |||
| 2015-05-02 | Added a infrastructure for check passes, and wrote a few | azidar | |
 |
index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
| aboutsummaryrefslogtreecommitdiff |