| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-05-04 | Fixed change where type of mux-ss was incorrect | azidar |
| 2015-05-02 | Added a infrastructure for check passes, and wrote a few | azidar |
| 2015-05-02 | Now when expanding ConnectFrom/ToIndex, create a node for the index so it isn... | azidar |
| 2015-05-01 | Fixed performance bug where PlusWidth, MinusWidth, and ExpWidth could be simp... | azidar |
| 2015-05-01 | Fixed bug where the enable was looked at for lowering MUX. | azidar |
| 2015-04-29 | Fixed bug in lowering of subfields. Fixed ModuleVec.fir to be correct | azidar |
| 2015-04-28 | Instances are now male. Reworked lowering pass to be sane. chisel3/ModuleVec.... | azidar |
| 2015-04-22 | Added new test that breaks current parser. updated todo | azidar |
| 2015-04-21 | Added new test | azidar |
| 2015-04-20 | Fixed tests to use new execution arguments. Added and fixed chisel3 bugs | azidar |
| 2015-04-16 | Updated parser to correctly read empty statements | azidar |
| 2015-04-13 | new chisel3 tests | jackbackrack |
 |
index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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