| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-07-14 | Pass most tests. The ones that do not pass are not expected to, yet | azidar | |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. ↵ | azidar | |
| Added Long support so UInt(LARGENUMBER) works | |||
| 2015-05-21 | Added pad pass, used for flo backend | azidar | |
| 2015-05-02 | Now when expanding ConnectFrom/ToIndex, create a node for the index so it ↵ | azidar | |
| isn't duplicated for all the whens | |||
| 2015-05-01 | Fixed performance bug where PlusWidth, MinusWidth, and ExpWidth could be ↵ | azidar | |
| simplified earlier, and also now have equal? defined so mMaxWidth doesn't blow up during width inference | |||
| 2015-04-28 | Instances are now male. Reworked lowering pass to be sane. ↵ | azidar | |
| chisel3/ModuleVec.fir doesn't work because incorrecly generated? | |||
| 2015-04-20 | Fixed tests to use new execution arguments. Added and fixed chisel3 bugs | azidar | |
| 2015-04-16 | Updated parser to correctly read empty statements | azidar | |
| 2015-04-13 | new chisel3 tests | jackbackrack | |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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