| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-05-21 | Added pad pass, used for flo backend | azidar |
| 2015-05-02 | Now when expanding ConnectFrom/ToIndex, create a node for the index so it isn... | azidar |
| 2015-05-01 | Fixed performance bug where PlusWidth, MinusWidth, and ExpWidth could be simp... | azidar |
| 2015-04-28 | Instances are now male. Reworked lowering pass to be sane. chisel3/ModuleVec.... | azidar |
| 2015-04-20 | Fixed tests to use new execution arguments. Added and fixed chisel3 bugs | azidar |
| 2015-04-16 | Updated parser to correctly read empty statements | azidar |
| 2015-04-13 | new chisel3 tests | jackbackrack |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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