| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-07-14 | Added clock support | azidar | |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. ↵ | azidar | |
| Added Long support so UInt(LARGENUMBER) works | |||
| 2015-05-21 | Added pad pass, used for flo backend | azidar | |
| 2015-05-04 | Added new Control.fir with reduced padding | azidar | |
| 2015-05-02 | Added a infrastructure for check passes, and wrote a few | azidar | |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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