| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-07-14 | Added clock support | azidar | |
| 2015-06-12 | Major revisions to spec. Bumped to v0.1.2 | azidar | |
| 2015-06-03 | Fixed verilog backend bugs. Passes ALU. Fails Datapath | azidar | |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. ↵ | azidar | |
| Added Long support so UInt(LARGENUMBER) works | |||
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar | |
 |
index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
| aboutsummaryrefslogtreecommitdiff |