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2016-09-12Legalize bit select. Run Legalize after PadWidths.Jack
Bit selecting a literal resulted in invalid Verilog. Legalize now deals with this by replacing any bits select of UInt or SInt literals with a new literal composed of the selected bits. Legalize also is now run after PadWidths because that pass introduces this issue. Fixes #170
2016-09-12Change Legalize Connect to respect SIntJack
Legalize will wrap the rhs of a connect statement with a bit select primop if the lhs is of smaller width than the rhs. This bit select is now wrapped in a asSInt cast if the original rhs was an SInt so that is has the correct type. Fixes #173
2016-09-12Change Legalize Shift Right to respect SIntjackkoenig
Fix bug where Legalize was generating a bit select for SInts without then casting to SInt Fixes #169
2016-09-12Change bitWidth to support ClockTypejackkoenig
Match on GroundType instead of UIntType and SIntType
2016-09-12Add unapply for GroundTypejackkoenig
2016-09-12Change Mappers to Value Classesjackkoenig
2016-09-12Rework map functions as class methodsjackkoenig
Changed code from match statements in Mappers.scala to methods on the various IR classes. This allows custom IR nodes to implement the mapper functions and thus work (ie. not match error) when map is called on them. This also should have a marginal performance increase because of use of virtual function calls rather than match statements.
2016-09-12Added test to check invalid bug was fixedazidar
2016-09-12Fixed bug where nodes of Invalids where createdazidar
2016-09-12Bug fix -- remove all empty expressions after ReplSeqMem passes (#294)Angie Wang
* Bug fix -- remove all empty expressions after ReplSeqMem passes * Added test to make sure ReplSeqMem can handle BundleType SMem (EmptyExpression leakage)
2016-09-08Revert Expand Whens to process a set of connection lhsjackkoenig
2016-09-08Remove brittle ReplSeqMemTestjackkoenig
This test is breaks with any minor change to code generation. It should be replaced with a more robust test.
2016-09-08memoize nodes in ExpandWhensDonggyu Kim
2016-09-08remove Utils.{AND, OR, NOT, EQV}Donggyu Kim
hidden const props not desirable
2016-09-08clean up ExpandWhensDonggyu Kim
2016-09-08refactor RemoveCHIRRTLDonggyu Kim
2016-09-08refactor resolvesDonggyu Kim
2016-09-08refactor InferTypesDonggyu Kim
2016-09-08split Passes.scala into multiple files(InferTypes.scala, Resolves.scala, ↵Donggyu Kim
RemoveCHIRRTL.scala)
2016-09-08refactor InferWidthsDonggyu Kim
2016-09-07put InferWidths in a seperate file and fix spacesDonggyu Kim
2016-09-07refactor checksDonggyu Kim
2016-09-07clean up PrimOpsDonggyu Kim
2016-09-07clean up miscsDonggyu Kim
2016-09-07clean up WIR.scalaDonggyu Kim
2016-09-07Merge branch 'master' into cleanup_passesAdam Izraelevitz
2016-09-07clean up Emitter.scala (#275)Donggyu
2016-09-07clean up SplitExpressionsDonggyu Kim
2016-09-07clean up LowerTypesDonggyu Kim
2016-09-07clean up PullMuxes & ExpandConnectsDonggyu Kim
2016-09-07clean up Utils.scalaDonggyu Kim
remove unnecessary functions & change spaces
2016-09-07remove Utils.ONEDonggyu Kim
2016-09-07remove Utils.tpeDonggyu Kim
2016-09-07Utils.scala: remove vars with foldDonggyu Kim
2016-09-07Added ReplaceSubAccesses before RemoveSubAccessesazidar
2016-09-07add caches for create_exps in RemoveAccessDonggyu Kim
2016-09-07clean up RemoveAccessesDonggyu Kim
2016-09-06optimize equals of WrappedExpression & WrappedTypeDonggyu Kim
2016-09-06remove unnecessary mappers in NamespaceDonggyu Kim
there's a big stack overhead with mappers
2016-09-06replace flatMap with foldLeft in create_expsDonggyu Kim
internal implementation for flatMap seems to be inefficient
2016-09-06Address style feedback and add tests for getConnectOrigin utilityAngie
2016-09-06Support optionally filling write mask to data width via transform input ↵Angie
config file
2016-09-06Expanded annotations for valid memory sizesAngie
2016-09-06Edited conf generation to handle mem namespace collisionAngie
* Also started separate pass for annotating valid memory
2016-09-06Made the connect origin function more powerfulAngie
* It analyzes through statements that ConstProp would've optimized * Edge case wmask can be removed (pass tries harder to figure out that wmask = wen)
2016-09-06Added simple unit test for ReplSeqMemAngie
2016-09-06Added back support for conf writing.Angie
* Conf file info is passed in through annotations. * A pass should have its own set of sub-arguments delimited by :
2016-09-06Changed wmask to convert from VecType to UIntAngie
* Instead of filling the whole data width * Added helper functions in MemUtils
2016-09-06Replace DefMemories with wrapped black boxAngie
* Note, this version uses Albert's toBitMask function, * which expands the bit mask to be the full data width (similar to Chisel2 output) * Black boxes only have wmasks as needed
2016-09-06Pulled out duplicate memory annotationsAngie
* Annotate reference * Changed memory port names to RWx, Wx, Rx, etc. and reconnected nodes
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