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Fixes #990
h/t @pentin-as and @abejgonzalez
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This fixes issue #988
I tried one alternative to this fix: record the time to do a *no rename* run (`depth = 0`) and check that the time to do the *deep rename* (`depth = 500`) was a reasonable multiple of the *no rename* test. Unfortunately, the discrepancies were all over the map, sometime as much three orders of magnitude difference.
I decided the current fix was the simplest - don't enforce timing checks if we're doing coverage testing, although determining the latter is brittle.
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Previously, components that did not affect the output would cause
exceptions because they were missing from the label2group Map. This
commit treats them as "reachable" by the ports so they are included in
the default "ungrouped" group.
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This fixes an issue where expressions created by GroupComponents would
be improperly lowered because they were not marked as references to
instance ports.
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* Seal Direction trait
* Add WRef factories for ports and instances
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This adds a requirement that all Compilers must have at least one
Transform. Without this, there is no way to determine the inputForm or
outputForm of a given compiler as these are (rightly) defined in terms of
the head/last transform.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This changes the NoneCompiler to be a unary sequence consisting of an
IdentityTransform. This fixes the inputForm and outputForm inherited
methods that implicitly mandate a non-empty transform sequence.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds an identity transform that applies an identity function to some
CircuitState, i.e., it just returns the original CircuitState. This is
useful for transform generators that may, for edge cases, generate an
empty transform sequence. Other classes (e.g., Compiler) have explicit or
implicit requirements that a transform sequence is non-empty.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Give better error when mport references non-existent memory
* Closes #796
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This fixes a bug where DiGraph summation (using the `+` operator) would
mutate the DiGraph. This occurred because the underlying edges set was not
being cloned. This is fixed to explicitly clone the underlying edges set.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Iterating on a HashSet could cause identical modules (including
annotations) to not dedup
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* Added Foreachers
* Changed CheckTypes to use foreach
* Check widths now uses foreach
* Finished merge, added foreachers to added stmts
* Address reviewer feedback
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Where the high form compiler removes Chirrtl (and runs some checks),
this compiler does nothing but read in the circuit and then emit it
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This breaks firrtl.options.Stage into a small type hierarchy:
* Phase: something that transforms an AnnotationSeq
* Stage extends Phase: a Phase with a Command Line Interface
Some of the old "common options" (input annotation file and target
directory) are moved into firrtl.options and provided as part of the Stage
class. Stage will automatically preprocess an input annotation sequence to
resolve all input annotation files and add a default target directory.
Minor changes:
* Adds ViewException
* Stops mixing in the DoNotTerminateOnExit trait into the default Shell
parser
* Add StageOptionsView
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
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Huge performance improvement when you have lots of ports for a given
module. Also split up some long implicit argument lines.
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- Add firrtl.transforms.CombineCats
- Use CombineCats in LowFirrtlOptimization
- Modify Verilog emitter to allow for nested Cat DoPrims
- Modify firrtlEquivalenceTest to write input FIRRTL string to test directory
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TargetDirAnnotation was moved from firrtl to firrtl.stage. However, this
is only aliased as a val in the firrtl package object. This also needs to
be type aliased for matching against a type. This fixes a bug I ran across
in the visualizer.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This shows an example of using a RegisteredLibrary, with the appropriate
META-INF ServiceLoader entry, that adds options from the InferReadWrite
and ReplSeqMem transforms.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds a new package, "firrtl.options", that provides a framework for
working with options inside and outside FIRRTL.
Small changes:
- Make TerminateOnExit return the correct exit code
- Deprecate mutable TerminateOnExit
- Add immutable DoNotTermianteOnExit
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This changes the CheckTypes.UniferredWidth exception to include the pretty
printed Target that was uninferred and suggests to the user that they may
have forgotten to assign to it. This changes the CheckTypes pass to
communicate the necessary Target information during AST traversal such
that when an uninferred width is found, the Target is known and available.
This also adds one test checking the message of the UniferredWidth
exception.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds a pretty printer for firrtl.annotation.Target and associated
tests. This uses a tree-like output where the following target
~Circuit|Module/foo:Foo>ref.field[0] will serialize to:
circuit Circuit:
└── module Module:
└── foo of Foo:
└── ref.field[0]
This enables better error messages and a human readable syntax better than
the existing serialize method (and avoiding the need for users to
understand the Target serialization syntax), but that is not intended to
be deserialized nor space efficient.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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It is O(n) and every use is in an O(n) iteration resulting in O(n^2).
Same information can be extracted from create_exps which happens to also
be called at every use of get_flip.
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When constructing the black box helper file list (firrtl_black_box_resource_files.f), filter out Verilog header files (*.vh) - Fixes #917
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Formerly #865
Major Code Changes/Features Added:
Added Target trait as replacement for Named
Added TargetToken as token in building Target
Added GenericTarget as a catch-all Target
Added CircuitTarget, ModuleTarget, ReferenceTarget, and InstanceTarget
Added ResolvePaths annotation
Added EliminateTargetPaths (and helper class DuplicationHelper)
Updated Dedup to work with instance annotations
Updated RenameMap to work with instance annotations
DCE & ConstantProp extend ResolveAnnotationPaths
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This reverts commit 7e2f787e125227dc389d5cf1d09717748ecfed2e.
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Added Target, which now supports Instance Annotations. See #865 for details.
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This wraps interactions with a BlackBox resource file such that a
FileNotFoundException are wrapped in a BlackBoxNotFoundException and
rethrown. This provides a better, verbose error message to the user and avoids a
FileNotFoundException showing up as an internal FIRRTL error.
This adds tests that the expected exception is thrown for both
BlackBoxResourceAnno and BlackBoxResourceAnno.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This moves VerilogRename out of Passes.scala and genericizes it as the new
Transform KemoveKeywordCollisions. This new Transform will remove keywords
for arbitrary sets of reserved keyword.
This adds VerilogRename back as a class instead of an object.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Summary of changes to firrtl.passes.VerilogRename:
- Use "_" to mangle names that conflict with Verilog
keywords (previously "$")
- Rewrite to operate on the whole AST to propogate mangled ports and
module names
- Make VerilogRename a Transform (was previously a Pass)
- Renames are now propagated
- Adds documentation for new VerilogRename
This makes the VerilogRename Transform (previously a Pass) use an
underscore ('_') instead of a dollar sign ('$') to mangle names that
conflict with Verilog keywords. This prevents problems with potentially
buggy tools that are not expecting '$' in Verilog names.
This reimplements VerilogRename to be safe for name collisions that may
occur anywhere in the AST, e.g., in ports, module names, circuit names, or
in any statements/expressions. Previously, names were only mangled in
statements and in place. This resulted in problems where renames of ports
in a child's namespace would not be guaranteed to be mangled the same way
in a parent's namespace. The algorithm is reimplemented to walk all
modules in reverse topological order (from leafs to main) and relying on a
RenameMap to track name changes.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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