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2021-11-23Enable memory initialization in synthesis for FPGA targets (#2430)Carlos Eduardo
2021-11-23[deprecation clean up] Remove firrtl.Driver (#2419)Jiuyang Liu
Co-authored-by: sinofp <sinofp@tuta.io>
2021-11-23fix tests that depend on Driver (#2429)Jiuyang Liu
Co-authored-by: sinofp <sinofp@tuta.io>
2021-11-22remove firrtl.transforms.BlackBoxSourceHelper.fileListName. (#2426)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-22remove firrtl.transforms.InferResets.DifferingDriverTypesException (#2425)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-22remove firrtl.transforms.InlineAcrossCastsTransform. (#2424)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-22remove firrtl.FIRRTLException (#2421)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-22[deprecation clean up] remove deprecated API in firrtl.Utils (#2420)Jiuyang Liu
* remove firrtl.Utils.get_flip. * remove firrtl.Utils.indent.
2021-11-19Disable random init (#2396)Jiuyang Liu
* Add option to disable random mem/reg init Co-authored-by: Jiuyang Liu <liu@jiuyang.me> * fix for code review. Co-authored-by: SharzyL <me@sharzy.in>
2021-11-12Let firrtl based applications run despite loading unknown annotations (#2387)Chick Markley
An application like barstools may contain a main that loads an annotations file containing annotation classes that are not on it's classpath. This change allows unknown annotations to be preserved by wrapping them in a UnrecognizedAnnotation. If annotations are then output to a file, they will be unwrapped during serialization This feature can be enabled via an AllowUnrecognizedAnnotations annotation Co-authored-by: chick <chick.markley@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-11-10smt: fix handling of div primitive in formal backend (#2409)Kevin Laeufer
We never tested the case where the width of the numerator was less than the denominator. This should fix any issue with this combination.
2021-11-04BlackBoxSourceHelper: ensure trailing newline in .f file (#2405)Kevin Laeufer
2021-10-28typo: correct Error Info (#2398)SingularityKChen
+ correct the Error Info of "At least one dedupable annotation..."
2021-10-19Remove The WriteEmitted Phase (#2390)David Biancolin
2021-10-18Favor os-lib write.over in WriteEmitted (#2389)David Biancolin
2021-10-09Support parsing missing keywords as ids (#2381)Jack Koenig
Reset, AsyncReset, Interval, attach, assert, assume, and cover have all been added as keywords but not added to the allowlist for parsing as ids.
2021-10-04Add test of #2379 issue, NFCSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-10-04Hotfix for Vector Reg Init LegalizeConnects BugSchuyler Eldridge
Add a private pass, LegalizeConnectsOnly, that behaves like LegalizeConnects, but only pads connects instead of connects and register inits. Padding is necessary for ReplSeqMem, but ReplSeqMem runs before LowerTypes and vector registers can still exist at this point. Connects, conversely, are all blown out by ExpandConnects and can be safely, blindly treated as ground type. Fixes #2379. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-09-29TopWiring: filter out unnamed declarations when building source lists (#2376)David Biancolin
* Demonstrate a couple failing cases * Have TopWiring ignore unnamed declarations as potential sources
2021-09-29Have Flatten & InlineInstances remove their annotations (#2374)David Biancolin
* Have Flatten & InlineInstances remove their annotations * Format
2021-09-29Add RTLIL Backend. (#2331)Nicolas Machado
* Added RTLIL Backend. * Add test for Rtlil Backend, fix per-module file emission, scalafmt, and apply bugfixes for inconsistencies found during testing. * Fix build on scala 2.13 * Add additional equivalence test, make some bugfixes and perf opts to the emitter. * Final changes as requested by Kevin, code cleanup, add support for formal cells.
2021-09-23transforms.formal: ensure named statements as output (#2367)Kevin Laeufer
2021-09-14Fix multi-protobuf test when run multiple times (#2357)Jack Koenig
The test was leaving the test directory in a dirty state that would fail on a rerun. Fix the test so that it can be run multiple times in a row.
2021-09-13Bump Scala to 2.12.14 and 2.13.6 (#2356)Jack Koenig
This required also bumping sbt-scalafix to bring in a newer version of semanticdb. The new version of semanticdb had an issue with a regex in SMTLib, fixed by fixing the way '$' is escaped in the regex.
2021-09-11Remove BlackBoxSourceHelper from ReplaceMemTransform (#2355)Jack Koenig
BlackBoxSourceHelper should only run late in compilation to allow transforms to tweak its behavior (eg. changing BlackBoxTargetDirAnno).
2021-09-10MemConf: Do not add another new line when serializing (#2354)Megan Wachs
2021-09-08smt: make SMT + TransitionSystem lib public (#2350)Kevin Laeufer
2021-09-08smt: refactor SMT expression library (#2347)Kevin Laeufer
2021-09-08Multi protobuf module emission and consumption (#2344)Jared Barocsi
* Add compiler option (`-p`) to emit individual module protobufs * Implement multi module combination when reading directory of protobufs Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-08-30[smt] treat stop with non-zero ret like an assertion (#2338)Kevin Laeufer
We treat it as an assertion that the stop will never be enabled. stop(0) will still be ignored (but now demoted to a info from a warning).
2021-08-26Fix dshl zero-width shift behavior (#2339)Schuyler Eldridge
* Fix dshl zero-width shift behavior Add a special case for dshl handling in the ZeroWidths pass. If one expression is shifted by a second, zero-width expression, just return the first expression. This prevents a bug where the width will incorrectly expand due to zero-widths introducing a 1-bit zero expression. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * fixup! Fix dshl zero-width shift behavior
2021-08-21Add BufferedCustomFileEmission (#2334)Jack Koenig
Uses virtual method .getBytesBuffered: Iterable[Array[Byte]] to optimize file emission.
2021-08-20Fix Serializer for single indented DefModule emission (#2332)Jack Koenig
2021-08-13Modify NoCommonSubexpressionElimination to ↵胡波
NoCommonSubexpressionEliminationAnnotation (#2329) to make it has the same form with NoDCEAnnotation and NoConstantPropagationAnnotation
2021-08-10[smt] make SMTLib + Btor2 emitters public objects (#2326)Kevin Laeufer
This will make it easier for formal verification libraries to make use of these emitters.
2021-08-10[smt] PropagatePresetAnnotations is now a real prereq (#2325)Kevin Laeufer
2021-08-09PropagatePresetAnnotations: remove dep. on SplitExpressions and PadWidths ↵Kevin Laeufer
(#2324) Both transforms are (most likely) not needed.
2021-08-09PropagatePresetAnnotations: remove false prerequisites (#2323)Kevin Laeufer
The SMT backend actually needs to run PropagatePresetAnnotations (as will treadle at some point). None of the Verilog specific passes were actually required!
2021-08-09Implement NoCommonSubexpressionElimination (#2291)Jiuyang Liu
* implement NoCommonSubexpressionElimination to resolve chipsalliance/chisel3#2006 * Update src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-08-04Revert "Deprecate DependencyAPIMigration. (#2303)" (#2316)Kevin Laeufer
This reverts commit 2630537cf956eea3768c5bd8e57de839f7d3700a.
2021-08-03Require Andr, Orr, Xorr, Neg to have one operand (#2312)Schuyler Eldridge
Fix an OG bug where Andr, Orr, and Xorr would accept an arbitrary number of operands. Verilog emission doesn't support this and will silently drop all operands after the first. E.g., "andr(a, b)" would emit as "&a". After this commit, "andr(a, b)" will be rejected by checking passes. For archaeological purposes, this appears to have been the behavior dating back to when this was added in d2d3260a. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-08-02remove LoweringCompilersSpec (#2310)Kevin Laeufer
This has outlived its usefulness.
2021-08-02add emitter for optimized low firrtl (#2304)Kevin Laeufer
* rearrange passes to enable optimized firrtl emission * Support ConstProp on padded arguments to comparisons with literals * Move shr legalization logic into ConstProp Continue calling ConstProp of shr in Legalize. Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-07-29Dedup attribute annos (#2297)Jared Barocsi
* Add new util "groupByIntoSeq" * Restore annotation order when dedupping annotations * Attribute annotations now deduplicate * Implement doc string anno dedup Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-07-27Deprecate DependencyAPIMigration. (#2303)Jiuyang Liu
* deprecate DependencyAPIMigration.
2021-07-27ir: make HashCode.toHashString public (#2302)Kevin Laeufer
This will allow chiseltest to save the hash code to disk for the purpose of caching simulation binaries.
2021-07-25Add typedef in DependencyManager.Jiuyang Liu
This is a bug fix, before this PR, Scala compiler will infer `Nothing`, which makes code below failed to compile: ``` class UserCompiler extends TransformManager(Seq(Dependency(UserPass))) { override def optionalPrerequisiteOf: Seq[TransformDependency] = Seq( Dependency[DedupModules] ) } ```
2021-07-14Fix memory annotation deduplication (#2286)Jared Barocsi
* Add transform to deduplicate memory annotations * Add annotation deduplication to Dedup stage * ResolveAnnotationPaths and EliminateTargetPaths now invalidate the dedup annotations transform * Verilog emitter now throws exception when memory annotations fail to dedup Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-07-11Rm java.io in WriteEmitted (#2275)sinofp
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-07-11Deprecate BlackBoxResourceAnno (#2262)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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