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The SMT backend actually needs to run PropagatePresetAnnotations
(as will treadle at some point).
None of the Verilog specific passes were actually required!
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* implement NoCommonSubexpressionElimination to resolve chipsalliance/chisel3#2006
* Update src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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This reverts commit 2630537cf956eea3768c5bd8e57de839f7d3700a.
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Fix an OG bug where Andr, Orr, and Xorr would accept an arbitrary number
of operands. Verilog emission doesn't support this and will silently
drop all operands after the first. E.g., "andr(a, b)" would emit as
"&a". After this commit, "andr(a, b)" will be rejected by checking
passes.
For archaeological purposes, this appears to have been the behavior
dating back to when this was added in d2d3260a.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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This has outlived its usefulness.
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* rearrange passes to enable optimized firrtl emission
* Support ConstProp on padded arguments to comparisons with literals
* Move shr legalization logic into ConstProp
Continue calling ConstProp of shr in Legalize.
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add new util "groupByIntoSeq"
* Restore annotation order when dedupping annotations
* Attribute annotations now deduplicate
* Implement doc string anno dedup
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* deprecate DependencyAPIMigration.
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This will allow chiseltest to save
the hash code to disk for the purpose
of caching simulation binaries.
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This is a bug fix, before this PR, Scala compiler will infer `Nothing`, which makes code below failed to compile:
```
class UserCompiler extends TransformManager(Seq(Dependency(UserPass))) {
override def optionalPrerequisiteOf: Seq[TransformDependency] = Seq(
Dependency[DedupModules]
)
}
```
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* Add transform to deduplicate memory annotations
* Add annotation deduplication to Dedup stage
* ResolveAnnotationPaths and EliminateTargetPaths now invalidate the dedup annotations transform
* Verilog emitter now throws exception when memory annotations fail to dedup
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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The pass injects pipe registers immediately after the declaration of the
memory. This can be problematic if the clock for the associated memory
port is defined after the declaration of the memory. For any memory port
clocks that are driven by non-ports, we now inject a wire before the
pipe register declarations to be sure there are no
use-before-declaration issues.
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* Restore parsed MultiInfo structure in firrtl parser
* Change erroneous expected output in InfoSpec test
FileInfo compression sorts the outputted entries alphabetically, but
this test did not reflect that fact
* Fix typo in comment
* Add unit tests for file locator parsing
* Fix syntax issues and typos
* More redundant braces removed
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* smt: include firrtl statement names in SMT and btor2 output
* smt: remove println
* smt: make tests run again and fix stale ones
Apparently `private` classes aren't found by th sbt test runner.
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Add a new option to the FIRRTL compiler, "--start-from = <form>". If
used, this will cause the compiler to assume that the input FIRRTL
circuit is already in the specific form. It will then skip unnecessary
passes given this information.
E.g., if a user requests to run "firrtl -X verilog --start-from low"
then the compiler will only run transforms necessary to get from low
FIRRTL to Verilog. Transforms necessary for ingesting FIRRTL IR will be
run if needed (checks and type/kind/flow resolution).
To implement this, a CurrentFirrtlStateAnnotation is added. Advanced
users can use this directly to tell the FIRRTL compiler exactly what
transforms have already been run, including the ability to ignore checks
or type/kind/flow resolution if they so desire.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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* Add Protocol Buffer emission export
This adds infrastructure and annotations that let a user emit a FIRRTL
circuit as a Protocol Buffer.
Fixes #1696.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* fixup! Add Protocol Buffer emission export
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* make PresetRegAnnotation public
this annotation is useful outside the firrtl compiler:
- to implement a pass that creates registers which
need to be initialized at the beginning of simulation
(e.g., for formal verification)
- to support preset registers in treadle
* add PresetRegAnnotation test and deal with annotation correctly in RemoveReset pass
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Add a compiler/emitter that can target minimal high form. This will
produce output that only has CHIRRTL constructs removed.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Requested by reviewer.
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* ReplaceMemMacros: add target rename test case
* ReplaceMemMacros: rename references to instances
* fix renaming for deduped mems
* use grouped DummyAnnos to preserve order
* Apply suggestions from code review
Co-authored-by: Jack Koenig <koenig@sifive.com>
* run scalafmt
* flatten targets
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add GenVerilogMemBehaviorModelAnno & vlsiMemGen
* Add CLI support for GenVerilogMemBehaviorModelAnno
* Add simple test for GenVerilogMemBehaviorModelAnno
* Fix for review
1. rename case class Port(prefix, `type`) to Port(prefix, portType)
2. fix AnnotatedMemoriesAnnotation collect function.
3. fix bug that ModuleName is not correct.
* Format DumpMemoryAnnotations & ReplSeqMemTests
* Fix for review
1. Inline genDecl, genPortSpec, genSequential, genCombinational
2. Add DefAnnotatedMemory informations in header
3. Change helpText
4. Check output Verilog by Verilator, the code is from FirrtlRunners#lintVerilog
* Fix ReadWritePort mask name
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* add more inline renaming test cases
* InlineInstances: fix renaming for local targets
* run scalafmt
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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LowerTypes creates a lot of mappings for the RenameMap. The built-in
.distinct of renames becomes a performance program for designs with
deeply nested Aggregates. Because LowerTypes does not create duplicate
renames, it can safely eschew the safety of using .distinct via a
private internal API.
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* add os-lib to dependency.
* use os-lib in Z3ModelChecker
* fix for review by Kevin.
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This function will safely wrap any unserializeable annotations in
UnserializeableAnnotations so that they can be safely serialized to JSON
for logging.
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* Implement MFC-style source locator compression
* Fix formatting issues
* Fix emitting empty FileInfo if the firrtl doesn't have one
* Remove '.scala' requirement in FileInfo parsing regex
* Handle parsing of FileInfos with no line/col nums
* Split FileInfos only if they match
This should fix any issues with FileInfos that do not use the "file line:col"
format, and allow any valid firrtl using these info comments to compile.
* Add unit tests for locator compression
* Move InfoTests to InfoSpec class
* Fix existing unit tests with fileinfo comments
* Add unit tests to ignore the algorithm's own output
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* remove all deprecations, switch to new API.
* Add MemLibOutConfigFileAnnotation to replace ConfWriter.
* Inline CreateMemoryAnnotations in ReplSeqMem.
* Dont use ConfWriter anymore.
* Fix ReplSeqMemTests, rewrite checkMemConf to directly read from annoation.
* Fix for review.
0. Since DependencyAPI only initiate transform only once, ListBuffer is
dangerous to use, remove defAnnotatedMemories from Transform.
1. Add trait HasAnnotatedMemories to store ListBuffer,
MemLibOutConfigFileAnnotation also extends from which now.
* Use two annotations converting and storing DefMemory.
0. rewrite CreateMemoryAnnotations to match ReplSeqMemAnnotation
creating PinAnnotation.
1. add DumpMemoryAnnotations to convert from
AnnotatedMemoriesCollectorAnnotation to MemLibOutConfigFileAnnotation
2. refactor MemLibOutConfigFileAnnotation and remove
HasAnnotatedMemories
3. add private AnnotatedMemoriesCollectorAnnotation to store mutable
DefAnnotatedMemory
4. change ReplSeqMem to SeqTransform
* Fix for review.
0. replace AnnotatedMemoriesCollectorAnnotation with immutable
AnnotatedMemoriesAnnotation.
1. add ListBuffer[DefAnnotatedMemory] in ReplaceMemMacros.execute.
* private functions in ReplaceMemMacros transform.
* scalafmt
* remove ConfWriter API.
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Looks like a typo/auto-merge hiccup.
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With Stage/Phase, users can provide complex functionality at the phase
level rather than just the transform level. It is useful to have the
same logging information at that level. Note that this change still logs
transforms in the same way, but now the time in inclusive of annotation
renaming which can also [unfortunately] be slow.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Fixes #2173
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Constant propagation of the Xor op folds `xor(a, SInt(0))` to
`asUInt(a)`. For comparison, Or folds to `asUInt(pad(a, W))`. This can
be a problem in the following case:
circuit Foo :
module Foo :
input a: UInt<3>
output b: UInt<4>
b <= asUInt(xor(asSInt(a), SInt<4>(0)))
This would emit the assignment as `b = a` instead of the sign-extended
`b = {{1{a[2]}},a}`.
This requires adjusting the `pad(e, t)` function use in const prop,
which currently just inserts a `Pad` prim op with the requested output
type. However, the function advertises that it pads *to the width* of
the type `t`. Some of the folds rely on this and request the padding of
a SInt<N> to the width of a UInt<M>. But the current implementation then
then actually returns a `Pad` op with type UInt<M>, instead of the
SInt<M> that was requested.
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Using Utils.indent() gives deprecation warnings to use Serializer instead. However,
the Serializer class itself doesn't provide a means to manually indent a FirrtlNode
string a certain number of times.
The indent variable, previously hardcoded to 0, is now exposed as a second parameter
for the modified serialize function, and the old serialize function just calls the
modified serialize with indents = 0 for binary compatibility
Co-authored-by: Megan Wachs <megan@sifive.com>
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* bitWidth: add scaladoc
* smt: use existing bitWidth API
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To maintain binary compatibility, InlineAcrossCasts is just aliases to
the now deprecated InlineCasts. We can make the binary incompatible
change of renaming the class and object for 1.5.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Update name of FPGA flag based on Jack's comment
* Add Scaladoc to describe what each constituent transform does
* Add SeparateWriteClocks to --target:fpga
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